322164

3.1.3 Intel ® VT-d Objectives ............................................................................30
3.1.4 Intel ® VT-d Features...............................................................................30
3.1.5 Intel ® VT-d Features Not Supported..........................................................31
3.2 Intel ® Trusted Execution Technology (Intel ® TXT) .................................................31
3.3 Intel ® Hyper-Threading Technology .....................................................................32
3.4 Intel ® Turbo Boost Technology ............................................................................32
4 Power Management .................................................................................................33
4.1 ACPI States Supported .......................................................................................33
4.1.1 System States........................................................................................33
4.1.2 Processor Core/Package Idle States...........................................................33
4.1.3 Integrated Memory Controller States.........................................................33
4.1.4 PCI Express* Link States .........................................................................34
4.1.5 Interface State Combinations ...................................................................34
4.2 Processor Core Power Management ......................................................................34
4.2.1 Enhanced Intel ® SpeedStep ® Technology ..................................................34
4.2.2 Low-Power Idle States.............................................................................35
4.2.3 Requesting Low-Power Idle States ............................................................36
4.2.4 Core C-states .........................................................................................37
4.2.4.1 Core C0 State ...........................................................................37
4.2.4.2 Core C1/C1E State ....................................................................37
4.2.4.3 Core C3 State ...........................................................................38
4.2.4.4 Core C6 State ...........................................................................38
4.2.4.5 C-State Auto-Demotion ..............................................................38
4.2.5 Package C-States ...................................................................................38
4.2.5.1 Package C0 ..............................................................................40
4.2.5.2 Package C1/C1E........................................................................40
4.2.5.3 Package C3 State ......................................................................40
4.2.5.4 Package C6 State ......................................................................40
4.3 Integrated Memory Controller (IMC) Power Management.........................................41
4.3.1 Disabling Unused System Memory Outputs.................................................41
4.3.2 DRAM Power Management and Initialization ...............................................41
4.3.2.1 Initialization Role of CKE ............................................................41
4.3.2.2 Conditional Self-Refresh .............................................................41
4.3.2.3 Dynamic Power Down Operation..................................................42
4.3.2.4 DRAM I/O Power Management ....................................................42
4.4 PCI Express* Power Management ........................................................................42
5 Thermal Management ..............................................................................................43
6 Signal Description....................................................................................................45
6.1 System Memory Interface ...................................................................................46
6.2 Memory Reference and Compensation ..................................................................48
6.3 Reset and Miscellaneous Signals ..........................................................................48
6.4 PCI Express* Based Interface Signals ...................................................................49
6.5 DMI—Processor to PCH Serial Interface.................................................................49
6.6 PLL Signals .......................................................................................................50
6.7 Intel ® Flexible Display Interface Signals ...............................................................50
6.8 JTAG/ITP Signals ...............................................................................................51
6.9 Error and Thermal Protection...............................................................................52
6.10 Power Sequencing .............................................................................................53
6.11 Processor Core Power Signals ..............................................................................53
6.12 Graphics and Memory Core Power Signals .............................................................55
6.13 Ground and NCTF ..............................................................................................56
6.14 Processor Internal Pull Up/Pull Down ....................................................................56
4 Datasheet, Volume 1