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7.10.2 Input Device Hysteresis Electrical Specifications The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design. Figure 7-2. Input Device Hysteresis . VTTD Maximum VP Minimum VP Maximum VN Minimum VN PECI Ground PECI High Range PECI Low Range 74 Datasheet, Volume 1 § § Minimum Hysteresis Valid Input Signal Range
Processor Land and Signal Information 8 Processor Land and Signal Information 8.1 Processor Land Assignments The processor land-map quadrants are shown in Figure 8-1 through Figure 8-4. Table 8-2 provides a listing of all processor lands ordered alphabetically by pin name. Not all signals listed in this chapter are used by the processor. Table 8-1 lists the signals that are not used by the Intel Core i7-800 and i5-700 desktop processor series. The signals are included for reference to define all LGA 1156 land locations. These signals will be used by future processors that are compatible with LGA 1156 platforms. Table 8-1. Signals Not Used by the Intel ® Core i7-800 and i5-700 Desktop Processor Series Interface Signals Not Used Intel Flexible Display Interface Integrated Graphics Core Power Memory Memory Interface:, ECC Related Memory Interface: RDIMM Related FDI_FSYNC[1:0] FDI_LSYNC[1:0] FDI_INT FDI_TX[7:0] FDI_TX#[7:0] GFX_DPRSLPVR GFX_IMON GFX_VID[6:0] GFX_VR_EN VAXG SA_DM[7:0] SB_DM[7:0] SA_ECC_CB[7:0] SB_ECC_CB[7:0] SA_DQS[8]/SA_DQS#[8] SB_DQS[8]/SB_DQS#[8] SA_CS#[7:4] SB_CS#[7:4] Datasheet, Volume 1 75
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Intel ® Core i7-800 and i5-700 Des
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Contents 1 Introduction............
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7 Electrical Specifications .......
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7-9 Control Sideband and TAP Signal
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Introduction 1 Introduction The Int
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Introduction 1.1 Processor Feature
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Introduction nonzero) with an Unsup
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Introduction 1.6 Terminology Term D
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Introduction 1.7 Related Documents
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Interfaces 2 Interfaces This chapte
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Interfaces 2.1.3.2 Dual-Channel Mod
Page 23 and 24: Interfaces 2.1.5 Technology Enhance
Page 25 and 26: Interfaces Figure 2-4. Packet Flow
Page 27 and 28: Interfaces 2.2.3 PCI Express* Ports
Page 29 and 30: Technologies 3 Technologies 3.1 Int
Page 31 and 32: Technologies 3.1.5 Intel ® VT-d Fe
Page 33 and 34: Power Management 4 Power Management
Page 35 and 36: Power Management — All active pro
Page 37 and 38: Power Management Note: The P_LVLx I
Page 39 and 40: Power Management The processor exit
Page 41 and 42: Power Management 4.3 Integrated Mem
Page 43 and 44: Thermal Management 5 Thermal Manage
Page 45 and 46: Signal Description 6 Signal Descrip
Page 47 and 48: Signal Description Table 6-3. Memor
Page 49 and 50: Signal Description Table 6-5. Reset
Page 51 and 52: Signal Description 6.8 JTAG/ITP Sig
Page 53 and 54: Signal Description 6.10 Power Seque
Page 55 and 56: Signal Description 6.12 Graphics an
Page 57 and 58: Electrical Specifications 7 Electri
Page 59 and 60: Electrical Specifications Table 7-1
Page 65 and 66: Electrical Specifications 7.7 Test
Page 69 and 70: Electrical Specifications Figure 7-
Page 73: Electrical Specifications 7.10 Plat
Page 77 and 78: Processor Land and Signal Informati
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