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Table 4-6. Targeted Memory State Conditions Mode Memory State with External Graphics 4.3.2.3 Dynamic Power Down Operation Power Management C0, C1, C1E Dynamic memory rank power down based on idle conditions. C3, C6 Dynamic memory rank power down based on idle conditions If there are no memory requests, then enter self-refresh. Otherwise, use dynamic memory rank power down based on idle conditions. S3 Self Refresh Mode S4 Memory power down (contents lost) Dynamic power-down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down. The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state. The processor core controller can be configured to put the devices in active power down (CKE de-assertion with open pages) or precharge power down (CKE de-assertion with all pages closed). Precharge power down provides greater power savings but has a bigger performance impact, since all pages will first be closed before putting the devices in power down mode. If dynamic power-down is enabled, all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh. 4.3.2.4 DRAM I/O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference. This includes all signals associated with an unused memory channel. Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM control signals, such as CS#, CKE, and ODT for unpopulated DIMM slots. The I/O buffer for an unused signal should be tristated (output driver disabled), the input receiver (differential sense-amp) should be disabled, and any DLL circuitry related ONLY to unused signals should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled). 4.4 PCI Express* Power Management • Active power management support using L0s, and L1 states. • All inputs and outputs disabled in L3 Ready state. 42 Datasheet, Volume 1
Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7). § § Datasheet, Volume 1 43
Page 1 and 2: Intel ® Core i7-800 and i5-700 Des
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: 7 Electrical Specifications .......
Page 7 and 8: 7-9 Control Sideband and TAP Signal
Page 9 and 10: Introduction 1 Introduction The Int
Page 11 and 12: Introduction 1.1 Processor Feature
Page 13 and 14: Introduction nonzero) with an Unsup
Page 15 and 16: Introduction 1.6 Terminology Term D
Page 17 and 18: Introduction 1.7 Related Documents
Page 19 and 20: Interfaces 2 Interfaces This chapte
Page 21 and 22: Interfaces 2.1.3.2 Dual-Channel Mod
Page 23 and 24: Interfaces 2.1.5 Technology Enhance
Page 25 and 26: Interfaces Figure 2-4. Packet Flow
Page 27 and 28: Interfaces 2.2.3 PCI Express* Ports
Page 29 and 30: Technologies 3 Technologies 3.1 Int
Page 31 and 32: Technologies 3.1.5 Intel ® VT-d Fe
Page 33 and 34: Power Management 4 Power Management
Page 35 and 36: Power Management — All active pro
Page 37 and 38: Power Management Note: The P_LVLx I
Page 39 and 40: Power Management The processor exit
Page 41: Power Management 4.3 Integrated Mem
Page 45 and 46: Signal Description 6 Signal Descrip
Page 47 and 48: Signal Description Table 6-3. Memor
Page 49 and 50: Signal Description Table 6-5. Reset
Page 51 and 52: Signal Description 6.8 JTAG/ITP Sig
Page 53 and 54: Signal Description 6.10 Power Seque
Page 55 and 56: Signal Description 6.12 Graphics an
Page 57 and 58: Electrical Specifications 7 Electri
Page 59 and 60: Electrical Specifications Table 7-1
Page 65 and 66: Electrical Specifications 7.7 Test
Page 69 and 70: Electrical Specifications Figure 7-
Page 73 and 74: Electrical Specifications 7.10 Plat
Page 75 and 76: Processor Land and Signal Informati
Page 93 and 94:
Processor Land and Signal Informati
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