Tachyon

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brion.com
Tachyon
LAD
A COMPREHENSIVE SOLUTION FOR HIGH FIDELITY
LITHOGRAPHY MODELING DURING THE INTEGRATED
CIRCUIT (IC) DESIGN IMPLEMENTATION PHASE
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Tech node,
litho layer GDSII layout
Tachyon Lithography-Aware Design (LAD)
sets new standards for fast, accurate and
robust lithography modeling in the IC
implementation flow. Discover and correct
design induced lithography hot spots
before tapeout. Extract more from your target process - performance, density
and yield with lower power. Tachyon LAD is compatible with existing design
flows and tools.
Built on a Solid Foundation
Brion Technologies, an ASML company, is the largest, fastest growing pure-play computational lithography
company in the industry. More customers have qualified Brion’s process window lithography verification
model than any other company’s. Brion also represents an emerging standard for optical proximity
correction (OPC) generation.
With such a deep core competency in post-tapeout lithography modeling and optimization, Brion is the
perfect partner to bring this information to the pre-tapeout IC implementation flow. Using Tachyon LAD,
designers can now discover and correct a wide range of design-induced lithography hot spots before
tapeout. Timing analysis is also enhanced, resulting in better performing designs with reduced time
to volume.
Early Adoption
IC Design Flow
Layout Editor
/ Viewer
Place and
Route
Timing
Analysis
Model - Based
DRC
Calibrating semiconductor lithography models is a long, time consuming and error-prone task. Tachyon LAD
makes maximum use of the same calibrated and robust models used in today’s advanced wafer
manufacturing facilities. No new models and no model availability time lag.
Silicon contours,
hot spot markers,
fixing hints

Tachyon LAD
LAD Product Features
Accurate Full Process-Window Modeling
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The same fully calibrated models
are used in OPC generation and
OPC verification
■ Fast modeling for the entire process -
mask, optics, resist and etch
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Mask and wafer process
variability analysis
Dense image-based computation
Inputs to Third Party EDA Tools
■ Cross-process window contours
with and without mask CD errors
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Lithography manufacturability hot
spot check reports (contours and
hot spot markers)
■ Hot spot resolutions
Speed and Performance
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Fully integrated hardware
accelerated platform for full
chip applications
Fast, predictable turnaround time
Linearly scales with chip area
Linearly scales with leaf node
additions
Insensitive to design hierarchy,
pattern complexity and file size
Applications Include
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Library and memory
cell optimization
Full chip place and
route optimization
Timing analysis
Model based design rule check
(DRC) sign-off
Real-time contour review for
custom layout and RET review
Tachyon LAD is architected to interface easily to existing IC
implementation and verification tools. Users will be able to upgrade their
existing flows to support critical manufacturing information. Tachyon LAD
communicates this information in a form that is familiar to designers –
GDSII compatible data with hot spot markers. While the analysis engines
inside Tachyon LAD contain detailed lithography information, that
complexity is hidden from the user.
No new models to verify, no new tools to adopt, no new technology to
learn, just manufacturable, robust designs.
Unified Models, Simplified Analysis
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Computational Lithography Enabled Design & Manufacturing
Library
Custom
Layout
P&R
Design Intent
Extraction
Power
Timing
Process Information
DRC
LVS
CL
Model
Process window
Process window
RET
OPC
LMC
Mask
Data
Prep
MEEF defects
Hot spots
Statistics
Thru-PW defects
Full chip contour Thru PW defects
Hot spots
Process Information
Mask
Writer
Mask
Inspect
Mask
Metrology
Design Intent
The same process model used
in the entire design to manufacturing flow
Wafer
Scanner
Wafer
Metrology
With Tachyon LAD, there is now one accurate and production proven
model used throughout the entire design and manufacturing flow. Clear
manufacturability ownership is established. Lithography process models
and resolution enhancement techniques (RET) are owned by the Fab;
chip performance and robustness are owned by the designer.
Tachyon LAD is being integrated with third party EDA tools and design
flows through a well defined client-server interface architecture. Ask your
EDA vendor about Tachyon LAD support today.
Brion Technologies, Inc.
Phone: +1 (408) 653-1500
Email: info@brion.com
brion.com
© 2007 Brion Technologies, Inc. All rights reserved.