Tachyon DDL & Tachyon DPT

Tachyon DDL & Tachyon DPT
Description
Tachyon DDL & Tachyon DPT offer comprehensive low-k 1
computational lithography solutions.
As the semiconductor industry enters the ultra low-k 1
era,
strong resolution enhancement technology (RET) techniques
such as Double Dipole Lithography (DDL) and Double
Patterning Technology (DPT) are required to continue along
the path of Moore’s Law. Built on Tachyon’s high performance
computing platform, Tachyon DDL and Tachyon DPT, along
with Tachyon OPC+ and Tachyon LMC, deliver complete
and production-worthy end-to-end solutions for the low-k 1
computational lithography needs of sub-28 nanometers (nm)
and below devices.
Key Benefits
High performance architecture
Tachyon DDL and Tachyon DPT are built on the highly
successful Tachyon platform, with proven image-based
computing and focus-exposure modeling (FEM). Tachyon’s
industry-leading high performance platform enables fast and
efficient implementation of computationally intensive DDL
and DPT for full-chip advanced logic and memory applications
for sub-28 nm process generations. Tachyon DDL and
Tachyon DPT are a complete solution suite for the
production-worthy implementation of DDL and DPT
technology, delivering ultrahigh capacity, fast turnaround
time, and industry-leading accuracy.
Full model-based solution
Tachyon DDL and Tachyon DPT use patented model-based
approaches throughout the flow to replace steps that
conventionally would have been rule-based decomposition
method. Accurate model simulations are conducted from
design horizontal and vertical conversion, shielding generation,
optical proximity correction (OPC), mask rule compliance
(MRC) to pattern stitching, delivering the most robust
solutions in one integrated step, thereby eliminating any
guesswork and manual iterations. Tachyon DDL and
Tachyon DPT are enabled by highly accurate focusexposure
models and separate etch models.
Leading-edge technology
Tachyon DDL based on ASML’s patented Double Dipole Lithography
technology which improves resolution while reducing
manufacturing cost. The technology can be applied to different
patterning needs, including logic and memory designs, for both
front-end and back-end processes.
Tachyon DDL also supports generic double exposure techniques
in which a design is split into two masks that are optimized to
their respective imaging conditions to yield the best possible
process window.
Tachyon DPT uses innovative algorithms and proprietary methods
to deliver full-chip global coloring, pitch-aware decomposition,
gate and overlay-aware pattern split, stitching, and pattern
density balance. It has a built-in capability to flag native conflicts,
allowing customers to build on their design for manufacturing
(DFM) framework. Tachyon DPT supports all process technologies
including photo freeze, litho-etch-litho-etch, and spacer
techniques, and supports both positive tone and negative
tone processes.
High quality output
Tachyon DDL and Tachyon DPT co-optimize critical quality
metrics including critical dimension (CD) control, mask
error enhancement factors (MEEF), and overlay error
tolerance throughout the entire flow, while carefully
maintaining the mask manufacturing constraints. The
results are reliable production-quality mask designs with
high accuracy and through-process window robustness.
Ready to be deployed
Tachyon DDL and Tachyon DPT are complete end to-end
solutions that convert any full-chip design into manufacturable
mask layouts. The resulting output data is ready for Tachyon
LMC (Lithography Manufacturability Check), fracturing and
mask data preparation. Together with Tachyon SMO (Source
Mask Optimization), which optimizes the imaging conditions
for each of the masks, Tachyon DDL and Tachyon DPT
provide users with a complete, production-worthy computational
lithography optimization suite to provide a cost effective
low-k 1
solution.
Process Window & Process Control

Litho-etch
M1 example:
k 1
= 0.31
NA=1.2
35 DX+DYX,Y
polarization
Litho-etch
Poly example:
k 1
= 0.3
NA=0.93
NA, sigma out/sigma in=0.95/0.71,
60 DX+DY, X,Y
polarization
Tachyon DDL uses model simulations and innovative algorithms to automatically decompose the design into two optimal masks which provide the best
final image quality and process window robustness. The technique can be applied to both logic and memory style designs to achieve k 1
< 0.3 imaging.
Tachyon DPT performs global coloring,
pattern split, model-based stitching
compensation, SRAF placement, and
model-based OPC all in one integrated flow,
reducing the development and computational
cost of implementing the technology.
Process Window & Process Control

Functions and Features
Double exposure lithography implementation
• Supports ASML-patented double dipole
lithography technology
• Supports generic double exposure
lithography technology
• Complete model-based full-chip pattern decomposition
• Source polarization for contrast improvement
• Process window optimized SRAF placement and
guaranteed SRAF non-printability
• Binary,attenuated phase shift, and tri-tone masks
• Simultaneous shielding and OPC optimization on
two masks
• Co-optimized shielding for optimal ILS and side
lobe margin
• Intelligent ripple control for complex 2D structures
• Production proven
Double patterning technology implementation
• Full-chip Litho-DPT and Spacer-DPT
• Efficient full-chip global coloring without coloring
conflict propagation
• Programmable geometry specific coloring
• Gate-aware pattern split
• Pitch-aware coloring
• Model-based and rule-based stitching compensation
• Overlay error tolerant and MEEF-aware
stitching compensation
• Process window model-based OPC with resist and/or
etch model
• Automatic density balancing for contact Litho-DPT
• Native conflict identification and conflict loop analysis
• Native conflict resolution for cell optimization
• Supports positive tone and negative tone DPT processes
Red: Pinching without overlay aware stitching
Blue: Optimal contour with overlay aware stitching
5 nm x overlay error 5 nm x and 5 nm overlay error
Without proper overlay error tolerance stitching, small overlay errors
combined with a slight defocus could result in serious pinching, thereby
killing the device yield.
split/stitch
Production-ready quality
• Process window-aware correction
• Built-in MRC for output masks
Efficiency and cycle time performance
• Fully integrated (single step) flow on a common platform
• Fully distributed layout decomposition and modelbased
OPC
• Hierarchical support for higher throughput
• Built-in innovative algorithms for optimal cycle
time performance
Flexibility and ease of use
• Full model-based approach that requires no fine tuning
and maintaining of complex rules
• Complete ready-to-use, built-in algorithms and optimal
mask designs for robust process window
• Fully parameterized user input and script-driven flow
• Programmable customization via easy scripting to meet
users’ special needs
Tachyon DPT employs overlay error tolerance model-based stitching error
compensation. The resulting design is free of overlay error induced issues under
normal manufacturing conditions.
Process Window & Process Control

22 nm
NA=1.35
sigma out/sigma in=0.77/0.97
60 DX+DY
Regular DDL Split and OPC
DDL with Intelligent Ripple Control
Tachyon DDL’s model-based shielding and intelligent ripple control overcomes the difficulty with the traditional rule-based splitting method to control
the ripples in complex 2D structures
DPT
SPT split
Model-based
OPC with
overlay aware
stitching
Tachyon
LMC
Tachyon DPT together Tachyon OPC+ and Tachyon LMC provides a complete spacer double patterning flow from mask split, mask correction,
and overlay aware verification
© 2010 Brion Technologies, Inc. All rights reserved.
Brion Technologies, Inc. • Phone: +1 (408) 653-1500 • Email: info@brion.com • brion.com
Process Window & Process Control