Topic 4

TOPIC 4 FLIP FLOP

Flip-flop definition:
•
flip-flop or latch is a circuit that has two
stable states and can be used to store
state information.
•
Flip-flops or latches are used as data storage
elements
•
The circuit can be made to change state
by signals applied to one or more control
inputs and will have one or two outputs.
•
It is the basic storage element
in sequential logic.

•
Data storage
Flip-flop Aplications
•
Timing operation
•
Counting purpose (JK flip-flop and T
flip-flop)
•
Flip-flop (D flip flop) can be used as
frequency divider.

Flip-flop Types
1. SR flip flop:
a) An active HIGH SR Flip-flop
b) An active LOW SR Flip-flop
c) Clocked SR Flip-flop
2. JK flip flop
a) Basic JK Flip-flop
b) JK Flip-flop With PRESET and CLEAR.
3. T flip flop

Introduction of Flip-flops
Triggered
•
The state of a flip-flop is changed by a momentary change
in the input signal.
•
This change is called a trigger and the transition it causes
is said to trigger the flip-flop.
•
The basic circuits of Figure 1 and Figure 2 require an input
trigger defined by a change in signal level.
•
This level must be returned to its initial level before a
second trigger is applied.
•
Clocked flip-flops are triggered by pulses.

Introduction of Flip-flopsTriggered
•
Clock is usually a square wave
•
The clock pulse goes through two signal transitions: from 0 to
1 and the return from 1 to 0. As shown in figure below, the
positive transition is defined as the positive edge and the
negative transition as the negative edge.
Definition of clock pulse transition

Synchronous vs Asynchronous
•
Almost all Logic “Chips” Include a Clock
•
The Clock helps to “Synchronize” the
Operation of the Circuits.
•
The “Clock” is simply a very regular Hi/Lo
Pulse train
•
Logic Forms are divided into two groups:
– SYNCHRONUS → Depend on Clock
– Asynchronous → NO Clock-Dependency

An Active HIGH SR Flip-flop
• Logic symbol:
• Logic circuit:
S
R
Q
Q
'

§ Truth table for active-high input S-R flip-flop:
§ Timing diagram:

An Active LOW SR Flip-flop
• Logic symbol:
S
R
Q
Q'
• Logic circuit:

§ Truth table for active-low input S'-R' flip-flop:
S' R' Q Q' Condition
0 0 1 1 Invalid condition.
0 1 1 0 SET
1 0 0 1 RESET
1 1
Q Q' Hold
§ Timing diagram:

Clocked SR Flip-flop

Logic circuit for Clocked SR Flip-flop

Timing diagram for positive edge
triggered

Example of waveform positive
edge triggered

Example of waveform negative
edge triggered

Timing diagram for negative edge
triggered

JK Flip-flop
•
The sequential operation of JK flip-flop is
exactly same to the SR flip-flop.
•
The difference is JK flip-flop has no INVALID
input state but using a TOGGLE operation.
Figure: Logic circuit of JK Flipflop

JK Flip-flop
• Logic symbol:
•
Truth table:
Change to

Figure: Timing Diagram for JK FF
using Positive edge triggered with
Q initial is 1
JK Flip-flop
•
Timing diagram/waveform (example):

JK Flip-flop
(with Synchronous and Asynchronous Input)
•
JK FF have 2 outputs and 5 inputs
•
Synchronous input : J, K and CLK
• Asynchronous Logic input : Preset (PRE) and Clear
(CLR) symbol:
•
Output : Q and Q’.

JK Flip-flop
(with Synchronous and Asynchronous Input)
•
Asynchronous inputs on a flip-flop have
control over the outputs (Q and not-Q)
regardless of clock input status.
•
The preset (PRE) input drives the flip-flop to a
set state while the clear (CLR) input drives it to
a reset state.
•
It is possible to drive the outputs of a J-K flipflop
to an invalid condition using the
asynchronous inputs, because all feedback
within the multivibrator circuit is overridden.

JK Flip-flop
(with Synchronous and Asynchronous Input)
Figure: JK Flip-flop with PRE and
CLR truth table

Timing Diagram For JK Flip-flop
(with Synchronous and Asynchronous Input)

Timing Diagram For JK Flip-flop
(with Synchronous and Asynchronous Input)

T Flip-flop
•
This flip-flop toggles (Q changes state)
on the negative going edge of the
clock pulse.
•
Q will only toggle on the negative edge
of the clock pulse, when T is high.
Logic symbol
(Positive edge
triggered)
Logic symbol
(Negative edge
triggered)

•
Logic circuit:
T Flip-flop

T Flip-flop
•
Truth table :
• Timing
diagram :
Assume that Q0 =
1

Truth
table
D Flip-flop
•
The D stands for "data".
•
The D type flip-flop has only one input (D
apart from the clock)
Logic symbol
(Positive edge
triggered)
Logic symbol
(Negative edge
triggered)

•
Logic diagram
D Flip-flop

D Flip-flop
•
When the clock goes high, D (a 0 or a 1) is
transferred to Q.
• When Timing the clock goes low, Q remains
unchanged. diagram :
At A, clock and data are high.
Q goes high and stays high until
•
Q stores the data until the clock B. goes high
again, when new data may be low. available.
At B, clock is high and data is
Q goes low and stays low until
C.

Construct a D Flip-Flop Using JK Flip-Flop
•
D flip-flop can be constructed using JK flip-flop
If the input of J and K are connected to
the inverter.

Construct a T Flip-Flop Using JK Flip-Flop
• T flip-flop can be constructed using JK flipflops
by connecting both inputs J and K
together.
CLK
T
J
clk
K
Q
Q'