Topic 5

5.0:COUNTER
Created by:
Noorziza Binti Abdul Aziz
Electrical Engineering Department
Politeknik Ibrahim Sultan

Introduction of counter
• Counters can be built when the flip-flops
are connected together.
• Flip-flops are used in the counter circuit can be built using
a JK flip-flop, and T.
• The number of flip-flops and how the flip-flops
are connected can determine the number of conditions
(modulo /mod) and the sequence numbers for
every triggering clock given to the counter.
• counters can be categorized into two types according
to how the triggered input clock :
asynchronous and synchronous counter.

Introduction of counter (cont…)
• asynchronous counter is where the first flipflop
receive the clock triggered from external clock and
the subsequent flip-flop will receive the clock triggered by the
Q output from previous flip-flop. This counter is also known as
ripple counter.
• synchronous counter is where the each flipflop
receives clock pulses simultaneously.
• One flip-flop can generate counting of either 0 or 1.
• Two flip-flops can generate counting of 4 states counter (00,
01, 10, 11).
• 3 flip-flops can generate counting of 8 states counter
(000,001,010,011,100,101,110,111) and others.

Example:
• This circuit can only count for two conditions either 0 or 1.
• Assume that the initial stage for flip-flop is RESET (Q = 0).
• Then the J and K inputs are shorted to logic 1 (J = 1, K = 1).
The flip-flop will be TOGGLED.
• In the first positive edge clock triggered, flip-flop will toggled
where Q change to 1. That’s mean the counter was count in 1
clock pulse.
• This stage will repeated to next clock pulse given.

Asynchronous counter
(i)
(ii)
(iii)
(iv)
(v)
(vi)
Asynchronous Up Counter
Asynchronous Counter as frequency dividers
Asynchronous Down Counters
Asynchronous Up/Down Counters
Asynchronous Counter mode number less then 2 n
Decade (mode 10)counters

(i)
Asynchronous Up Counters
• Up counter will count in order from the smallest/minimum
number to the greatest number (ex: 0,1,2,3,4,5,6,7,0,1,…)
• For the positive edge triggered flip-flop, output will connect to
the next clock flip-flop.
• For the negative edge triggered flip-flop, output Q will connect
to the next clock flip-flop.
• Mode is a condition of counters (ex: mode 6 will count
0,1,2,3,4,5,0,1,2,…).
• In the asynchronous counter, the previous output flip-flop will
trigger the next flip-flop.

The steps to built asynchronous
counter is:
1. Define the number of flip-flop.
The expression of mode, m is:
m=2 n , n = flip-flop numbers n = log m /
log 2
Example: mod 16 n = log 16 / log 2 = 4.
2. The maximum number of decimal places:
If mode m=2 n , the maximum number is m -1.
Example: mode 16 have a maximum number
is 15 and will repeated.
3. Built a transition/sequence diagram that shown the sequence
number
(example: 0 1 2 … (m-1).
4. Connect the external clock to the first flip-flop. Then, the output Q in
each flip-flop will be connected to the clock input for the next flip-flop.
5. Make sure that J and K for each flip-flop will be connected to the
logic 1.

Example :
Built a circuit for mod 4 asynchronous up
counters by using a J-K flip-flop.
Solution:
1. Number of FF
n = log 4/log 2
= 2 FFs
2. Transition/ sequence
diagram
repeat
11
00
01
10

3. Draw the counter circuit
using positive edge clock
triggered
JA
clk
QA
JB
clk
QB
KA
QA
KB
QB
4. Timing diagram (using positive edge clock triggered)
**Assume that the initial stage for counter is RESET
(Q=0).
clk
1
QA
0 1 0
1
0
1
LSB
QA
QB
0
0
1
1
0
0 MSB
Binary
Output
00 01 10 11 00 01

Solution (cont…)
3.Draw the counter circuit if using
the negative edge clock
triggered
JA
KA
clk
QA
QA
JB
KB
clk
QB
QB
1
4. Timing diagram (using negative edge clock triggered)
clk
QA
LSB
QB
Binary
Output
00 01 10 11 00 01
MSB

Exercise:
Build a circuit for mode 8 asynchronous counters by using a J-K flipflop.
Answer:
1. m = 2n 8 = 2n n= log8 / log 2 3
2. Maximum decimal places m-1 7
3. Transition diagram:

(iv)
Counter circuit:
1
JA
QA
JB
QB
JC
QC
clk
clk
clk
KA
QA
KB
QB
KC
QC
(v)
Timing diagram:

(ii) Asynchronous counter as a
frequency dividers
• Each flip-flop will have an output frequency of half(½) from the
input.
• if several flip-flops are connected, there will divide the clock
frequency into two and this occur at each flip-flop output.
• The expression of output frequency is f ou t = f in /2 n , where n is
the numbers of flip-flop.
• The expression of distribution factors, Distribution Factor = 2 n ;
n is flip-flop numbers.

Example:
2-bit asynchronous counter as a frequency division.
Timing diagram shown the frequency division.

• The output frequency for the last flip-flop of any
counter will be the clock frequency divided by the
MOD of the counter.
• Ex: MOD-16 counter, last FF will have a freq =1/16
of the input clock, also called a divide by 16
counter

Example:
• Calculate the maximum number, mode and distributions
factors for the 5-bit asynchronous counter.
Answer:
• Maximum number:
5 bits counter must have 5 flip-flop
N = 2 n -1 31 ( 11111 2 )
• Mod = 2n 2 5 32
• Distributions factor
2 n 2 5 = 32

(iii)Asynchronous Down Counters
•This counter will count from
the maximum number to minimum numbers
•For the positive edge triggered flip-flop,
output Q will connect to the next clock flipflop.
•For the negative edge triggered flip-flop, Q’
output will connect to the next clock flipflop

Example figure: Down Counters (Positive edge flip-flop)
1
JA
QA
JB
QB
JC
QC
clk
clk
clk
KA
QA
KB
QB
KC
QC
• flip-flop A will toggle when received at the positive edge.
• flip-flop B will only toggles when it gets a positive edge QA.
• flip-flop C will only toggles when it gets a positive edge QB.
clk
QA
QB
QC
111 110 101 100 011 010 001 000

Table for sequence state:
Positive Edge Triggered QC QB QA
0 0 0 0
1 1 1 1
2 1 1 0
3 1 0 1
4 1 0 0
5 0 1 1
6 0 1 0
7 0 0 1

Example figure: Down Counters (Negative edge flip-flop)
1
JA
QA
JB
QB
JC
QC
clk
clk
clk
KA
QA
KB
QB
KC
QC
QA
QA
QB
QC
111 110 101 100 011 010 001 000

Synchronous UP/DOWN counters
• This circuit uses AND-OR gate network and controlled by the control input
UP/DOWN.
• When the control input UP/DOWN are HIGH, so that all the shaded AND
gate will be active and will connect the Q output to the input CLK, the
counters will count up.
• Conversely, if control UP/ DOWN is LOW, all the shaded AND gate is
disabled and all that is not shaded AND gate will
be active and will connect the output to the input CLK, the counter will
count down.
• Actually,asynchronous UP/DOWN is slower than asynchronous Up
Counters or Down Counters. This is caused by a
delay (propagation delay) is increased from AND-OR gate network.

Mode 8 Asynchronous Up/Down Counters (Q 0 , Q 1 and Q 2 as an output)
K
K
K
QA will follow the
negative edge clock
triggered. While QB
and QC will follow the
UP/DOWN controller
(rising clock down
counter, Falling clock
UP counter)

(v) Asynchronous counter mode
number less than 2n (m

Mode 6 Asynchronous Counter Circuit
• Flip-flop B and C connected to the input of a NAND
gate.
• Output of NAND gate connected to the CLEAR input
each flip-flops.
• This counter will RESET to 000 at 6 th clock pulse while
the counter archive 110.

• Example 1:
• Design an asynchronous counter with mod 12 by using JK flip-flop
and define the frequency output if the given frequency input is 30KHz
•
• Answer:
• This counter can only count from 012 (that’s mean from 0000 to
1011) and this counter will return to 0 (0000).
• In the previous lesson, if we use 4 flip-flops, it should be count from
0000 to 1111.
• By RESET the NAND gate, this counter will reset the state of 1100 to
be 0000.
• The output of flip-flop 3 and 4 will ‘HIGH’ (logic 1) and connected to
the input of NAND gate.
• When the output from NAND gate is ‘LOW’, the output for flip-flops 3
and 4 will be ‘CLEAR’ to 0000.

1
JA QA
clk
KA QA
clr
JB QB
clk
KB QB
clr
JC
clk
KC
clr
QC
QC
JD QD
clk
KD QD
clr
• Asynchronous counter in mode 12
**Frequency:
The sequence output is 1100 2 = 12 10 .
That’s mean this counter is in mode
12.
f out = f in /m 30KHz/12 2.5KHz.
Output for flip-flop 3
and 4 will HIGH and
connect to the input of
NAND gate.
[F4F3F2F1= 1100]

(v)
Decade (mode 10) counters
•mode 10 counter have 10 different output
and can count from 0 (0000) to 9 (1001).
•Mode 10 counter can use in many
applications such as digital clock, digital
voltmeter, and frequency counter.
•Mode 10 counter are useful as an interface
between the binary input to decimal display.

1
J
QA
J
QB
J
QC
J
QD
clk
clk
clk
K
clr
QA
K
QB
clr
K
clr
QC
K
QD
clr
• This circuit will RESET after tenth clock pulse.
• After the end of tenth clock pulse, QD and QB is high (logic 1)
, therefore the output of NAND gate is 0. This will RESET the
counter (0000).

• The sequence table for the Decade counter is:

• A timing diagram for mod 12 up/down counter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
UP/DOWN
QA
QB
QC
QD
0 1 2 3 4 5 6 7 8 9 10 11 10 9 8 7

Synchronous Counter
• In a synchronous counter, the input pulses
are applied to all clock pulse inputs of all flip
flops simultaneously (directly). Synchronous
counter is also known as parallel sequential
circuit.
• Synchronous counter can count sequentially
or randomly.
• Examples of Synchronous Counters are as
1. Synchronous up counter
2. Synchronous down counter
3. Synchronous up/down counter
4. Random counter

Step to built a synchronous counter circuits:
1. Define the flip-flop number
2. Construct the state table with present state and
next state.
3. Construct the excitation table with referring to the
truth table of JK Flip-flop or T flip-flop.
4. Built a K-map for each flip-flop input.
5. Draw the complete circuit from the simplified K-map
input.

Question 1 :
Design a 3 bit synchronous up counter using JK flip-flops with
negative edge clock triggered.
Answer:
Step 1: define the number of flip-flop:
M=2 n n = log M/log 2 3 flip-flops
Step 2: table state
Present
state
Next state
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000

• Step 3: excitation table (refer to JK flip-flop truth table)
Truth table of JK flip-flop
J K Qn Qn+1
0 0 0 0
1 1
0 1 0 0
1 0
1 0 0 1
1 1
1 1 0 1
1 0
Excitation table:
Present
state
Next
state
INPUT
JC KC JB KB JA KA
000 001 0 X 0 X 1 X
001 010 0 X 1 X X 1
010 011 0 X X 0 1 X
011 100 1 X X 1 X 1
100 101 X 0 0 X 1 X
101 110 X 0 1 X X 1
110 111 X 0 X 0 1 X
111 000 X 1 X 1 X 1
JK flip-flop truth
table can be
simplified as
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Step 4: Built a K-map.
OUTPUT
Present
state
Next
state
INPUT
JC KC JB KB JA KA
000 001 0 X 0 X 1 X
001 010 0 X 1 X X 1
010 011 0 X X 0 1 X
011 100 1 X X 1 X 1
100 101 X 0 0 X 1 X
101 110 X 0 1 X X 1
110 111 X 0 X 0 1 X
111 000 X 1 X 1 X 1
Qc\ Qb Qa
00 01 11 10
0
1
0 0 1 0
x x x x
Qc\ Qb Qa
0
1
00 01 11 10
x x x x
0 0 1 0
Qc\ Qb Qa
0
1
Qc\ Qb Qa
00 01 11 10
0
1
00 01 11 10
0 1 X X
0 1 X X
X 1 1 X
X 1 1 X
Qc\ Qb Qa
0
1
Qc\ Qb Qa
0
1
KA = 1
00 01 11 10
1 X X 1
1 X X 1
JA = 1
00 01 11 10
X X 1 0
X X 1 0
KB = Qa
JC = Qb Qa
KC = Qb Qa
JB = Qa

Step 5: counter logic circuit
KA = 1 JA = 1
KB = Qa
JB = Qa
KC = Qb Qa
JC = Qb Qa
1
JA QA
clk
KA QA
JB QB
clk
KB QB
JC QC
clk
KC QC
clk

Question 2 :
Design a 3 bit synchronous up counter using T flip-flops with
negative edge clock triggered
Answer:
Step 1: define the number of flip-flop:
M=2 n n = log M/log 2 3 flip-flops
Step 2: table state
Present
state
Next state
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000

Step 3: excitation table (refer to T flip-flop truth table)
Step 4:
K-Map
OUTPUT
Present
state
Next
state
INPUT
TC TB TA
000 001 0 0 1
001 010 0 1 1
010 011 0 0 1
011 100 1 1 1
100 101 0 0 1
101 110 0 1 1
110 111 0 0 1
111 000 1 1 1
Qc\ Qb Qa
00 01 11 10
0
1
0 0 1 0
0 0 1 0
Qc\ Qb Qa
00 01 11 10
0
1
0 1 1 0
0 1 1 0
INPUT Qn Qn+1
0
1
0 0
1 1
0 1
1 0
Qc\ Qb Qa
00 01 11 10
0
1
1 1 1 1
1 1 1 1
TA = 1
TC = Qb Qa
TB = Qa

Step 5: counter logic circuit
TC = Qb Qa
TB = Qa
TA = 1
1
TA QA
clk
QA
TB QB
clk
QB
TC QC
clk
QC
clk

Question 2 :
Design a synchronous counter using JK flip-flops with negative edge clock
triggered that can count a random number 0,3,5,1,4,6 and repeated.
Answer:
Step 1: Define the number of flip-flop (use the highest number counting
sequences. In this example, the highest number is 6)
Mod, M = 6 + 1 [6 is the highest number in counter]
M=2 n n = log 7/log 2 2.81 ~ 3 flip-flops
Step 2: table state
Present
state
Next
state
000 011
011 101
101 001
001 100
100 110
110 000

Step 3: excitation table (refer to JK flip-flop truth table)
OUTPUT
INPUT
Qn Qn+1 J K
Present
state
Next
state
JC KC JB KB JA KA
000 011 0 X 1 X 1 X
011 101 1 X X 1 X 0
101 001 X 1 0 X X 0
001 100 1 X 0 X X 1
100 110 X 0 1 X 0 X
110 000 X 1 X 1 0 X
QbQa
00 01 11 10
Qc
0
1
0 1 1 X
X X X X
QbQa
00 01 11 10
Qc
0
1
1 0 X X
1 0 X X
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
QbQa
00 01 11 10
Qc
0
1
Step 4: K-Map
1 X X X
0 X X 0
JC = Qa
QbQa
00 01 11 10
Qc
0
1
X X X X
0 1 X 1
KC = Qa + QB
JB = Qa
QbQa
00 01 11 10
Qc
0
1
X X 1 X
X X X 1
KB = 1
JA = Qc
QbQa
00 01 11 10
Qc
0
1
X 1 0 X
X 0 X X
KA = Qc . Qb

Jc = Qa
Kc = Qa + Qb
Jb= Qa
Kb = 1
Ja= Qc
Ka= Qc . Qb

Synchronous Counter Versus Asynchronous Counter
Asynchronous Counter
Only the first flip-flop driven by
external clock while the others flipflops
are driven by previous flipflop.
Cannot design random counters
Propagation delay is severe for
larger MOD of counters, especially
at the MSB.
Circuit design is very simple
Synchronous Counter
Synchronous counters are driven
by same clock (simultaneously)
Can design for sequence or
random number
No problem in propagation delay
because all flip-flops is triggered
simultaneously.
Design involve complex logic
circuit

Disadvantages of Asynchronous Counter
compare to Synchronous Counter
i. Has a propagation delay. The more number
of flip-flops in an asynchronous counter, the
slower it will be.
ii.
To count a truncated not equal to 2n, extra
feedback logic is required.
iii. Counting errors occur at high clocking
frequency.

Cascade connection
• The counter can be connected to get the
higher mode counter.
• The cascade connection constructed by
connecting the output of the last flip-flop into
the first flip-flop input of the next counter

• Asynchronous counter

• Synchronous counter
In the synchronous counter, there have addition
input as ‘count enable (CE)’ and ‘terminal count
(TC)’ in the output to avoid propagation delay.
The function of CE is to enable the counting
process and TC is to moves counter to the
next when the counter reaches the maximum
number or to produce a high output when the
process said to produce the maximum number.

Counters in Digital Clocks

5.0 COUNTER
5.1 DEFINITION:
A counter is a digital sequential logic device that will go
through a certain predefined states (for example counting
up or down) based on the application of the input pulses.
They are utilized in almost all computers and digital
electronics systems. There are two main types of counters:
Asynchronous and Synchronous counters.
5.1 Function of Counter
Timing
Sequencing
Counting
5.2 The Difference Between Asynchronous And Synchronous Counter
Asynchronous Counter
The circuit diagram for this counter is
simple to design.
Only the first flip-flop driven by
external clock while the others flipflops
are driven by previous flip-flop.
Propagation delay is severe for larger
MOD of counters, especially at the
MSB.
Frequency operating is low.
Cannot design random counters
Synchronous Counter
The circuit diagram for this counter
becomes difficult as number of states
increase in the counter.
The clock is driven by same clock
(simultaneously)
No problem in propagation delay
because all flip-flops is triggered
simultaneously.
Frequency operating is higher.
Can design for sequence or random
number
5.3 Mod of Counter
The mod number is always equal to the number of states which the counter goes through in each
complete cycle before it recycles back to its starting state.
An n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2 n .
5.3.1 Examples Type of Modulus
2 bit (MOD-4)
3 bits (MOD-8)
4 bits (MOD-16)
5.3.2 Maximum number of Counter
The largest number that counter will counting.
Maximum number = M -1 ; M is modulus
5.4 Number of Flip-flop
Number of flip-flop, n = log M/log 2;
M = modulus
5.5 State Diagram
State diagram shows the sequence of states through which the counter advances when it is clocked.
Examples of state diagram:

Figure 5.1 State diagram of the MOD 8 UP Counter
5.2 Asynchronous Counter
5.2.1 Asynchronous Up Counter
This counter will count in sequence from minimum usually startig at 0 to the
maximum number that depending on the Mod of the counter.
Example: counter in mod 8 will have a sequence number:
000 001 010 011 100 101 110 111
Figure 5.2 Asynchronous up counter circuit when using positive clock triggered
Figure 5.3 Asynchronous up counter circuit when using negative clock triggered

5.2.2 Asynchronous Counter as a frequency dividers
In the basic counter, each flip-flop provides an output waveform that is exactly half the
frequency of the waveform at its clock input.it can be illustrate as figure below:
Figure 5.4 Counter waveform showing frequency division by 2 for each flip-flop
In general, for any counter the output from the last flip-flop divides the input clock
frequency by the mod number of the counter. For example, a MOD-8 counter is also
called as divide-by-8 counter.
5.2.3 Asynchronous Down Counters
Figure 5.5
Asynchronous down counter circuit when using positive clock triggered
Figure 5.6
Asynchronous down counter circuit when using negative clock triggered

5.2.4 Asynchronous Up/Down Counters
Figure 5.7 Asynchronous up/down counter circuit (Mod 8)
Figure 5.8 Timing diagram Asynchronous up/down counter (Mod 8)
5.2.5 Glitch in Asynchronous Counter
Glitch is an undesired transition that occurs before the signal settles to its intended value. In other
words, glitch is an electrical pulse of short duration that is usually the result of a fault or design
error, particularly in a digital circuit.
For example in a digital electronics, flip-flops are triggered by a pulse that must not be shorter
than a specified minimum duration; otherwise, the component may malfunction. A pulse shorter
than the specified minimum is called a glitch. A related concept is the runt pulse, a pulse whose
amplitude is smaller than the minimum level specified for correct operation, and a spike, a short
pulse similar to a glitch but often caused by ringing or crosstalk. A glitch can occur in the presence
of race condition in a poorly designed digital logic circuit.
5.2.6 Asynchronous Counter mode number less then 2 n
Counter in this type are modified from basic counter in mod 2 n which allowing the counter
to skip states that are normally part of the counting sequence. To illustrate for this counter,
take an examples of 3 bit counter. Normally this counter will count from 000 to 111 but we
can design to build a mod 5 counter which only count 000 to 100.

Figure 5.9 Mod 5 asynchronous up counter
(i) The NAND output is connected to the asynchronous CLR (clear) inputs of each flip-flop.
As long as the NAND output is HIGH, it will have no effect on the counter. When it goes
LOW, it will clear all the flip-flop. So that, the counter immediately goes to the 000
state.
(ii) The input of the NAND gate are the outputs of Qc and Qb. So the NAND output will go
LOW whenever Qa = Qc = 1. This condition will occur when the counter goes from 100
to the 101 state. The LOW at the NAND output will immediately (nanosecond) clear the
counter to 000 state
5.2.7 Asynchronous Decade (Mod 10) Counter
Figure 5.10 Decade Counter circuit

5.3 Synchronous Counter
5.3.1 Synchronous Up Counter
Figure 5.11 Mod-16 Synchronous Up Counter
5.3.2 Synchronous Down Counter
Figure 5.12 Mod-16 Synchronous Down Counter
5.3.4 Synchronous Up/Down Counter

Figure 5.13 Mod-16 Synchronous Up/Down Counter
5.3.5 Synchronous Decade Counter
Figure 5.14 : Synchronous Decade Counter
5.3.6 Synchronous counter in random number
Example 1: Design a synchronous counter using JK flip-flops with positive edge clock triggered that can
count a random number 0, 3, 5, 1, 4, 6 and repeated.
Solution:
Step 1: Define the number of flip-flop (use the highest number counting sequences. In this example, the
highest number is 6)
Mod, M = 6 + 1 [6 is the highest number in counter]
M=2 n n = log 7/log 2 2.81 ~ 3 flip-flops
Step 2: Table state
Present state
Next state
000 011
011 101
101 001
001 100
100 110
110 000

Step 3: Excitation table (refer to JK flip-flop truth table)
JK Flip-flop Truth table
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
Excitation table
1 1 X 0
Step 4: Built the K-Map

Step 5: Draw a logic circuit
Example 2: Design a synchronous counter using T flip-flops with negative edge clock triggered that can count a
random number 0, 1, 4, 7, 5, 2 and repeated.
Solution:
Step 1: Number of flip-flop
Maximum number = 7
Mod = Maximum number + 1
= 8
n = log 8/log 2
= 3 flip-flops
Step 3: Table state
Present state Next State
000 001
001 100
100 111
111 101
101 010
010 000

Step 4 : Excitation table
T Q n Q n+1
0 0
0
1 1
0 1
1
1 0
T flip-flop truth table
Output
Input
Present state Next state Tc Tb Ta
000 001 0 0 1
001 100 1 0 1
100 111 0 1 1
111 101 0 1 0
101 010 1 1 1
010 000 0 1 0
Step 5 : K-map
Step 6: Circuit diagram
L2
L3
L4
5V
+V
CLK
CP1
CP2 Q1
Q2
FFA
S
J Q
CP _
K Q
R
FFB
S
J Q
CP _
K Q
R
FFC
S
J Q
CP _
K Q
R
Figure 5.15 Synchronous counter with counting of 0, 1, 4, 7, 5, 2 and repeated

5.3 Disadvantages of asynchronous counter compare to synchronous counter
a) Has a propagation delay. The more number of flip-flops in an asynchronous counter, the slower it will
be.
b) To count a truncated not equal to 2n, extra feedback logic is required.
c) Counting errors occur at high clocking frequency.
5.4 Different between Asynchronous Counter and Synchronous Counter
Asynchronous Counter
Only the first flip-flop driven by external clock
while the others flip-flops are driven by
previous flip-flop.
Cannot design random counters
Propagation delay is severe for larger MOD of
counters, especially at the MSB.
Circuit design is very simple
Synchronous Counter
Synchronous counters are driven by same
clock (simultaneously)
Can design for sequence or
random number
No problem in propagation delay because
all flip-flops is triggered simultaneously.
Design involve complex logic circuit
5.5 Cascade connection in counter
The counter can be connected to get the higher mode counter.
The cascade connection constructed by connecting the output of the last flip-flop into the first flip-flop
input of the next counter
Figure 5.16 Mod 32 asynchronous counter using cascade connection
I the syhroous outer, there have additio iput as out eale CE ad terial out TC
in the output to avoid propagation delay.
The function of CE is to enable the counting process and TC is to moves counter to the next when the
counter reaches the maximum number or to produce a high output when the process said to
produce the maximum number.

Figure 5.17 Mod 100 synchronous counter in cascade connection