A Technical History of Apple's Operating Systems - Mac OS X Internals

Mac OS X Internals (www.osxbook.com) 71
particularly as focus of microprocessor companies has shifted to micro-
architecture. It is common to see companies attempting to optimize su-
perscalar, out-of-order execution. For example, Intel’s Pentium Pro (1995)
translated complex x86 instructions into RISC-like micro-operations during
instruction decoding. A superscalar engine executed these micro-operations
in a speculative, out-of-order fashion, with register renaming. Intel’s P6 ar-
chitecture had various other RISC-like features.
The 801 Minicomputer Project, so called after the name of the building it was
housed in, started at IBM in 1975. John Cocke, who is regarded as the “father of
RISC architecture,” and others explored a simplified instruction set along with
compiler code-generation strategies for improving performance and reducing cost.
An early RISC tenet was an instruction-processing rate of 1 per clock-cycle. The
801 was able to achieve a clock-cycles-per-instruction (CPI) ratio of 1 for contrived
code, but not for general-purpose code. It had 120 instructions. As instruction pipe-
lining and cache memories evolved and improved, it became increasingly possible
to meet the goal of having a CPI of 1.
IBM’s first RISC-based product was the IBM Personal Computer RT (RISC
Technology), which was announced in January 1986. It ran an operating system
called the Advanced Interactive Executive (AIX). Further work led to a new design
called “AMERICA,” which led to “RIOS,” and eventually the “POWER” architec-
ture. POWER is a contraction for “Performance Optimized With Enhanced RISC.”
It combined the original RISC concepts with some traditional (CISC) concepts re-
sulting in a more balanced architecture, representing the second generation of
IBM’s RISC technology. The associated product family included the RISC System/
6000 (RS/6000), along with the AIX 3 operating system. The first RS/6000 systems
were announced on February 15, 1990.
The POWER architecture defined 184 instructions, which, although a few too
many from a RISC purist’s perspective, performed well with the independent execu-
tion units available in the RS/6000, as multiple instructions could be executed in a