A Technical History of Apple's Operating Systems - Mac OS X Internals

72 Chapter 1 A Technical History of Apple’s Operating Systems
single cycle. As the POWER architecture evolved, the earliest version of the archi-
tecture came to be known as POWER1. Even in the POWER1 era, there were mul-
tiple implementations of POWER, such as the low-end RISC Single Chip (RSC),
the mid-end RS .9, and the high-end RS 1.0. The RSC had a shared data and in-
struction cache. It was a low-cost shrinkage of POWER onto a single chip, whereas
the others were multiple-chip. The lowest-end RS/6000 model—the 33 MHz Model
220—was released in January 1992.
In the early 1980s, Berkeley and Stanford Universities were working on the
RISC and MIPS projects, respectively. By 1990, there were several competing
RISC architectures in the market: MIPS, HP Precision Architecture (PA-RISC),
SPARC V8, Motorola 88K, and IBM RS/6000. The Intel i860 was introduced in
1989 as a general-purpose, 64-bit RISC processor with 3D graphics capabilities.
The Alpha AXP from Digital Equipment Corporation joined the RISC crowd in
1992 as another 64-bit RISC processor.
1.5.2.2. Apple Wants RISC
As part of a project code-named Jaguar, Apple had briefly considered using a Mo-
torola 88K variant as their future RISC-based hardware platform. They turned to the
POWER architecture next.
In 1991 Apple, IBM, and Motorola joined forces to form the “AIM” Alliance
with the goal of creating a Common Hardware Reference Platform (CHRP). The
collaboration resulted in the PowerPC Architecture—a derivative of POWER. Pow-
erPC included most of the POWER instructions, while adding some new ones and
excluding some rarely used instructions. Important PowerPC improvements in-
cluded the following.
• It supported both 32-bit and 64-bit computing, with an implementation
being free to only implement the 32-bit subset. An implementation supporting
both would be able to dynamically switch between them.