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Finisar<br />
XFP<br />
The <strong>Ultimate</strong> <strong>10</strong><strong>Gb</strong>/s <strong>Solution</strong><br />
Lew Aronson<br />
October 17, 2002
Outline<br />
■ Background on Fiberoptic Transceivers and XFP<br />
■ XFP Multisource Agreement (MSA)<br />
�� Membership, Goals, Status<br />
�� Concept Model<br />
�� Mechanical/Thermal Design<br />
�� Signal Integrity, SONET Jitter Issues<br />
�� EMI Issues<br />
■ Finisar Results<br />
■ Critical Modeling Issues for XFP<br />
■ Summary<br />
Finisar<br />
Lew Aronson October 17, 2002
Fiberoptic Transceivers and Transponders<br />
Transceiver<br />
Serial<br />
Electrical<br />
Transponder<br />
Parallel<br />
Electrical<br />
RX -<br />
RX +<br />
I2C<br />
RX 0<br />
RX n<br />
TX +<br />
TX -<br />
Management<br />
TX 0<br />
TX n<br />
.<br />
.<br />
Serial ID<br />
and<br />
Diagnostics<br />
Demux<br />
Serial ID/<br />
Diagnostics<br />
Mux<br />
Postamp<br />
Laser Driver<br />
Postamp<br />
Laser Driver<br />
ROSA<br />
PIN/TIA<br />
TOSA<br />
Laser<br />
ROSA<br />
PIN/TIA<br />
TOSA<br />
Laser<br />
Finisar<br />
Opt In<br />
Opt Out<br />
Opt In<br />
Opt Out<br />
Lew Aronson October 17, 2002
What do Datacom Customers Want?<br />
■ Transceivers in Industry Standard Form-Factors<br />
�� Generally developed as Multisource Agreements, Multiple Vendors<br />
�� Mechanically and Electrically Interoperable<br />
■ Receptacle based Ra<strong>the</strong>r than Pigtailed<br />
■ Low Cost – Obtained through VERY high volume<br />
■ Small Footprint – Maximize Transceivers on Card Edge<br />
Finisar<br />
■ Low Power – Typ. < 1W per port for 1 – 2G Enables High Port Density<br />
■ Hot Pluggable Through Panel<br />
�� Allows Systems to be Configured to Customer Needs just before Shipping.<br />
�� Mix and Match Link Lengths<br />
�� Allows Easy Field Upgrades<br />
■ Most Customers Have Very Strict Reliability Requirements<br />
�� Integrated Monitoring Becoming Popular<br />
Lew Aronson October 17, 2002
Fiber Optic Link Standards<br />
■ E<strong>the</strong>rnet for Local Area Networks (LANs)<br />
�� <strong>10</strong>, <strong>10</strong>0 Mb/s – Not in Finisar Product Family<br />
�� Gigabit E<strong>the</strong>rnet – 1.25 <strong>Gb</strong>/s<br />
�� <strong>10</strong>G E<strong>the</strong>rnet – <strong>10</strong>.3 <strong>Gb</strong>/s – In initial deployment<br />
■ Fibre Channel for Storage Area Networks (SANs)<br />
�� FC1x–1.06<strong>Gb</strong>/s<br />
�� FC 2x – 2.125 <strong>Gb</strong>/s<br />
�� <strong>10</strong>GFC – <strong>10</strong>.5 <strong>Gb</strong>/s – In development<br />
Finisar<br />
■ Multimode and Singlemode Fiber and Copper, Many Reaches<br />
■ SONET<br />
�� OC-3,12,48,192 (155Mb/s, 622Mb/s, 2.5<strong>Gb</strong>/s, <strong>10</strong><strong>Gb</strong>/s)<br />
�� Reaches from 600m – 80 km<br />
Lew Aronson October 17, 2002
Standard Form-Factors for 1 – 2.5 <strong>Gb</strong>/s<br />
■ 1x9<br />
■ GBIC<br />
� Soldered, ~1” Pitch, SC Connectors<br />
� Popular for Multimode <strong>Gb</strong>E, In Decline<br />
Finisar<br />
� Hot Pluggable, ~1.5” Pitch, SC Connectors<br />
� Available for Many Link Standards<br />
� Single 5V Supply. 1.5W max<br />
■ Small Form Factor (SFF) – 3.3V Supply<br />
� Soldered, ~0.55” Pitch, LC Connectors<br />
� Available in 2x5 and 2x<strong>10</strong> (Analog Monitoring)<br />
■ Small Form Factor Pluggable (SFP) – 3.3V Supply<br />
� Hot Pluggable, ~0.65” Pitch, LC Connectors<br />
� Most Popular in New Designs<br />
�
Evolution of 1G Systems<br />
GLM <strong>Solution</strong><br />
GBIC <strong>Solution</strong><br />
SFP <strong>Solution</strong><br />
<strong>Ultimate</strong> SFP <strong>Solution</strong><br />
<strong>10</strong><br />
8<br />
1G<br />
Optics<br />
SERDES <strong>10</strong> 8B/<strong>10</strong>B 8 ASIC<br />
1G<br />
Optics<br />
1G Optics<br />
.<br />
1G Optics<br />
8B/<strong>10</strong>B<br />
SERDES<br />
Quad<br />
SERDES<br />
1G Optics ASIC w/<br />
.<br />
1G Optics<br />
1G Serial<br />
Outputs<br />
8<br />
8<br />
32<br />
32<br />
ASIC<br />
ASIC<br />
Lowest Cost<br />
Least Power<br />
Finisar<br />
Minimum Board Space<br />
Lew Aronson October 17, 2002
Evolution of <strong>10</strong>G Systems<br />
SONET<br />
Transponder<br />
XENPAK<br />
Transponder<br />
Module<br />
(X2, XPAK?)<br />
XFP: <strong>Ultimate</strong><br />
Serial Interface<br />
<strong>Solution</strong><br />
<strong>10</strong>G<br />
Optics<br />
<strong>10</strong>G<br />
Optics<br />
<strong>10</strong>G Optics ASIC w/<br />
.<br />
<strong>10</strong>G Optics<br />
Mux<br />
DeMux<br />
Mux<br />
DeMux<br />
16<br />
16<br />
XBI<br />
622M<br />
XAUI to<br />
64/66<br />
Scrambler ASIC<br />
<strong>10</strong>G Serial<br />
Output(s)<br />
4<br />
4<br />
XAUI<br />
3.1G<br />
16<br />
16<br />
Lowest Cost<br />
Least Power<br />
Finisar<br />
ASIC<br />
w/ XAUI<br />
Interface<br />
Minimum Board<br />
Space<br />
Lew Aronson October 17, 2002
Motivation for <strong>10</strong>G Serial Interface<br />
Finisar<br />
■ Advantages of a Transceiver with a <strong>10</strong>G Serial Interface<br />
are Overwhelming<br />
�� Eliminates Large Amount of Circuitry<br />
• MUX and DeMUX on Transceiver<br />
XAUI Interface (both ends)<br />
�� 50% or More of <strong>the</strong> Power of Parallel Interface Transponders<br />
is Related to <strong>the</strong> Internal Parallel-Serial Conversion<br />
�� A Transceiver with a Serial Interface is MUCH Smaller;<br />
Approximately 25% <strong>the</strong> size of XENPAK<br />
Lew Aronson October 17, 2002
Customer Concerns with XFP<br />
■ Host PCB Concerns<br />
�� Need up to 8 – 12” on FR-4 Substrates with Buried Stripline<br />
�� Fears of Routing <strong>10</strong>G Traces.<br />
■ PCI Card Compliance (Limits Device Height)<br />
■ Difficulty of One Form Factor for All Reachs<br />
�� Up to 40km (datacom) or 80 km (telecom)<br />
■ Thermal <strong>Solution</strong> to Support Proposed High Density<br />
■ Difficulty of Suppressing Electromagnetic Emissions (EMI)<br />
■ Overall SONET Jitter Compliance for Telecom<br />
■ Availability of ICs with <strong>10</strong>G Serial Interface<br />
Finisar<br />
Lew Aronson October 17, 2002
XFP Multisource Agreement (MSA)<br />
Finisar<br />
■ XFP MSA Group Founded in Late 2001 to Define <strong>10</strong>G Serial Transceiver<br />
�� Founding Members: Broadcom, Brocade, Emulex, Finisar, ICS (Sumitomo),<br />
JDSU (form. IBM), Maxim, Ciena, Tyco Electronics, Velio<br />
�� Currently Over 60 Companies – Optics, IC and Host System Companies<br />
■ What Does a Transceiver MSA Do?<br />
�� Defines Specs to Ensure Mechanical, Thermal and Electrical Interoperability.<br />
■ Goals of <strong>the</strong> XFP MSA<br />
�� Support of <strong>10</strong>G E<strong>the</strong>rnet, <strong>10</strong>G Fiber Channel and SONET OC-192<br />
Ideally in a Common Device for Same Reach<br />
�� Support Reaches to 40 km (recently extended to 80 km)<br />
�� Allow High Port Density (up to 16 Ports on Typical 19” Line Card<br />
�� Should work on Host PCBs with 8 – 12” Traces on FR-4<br />
�� Support PCI Height Applications<br />
�� Provide Good EMI <strong>Solution</strong><br />
Lew Aronson October 17, 2002
XFP Dimensions<br />
78.0<br />
Finisar<br />
18.4<br />
Module pitch: 23.5 mm<br />
Allows 16 Ports in 15”<br />
8.5<br />
Lew Aronson October 17, 2002
XFP MSA – Present Mechanical Design<br />
PCI compliant Riding<br />
Heatsink Shown<br />
.570” pin height<br />
Bail Latch<br />
Module Shown<br />
in Cage Without<br />
Riding Heatsink<br />
Compliant Gasket Seals<br />
Cage Against Bezel<br />
Finisar<br />
Large heat sink<br />
contact area<br />
Flat cage top supports<br />
heat sink when<br />
module is not installed<br />
Lew Aronson October 17, 2002
XFP MSA – Present Mechanical Design<br />
■ Riding Heatsink Concept Solves Major Thermal Issues<br />
EMI Fingers<br />
Cage Without<br />
Riding Heatsink<br />
Cage with<br />
Riding Heatsink<br />
Finisar<br />
�� PCI Systems have Tight Height Requirements, But Low Total Thermal Load<br />
�� Switch Systems Have Large Thermal Load but More Vertical Space<br />
�� Heatsink is Part of Cage and Adaptable to Different Applications<br />
�� Tested for Thermal Conductivity with Multiple Insertions with Contamination<br />
EMI Gasket<br />
Lew Aronson October 17, 2002
Form Factor Comparison<br />
XENPAK<br />
XFP<br />
300-pin XBI<br />
Finisar<br />
Lew Aronson October 17, 2002
XFP MSA – Thermal Considerations<br />
■ MSA Defines 4 Power Classes<br />
�� 1.5W Max – Likely Future Technology for < <strong>10</strong> km Parts<br />
�� 2.5W Max – Likely Initial <strong>10</strong> km Parts<br />
Finisar<br />
�� 3.5 W Max and > 3.5W – Long Haul XFP with Cooled Optics and APD<br />
■ Thermal Modeling Studies<br />
�� Simulations indicate Acceptable Performance in Datacom Environment<br />
8 Ports of 2.5W with Careful but no Exotic Cooling<br />
16 Ports Possible at 1.5W or with Front to Back Airflow<br />
�� Telecom System Thermal Modeling in Progress<br />
Lew Aronson October 17, 2002
XFP Pinout<br />
■ Uses 30-pin Version of Present SFP Connector<br />
Finisar<br />
� � +3.3 and +5V and +1.8V Supply (optional –5V for Long Haul)<br />
� +3.3V I2 � +3.3V I C Communication<br />
2C Communication<br />
30<br />
Gnd<br />
Gnd<br />
1<br />
29<br />
TD+<br />
-5V<br />
2<br />
28<br />
TD-<br />
MOD_Desel<br />
3<br />
27<br />
Gnd<br />
INTERRUPT<br />
4<br />
26<br />
Gnd<br />
TX_DIS<br />
5<br />
25<br />
REFclk-<br />
+5V<br />
6<br />
24<br />
REFclk+<br />
Towards ASIC<br />
Gnd<br />
7<br />
23<br />
Gnd<br />
+3.3V<br />
8<br />
22<br />
+1.8V<br />
Towards Bezel<br />
+3.3V<br />
9<br />
21<br />
P_Down<br />
I2C - SCL<br />
<strong>10</strong><br />
20<br />
+1.8V<br />
I2C - SDA<br />
11<br />
19<br />
Gnd<br />
MOD_ABS<br />
12<br />
18<br />
RD+<br />
MOD_NR<br />
13<br />
17<br />
RD-<br />
RX_LOS<br />
14<br />
16<br />
Gnd<br />
Gnd<br />
15<br />
Pinout still subject to change<br />
Lew Aronson October 17, 2002
XFP MSA – Electrical Reference Model<br />
Finisar<br />
■ Previous Transceiver Designs Will Not Meet Optical Jitter Specs<br />
�� Host Board Jitter Contribution at <strong>10</strong> <strong>Gb</strong>/s is Too Large<br />
■ Design Assumes A Signal Conditions (CDR) in bothTX and RX Paths<br />
■ Goal is support of 8 – 12” on FR-4 host boards.<br />
Electrical<br />
Compliance<br />
Points<br />
Host<br />
ASIC<br />
D<br />
A<br />
Host Board<br />
<strong>10</strong> <strong>Gb</strong>“XFI”<br />
Interface<br />
8–12”FR-4<br />
C’<br />
B’<br />
C<br />
B<br />
30 pin TYCO SFP<br />
Style Connector<br />
RX<br />
CDR<br />
TX<br />
CDR<br />
XFP Module<br />
PA ROSA<br />
LDR<br />
TOSA<br />
Optical<br />
Interface<br />
Lew Aronson October 17, 2002
XFI Interconnect Signal Integrity<br />
■ Amplitude and Eye Masks Specified at All Interfaces<br />
�� Transmission Swings of 200 – 350 mV p-p Single Ended<br />
�� Min Receiver Sensitivity of 62.5 mV Single Ended<br />
�� Loss Budget Corresponds to Connector + 8-12” FR-4<br />
Finisar<br />
■ Eye Masks + Jitter Specs Define CDR and Host ASIC Requirements<br />
■ Return Loss Specs at All Compliance Points Limit Reflection Induced Jitter<br />
�� Generates Critical Design Issues at Host Board IC, Module I/O<br />
�� Assumes Limited Discontinuities Along Host Board<br />
Via Design for Transistion to Buried Stripline Becomes Critical<br />
Lew Aronson October 17, 2002
XFP MSA – SONET Jitter Issues<br />
Finisar<br />
■ Specifying Host and Module Properties to Meet SONET Jitter a Major Concern<br />
■ Largest Issue is Transmitter Jitter Generation:<br />
�� Main Approach: Host and Module Share Jitter Generation Requirements<br />
Host Meets Low Frequency Jitter Gen. Spec < 60 mUIp-p for 50 kHz – 4 MHz<br />
XFP Filters High Frequency Jitter, < 60 mUI Gen. from 50 kHz – 80 MHz<br />
Ability of Host to Meet Spec is Controversial<br />
�� Alternate Approach: Module May Use Clock Multipler Unit (CMU) on TX Path<br />
Replaces Host Jitter Gen. with Need for Tight Control of Clock Spectrum<br />
■ Jitter Peaking Probably not Hard to Meet But Hard to Measure.<br />
■ O<strong>the</strong>r Questions on Jitter Tolerance Complex When Divided between Host and Module<br />
Lew Aronson October 17, 2002
XFP MSA – EMI Considerations<br />
■ Minimizing EMI in Specifications<br />
�� XFI Swing is Relatively Small (350 mV S.E. Max)<br />
�� LimitsonRisetime(>24ps20–80%)<br />
�� Transmit Preemphasis Not Allowed by Eye Mask<br />
■ Cage Design<br />
Finisar<br />
�� Early Cage Design Simulations Showed Significant Leakage into Host Chassis<br />
�� New Design Proposed and Simulated Showed 20 – 30 dB Improvement<br />
■ Remaining Issues<br />
�� Determine EMI from Stripline on Host Board with Worst Case XFI Signals<br />
�� Industry Standards on Test Patterns and Associated Spectrum<br />
Lew Aronson October 17, 2002
Comparing EMI for Different Cage Designs<br />
Finisar<br />
Original Cage Design Improved Cage Design<br />
Leakage Areas Extra Contact<br />
Points<br />
Compliant Casket<br />
Flush to Board<br />
Compliant<br />
Gasket to<br />
Host Board<br />
Compliant Wiping<br />
Contact to Raised<br />
Skirt Edge (Not<br />
Shown)<br />
Lew Aronson October 17, 2002
EMI Simulation Measurement Points<br />
Finisar<br />
Lew Aronson October 17, 2002
Mean E Field (dB V/m)<br />
Results – Average Field Value vs Frequency<br />
(Average of All Points of Array in Each Case)<br />
140.00<br />
130.00<br />
120.00<br />
1<strong>10</strong>.00<br />
<strong>10</strong>0.00<br />
90.00<br />
80.00<br />
70.00<br />
60.00<br />
50.00<br />
Baseline Imp Cage Shield<br />
Finisar<br />
0.00 5.00 <strong>10</strong>.00 15.00 20.00 25.00 30.00 35.00 40.00<br />
Frequency (GHz)<br />
Assumed Source<br />
w/ Equal Power vs<br />
Frequency<br />
Lew Aronson October 17, 2002
Finisar Recent XFP Results<br />
Finisar<br />
Lew Aronson October 17, 2002
TX Optical Output Eye – <strong>10</strong><strong>Gb</strong>E<br />
Finisar<br />
Lew Aronson October 17, 2002
RX Electrical Output Eye from XFP<br />
Loopbacked output through 30pin conn., 2” FR4, SMA, and cables<br />
– Passes 50% mask margin<br />
Finisar<br />
Lew Aronson October 17, 2002
Interoperability Results<br />
Finisar<br />
■ XBI to Serial MUX/DEMUX Sets on 300 pin – Serial SMA Coupons Tested.<br />
�� Broadcom (BCM8120/8121)<br />
�� Infineon (FOA4<strong>10</strong>01B1 / FOA5<strong>10</strong>01B1)<br />
■ Connected to XFP Eval Board with SMF Fiber Loopback<br />
■ No Errors Detected in Ei<strong>the</strong>r Case for 5 min Run.<br />
Finisar “Lotus”<br />
300 Pin Tester<br />
300<br />
Pin<br />
Conn<br />
Demux<br />
Mux<br />
FTRX-1409<br />
XFP Eval Board<br />
<strong>10</strong> km<br />
SMF<br />
Lew Aronson October 17, 2002
First Generation Reference Board<br />
Finisar<br />
Dual XFP modules on FR-408 eval board, SMA on one module, SERDES on o<strong>the</strong>r<br />
8” trace version, 12 layers , 62 mil thickness<br />
Buried stripline on layer 9, ground plane on 8 and <strong>10</strong><br />
In Preliminary Testing<br />
Lew Aronson October 17, 2002
XFP Host System – Via Designs<br />
■ Buried Stripline Important for Minimizing EMI<br />
Finisar<br />
■ Vias for Transition from ASIC to Stripline and Stripline to XFP Connector<br />
�� Good Via Design is Critical to Meet XFI Specs<br />
■ Via Tradeoffs<br />
�� Blind Vias Offer Minimum Parasitics – Most Expensive<br />
�� Through Vias are Standard Technology but Result in Via Stub<br />
■ Design Balances Via Inductance with Capacitance to Ground Planes<br />
■ Fullwave Analysis by Ansoft Resulted in Practical Via Designs Used in<br />
Finisar Reference Board.<br />
Lew Aronson October 17, 2002
Ansoft Reference Via Design<br />
Finisar<br />
De-embedded<br />
S-parameter<br />
22 mil<br />
12 mil<br />
20.5 mil<br />
31.5 mil<br />
31.5 mil<br />
31.5 mil<br />
20.5 mil<br />
Lew Aronson October 17, 2002
Via Structure<br />
Finisar<br />
Ground<br />
Vias<br />
Ground Plane<br />
Cutouts<br />
Short Microstrip<br />
to SERDES<br />
Stub Beyond<br />
Stripline Layer<br />
Lew Aronson October 17, 2002
SMA – XFP Connector Section<br />
SMAs<br />
62 mil Board,<br />
12 layer stackup,<br />
FR-408<br />
Ansoft G-S-S-G Via<br />
Design<br />
Buried Stripline<br />
on Layer 9<br />
200mm<br />
XFP<br />
Conn<br />
Finisar<br />
SMAs<br />
XFP<br />
Test<br />
Coupon<br />
50Ω Term<br />
or Scope<br />
50Ω Term<br />
Lew Aronson October 17, 2002
TDR Measurement from SMA End<br />
SMA<br />
Vias<br />
SMAs<br />
XFP Conn<br />
Test Coupon<br />
Buried Stripline<br />
on Layer 9<br />
200mm<br />
XFP<br />
Conn<br />
Finisar<br />
Diff TDR<br />
<strong>10</strong>0 Ω<br />
~±5Ω<br />
XFP<br />
Test<br />
Coupon<br />
50Ω Term<br />
or Scope<br />
50Ω Term<br />
Lew Aronson October 17, 2002
TDR Measurement- SMA and Vias<br />
SMA<br />
Vias<br />
SMAs<br />
Vias<br />
Buried Stripline<br />
on Layer 9<br />
200mm<br />
XFP<br />
Conn<br />
Finisar<br />
Diff TDR<br />
XFP<br />
Test<br />
Coupon<br />
50Ω Term<br />
or Scope<br />
50Ω Term<br />
Lew Aronson October 17, 2002
Eye Diagram Transmission<br />
Input: ~ 3<strong>10</strong> mV p-p Single Ended<br />
<strong>10</strong>.3G, 2^31 Pattern<br />
SMAs<br />
Buried Stripline<br />
on Layer 9<br />
200mm<br />
XFP<br />
Conn<br />
Finisar<br />
Output: ~ 1<strong>10</strong> mV p-p Eye Opening<br />
(XFP spec 62.5 mV, CDR sensitivity <strong>10</strong> mV)<br />
XFP<br />
Test<br />
Coupon<br />
50Ω Term<br />
or Scope<br />
50Ω Term<br />
Lew Aronson October 17, 2002
Internal 2^31 PRBS<br />
Generation<br />
XBI Mux<br />
Demux<br />
SERDES – XFP Connector<br />
Buried Stripline<br />
on Layer 9<br />
200mm<br />
XFP<br />
Conn<br />
Finisar<br />
Output: ~ 150 mV p-p<br />
Eye Opening<br />
(XFP spec 62.5 mV)<br />
XFP<br />
Test<br />
Coupon<br />
50Ω Term<br />
or Scope<br />
50Ω Term<br />
Lew Aronson October 17, 2002
Interoperability Results – Quake XBI – Mux/Demux<br />
Finisar<br />
■ Quake QT2011 on Reference Design Board Provides PRBS31 Pattern<br />
■ 8” of Buried Stripline<br />
■ XFP Transceiver Loopbacked over <strong>10</strong> km Fiber<br />
■ No Errors Detected by Quake PRBS Error Detectors<br />
Internal 2^31 PRBS<br />
Generation<br />
Quake<br />
QT2011<br />
XBI Mux<br />
Demux<br />
Buried Stripline<br />
200mm<br />
XFP Conn<br />
Finisar XFP<br />
<strong>10</strong> km<br />
SMF<br />
Lew Aronson October 17, 2002
Finisar Ref<br />
Board<br />
SONET Jitter Measurement<br />
Acterna SONET<br />
Jitter Tester<br />
Quake SERDES<br />
with 2^31 PRBS<br />
Generator<br />
Epson 1 ps<br />
RMS Clock<br />
Finisar<br />
XFP<br />
Module<br />
Measured RMS<br />
Jitter (Spec<br />
0.01 UI)<br />
Measured p-p Jitter<br />
(Spec 0.<strong>10</strong>0 UI)<br />
Finisar<br />
Lew Aronson October 17, 2002
Critical Modeling Issues for XFP<br />
■ Host Board Design<br />
�� Via Structures, Transmission Lines<br />
■ Host Board ASIC<br />
�� I/O Return Loss from Package Design and IC Circuit Combination<br />
■ XFP Connector<br />
�� Presently Very Significant Source of Reflections (but good enough)<br />
�� Improved Connector Designs will Increase Margins<br />
■ XFP Module<br />
�� Return Loss of CDR I/O<br />
�� Many Internal Modeling Problems.<br />
�� New Issues Associated with Very Small Optoelectronic Packages<br />
■ EMI Issues<br />
�� Potential Host Board Design, Cage, and Module Details Affect EMI<br />
�� Compliance Always More Difficult at Higher Frequencies<br />
Finisar<br />
Lew Aronson October 17, 2002
Summary of XFP Advantages<br />
■ Smaller Size<br />
� � >4x reduction in transceiver footprint relative to XENPAK<br />
�� Allows minimum width transceivers<br />
Finisar<br />
�� 16 ports per linecard will be supported at 1.5W or 2.5W each<br />
■ Lower Power<br />
� � >2x reduction in power dissipation in some cases<br />
(2.5W vs. 6W transponders)<br />
�� Elimination of XENPAK board cutout requirement<br />
Greater Board Density<br />
Lew Aronson October 17, 2002
Summary of XFP Advantages<br />
■ Significant Cost Reduction<br />
Finisar<br />
�� Elimination of Mux/Demux and XAUI ICs from <strong>the</strong> Transceiver<br />
�� Protocol independence allows Volume Consolidation<br />
�� Eventual Multiport Host ASICs Much Easier<br />
■ Datacom Economics<br />
�� Lower cost driven by Standardization and High-volume Production<br />
�� Receptacle Optics and Hot-pluggability allow Flexible System Design<br />
Lowest Overall System Cost<br />
Lew Aronson October 17, 2002
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