TN1050 - Lattice Semiconductor

Appendix C. VHDL Example for DDR Input and Output Modules
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
10-24
LatticeECP/EC and LatticeXP
DDR Usage Guide
entity ddr_mem is
port( dq : inout std_logic_vector(7 downto 0 );
dqs : inout std_logic;
clk : in std_logic; -- core clock
clk90 : in std_logic; -- 90 degree phase shifted clock from the pll
reset : in std_logic;
uddcntl : in std_logic;
read : in std_logic;
dataout_p : in std_logic_vector(7 downto 0);
dataout_n : in std_logic_vector(7 downto 0);
datatri_p : in std_logic_vector(7 downto 0);
datatri_n : in std_logic_vector(7 downto 0);
dqstri_p : in std_logic;
dqstri_n : in std_logic;
ddrclk : out std_logic;
datain_p : out std_logic_vector(7 downto 0);
datain_n : out std_logic_vector(7 downto 0);
dqsc : out std_logic;
prmbdet : out std_logic;
lock : out std_logic;
ddrclkpol : out std_logic);
--*****DDR interface signals assigned SSTL25 IO Standard *************
ATTRIBUTE IO_TYPE : string;
ATTRIBUTE IO_TYPE OF ddrclk : SIGNAL IS "SSTL25D_II";
ATTRIBUTE IO_TYPE OF dq : SIGNAL IS "SSTL25_II";
ATTRIBUTE IO_TYPE OF dqs : SIGNAL IS "SSTL25_II";
end ddr_mem;
architecture structure of ddr_mem is
--*****DDR Input register*********************************************
component IDDRXB
port(
D : in STD_LOGIC;
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
CE : in STD_LOGIC;
LSR : in STD_LOGIC;
DDRCLKPOL : in STD_LOGIC;
QA : out STD_LOGIC;
QB : out STD_LOGIC);
end component;