Virtual Machines – Architectures, Implementations, and ... - Hot Chips

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Decode-Dispatch Interpretation while (!halt) { inst = code(PC); opcode = extract(inst,31,6); switch(opcode) { case LdWordAndZero:LdWordAndZero(inst); case ALU: ALU(inst); case Branch: Branch(inst); . . .} } Instruction function list August 2005 VM Intro (c) 2005, J. E. Smith 28
Instruction Functions: Load LdWordAndZero(inst){ RT = extract(inst,25,5); RA = extract(inst,20,5); displacement = extract(inst,15,16); source = regs[RA]; address = source + displacement ; regs[RT] = data[address]; PC = PC + 4; } August 2005 VM Intro (c) 2005, J. E. Smith 29
Page 1 and 2: Virtual Machines: Architectures, Im
Page 3 and 4: Introduction Why are virtual machin
Page 5 and 6: Virtualization � Similar to abstr
Page 7 and 8: The “Machine Machine” � Diffe
Page 9 and 10: Virtual Machines add Virtualizing S
Page 11 and 12: Taking a Unified View “The subjec
Page 13 and 14: Process VMs � Execute application
Page 15 and 16: HLL VMs � Java and CLI are recent
Page 17 and 18: Composition OS 1 apps 2 ISA 2 OS 1
Page 19 and 20: Summary (Taxonomy) VM type (Process
Page 21 and 22: Emulation: Interpretation and Binar
Page 23 and 24: Definitions NOTE -- there are no st
Page 25 and 26: Definitions � Source ISA or binar
Page 27: Interpreter State � Hold complete
Page 31 and 32: Binary Translation � Generate “
Page 33 and 34: Binary Translation Example x86 Sour
Page 35 and 36: The Code Discovery Problem � In o
Page 37 and 38: Dynamic Translation SPC to TPC Look
Page 39 and 40: Tracking the Source PC � Can alwa
Page 41 and 42: Example PowerPC Translation 9AC0: l
Page 43 and 44: Software Jump Prediction � Form o
Page 45 and 46: Emulation Summary � Decode/Dispat
Page 47 and 48: Process Virtual Machines
Page 49 and 50: Process VM Architecture Initializat
Page 51 and 52: State Mapping � For best performa
Page 53 and 54: Direct (Hardware) Mapping � VM so
Page 55 and 56: Host OS Support � A system call w
Page 57 and 58: Self-referencing code � Original
Page 59 and 60: Exceptions: Traps � Can be detect
Page 61 and 62: PC Side Table code cache . . . bloc
Page 63 and 64: Recovering Memory State � Simple
Page 65 and 66: OS Call Emulation � Same source a
Page 67 and 68: Staged Emulation � Adjust optimiz
Page 69 and 70: Code Cache Management � Code Cach
Page 71 and 72: Pre-emptive Flush � Flush when pr
Page 73 and 74: System Environment � High level o
Page 75 and 76: Loaders � Requires two loaders
Page 77 and 78: Example: FX!32 � x86/Windows ABIs
Page 79 and 80:
Dynamic Binary Optimization
Page 81 and 82:
Profiling � Collect statistics ab
Page 83 and 84:
Collecting Profiles � Instrumenta
Page 85 and 86:
Improving Locality: Traces � Prop
Page 87 and 88:
Superblock Formation � Start Poin
Page 89 and 90:
Case Study: Intel IA-32 EL � Soft
Page 91 and 92:
IA-32 Optimizations � Floating po
Page 93 and 94:
IA-32 EL Performance � Where the
Page 95 and 96:
Code Patching Example Source Binary
Page 97 and 98:
Superblock Selection � Does not u
Page 99 and 100:
Performance � Compare with +o2
Page 101 and 102:
Performance Conclusions � Mostly
Page 103 and 104:
HLL VMs � Goal: complete platform
Page 105 and 106:
Modern HLL VMs � Superficially si
Page 107 and 108:
Modern HLL VMs � Compiler forms p
Page 109 and 110:
Security � A key aspect of modern
Page 111 and 112:
Garbage Collected Heap � Objects
Page 113 and 114:
Java “ISA ISA” � Includes •
Page 115 and 116:
Data Accessing Instruction stream o
Page 117 and 118:
Instruction Types � Pushing const
Page 119 and 120:
Bytecode Example public int perimet
Page 121 and 122:
Exception Table � Exceptions iden
Page 123 and 124:
Java Virtual Machine � An abstrac
Page 125 and 126:
Structure of Virtual Machine, contd
Page 127 and 128:
Protection Sandbox: Security Manage
Page 129 and 130:
Java Native Interface (JNI) � All
Page 131 and 132:
Microsoft CLI � Common Language I
Page 133 and 134:
Microsoft CLI and MSIL � Similar
Page 135 and 136:
Summary: HLL VMs vs. Process VMs
Page 137 and 138:
Co-Designed VMs � Design hardware
Page 139 and 140:
Precise Exceptions � Traps must b
Page 141 and 142:
Precise Interrupts via checkpoint/r
Page 143 and 144:
Page Fault Compatibility � Major
Page 145 and 146:
Input/Output � VMM itself uses no
Page 147 and 148:
Transmeta Crusoe Block Diagram Shad
Page 149 and 150:
Alias Hardware � To allow re-sche
Page 151 and 152:
Another Example: IBM AS/400 � A v
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