Stability of the Master Oscillator for FLASH at DESY

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6 2 DEFINITION OF STABILITY TERMS 2 Definition of stability terms The terms to understand the stability considerations of the reference source mentioned in section 1 are presented here. These are phase noise, integrated timing jitter, drifts and the transport of phase noise through a phase locked loop that serves as a frequency multiplier. For time durations faster than 100 ms one has to investigate the phase noise properties of an RF 4 source and all fluctations slower than 100 ms are denoted as drifts. 2.1 Phase noise description in time and frequency domain A general description of a carrier frequency ω0 that is disturbed in amplitude and phase in time domain is: u(t) = A0[1 + ∆a(t)] e jω0t + j∆ϕ(t) where ∆a(t) is the instantaneous contribution of amplitude fluctuations and ∆ϕ(t) is the contribution of phase fluctuations. The further description assumes much smaller amplitude fluctuations than phase fluctuations (∆a(t)
2.2 Transmission of amplitude - and phase noise in linear networks 7 2.2 Transmission of amplitude - and phase noise in linear networks To describe the transmission of amplitude - and phase noise from the input to the output in a linear network one makes use of a conversion matrix equation 6 that relates the amplitude - and phase fluctuations at the input of the network to the output of the network. � ∆aout A0 ∆ϕout � � �� noisy output = � � � � ∆ain Kaa Kaϕ A0 Kϕa Kϕϕ ∆ϕin � �� conversion matrix noisy input + � ∆anetwork A0 ∆ϕnetwork � � �� noisy network Amplitude - and phase fluctuations are phasors describing the noise as an AM 5 ∆a and PM 6 ∆ϕ at an offsetfrequency ∆ω from the carrier ω0 [5]. The amplitude of the AM contribution is normalized to the carrier voltage A0. The input amplitude - and phase noise is directly converted by the factors Kaa and Kϕϕ. The factors Kaϕ and Kϕa describe how an AM converts to a PM and how a PM converts to an AM. The additional vector accounts for the AM and PM noise contribution of the network. 2.3 Phase noise in a mutiplier chain An input phase noise ∆ϕin(t) is converted by an ideal multiplier N to the output ∆ϕout(t) that means that Kϕϕ = N. Assuming that Kaϕ = 0 and the multiplier is ideal the equation describing this reads: The spectral densities are gained from equation 3 and read: ∆ϕout(t) = N ∆ϕin(t) (7) Sϕout(f) = N 2 Sϕin (f) (8) The assumption of an ideal multiplier is not valid in all circumstances since the network will add it’s own noise to the output e.g. especially 1/f noise is a big noise source in semiconductors. 2.4 Phase noise model of a phase locked loop A common method to generate high stable reference frequencies is to make use of a phase locked loop (PLL). This will reduce the overall output power spectral density as derived in the previous section. The output frequency is phase locked to a reference source at a lower frequency [2.4]. The modeling of phase noise in a PLL follows the description in [2]. This model describes how the phase noise of the reference (Sϕ REF(f)) and the VCO (Sϕ V CO(f)) are filtered by the loop transfer function. This model excludes noise sources in the Phasedetector (PD), Loop Filter (LF) and Frequency divider (N). 5 Amplitude Modulation 6 Phase Modulation (6)
Page 1 and 2: Stability of the Master Oscillator
Page 3 and 4: CONTENTS 3 Contents 1 Motivation 4
Page 5: 1.2 Assignment 5 1.2 Assignment The
Page 9 and 10: 2.5 Integrated phase noise and timi
Page 11 and 12: 3.2 Drift measurement methods 11 3.
Page 13 and 14: 3.2 Drift measurement methods 13 Fi
Page 15 and 16: 3.2 Drift measurement methods 15 Fi
Page 17 and 18: 4.1 Overview 17 The frequencies req
Page 19 and 20: 4.2 Low Power Part 19 Figure 12: Lo
Page 21 and 22: 4.2 Low Power Part 21 fredquency [M
Page 23 and 24: 4.2 Low Power Part 23 Figure 17: Ph
Page 25 and 26: 4.2 Low Power Part 25 81 MHz VCXO c
Page 27 and 28: 4.2 Low Power Part 27 Sensitivity [
Page 29 and 30: 4.2 Low Power Part 29 The circuit f
Page 31 and 32: 4.2 Low Power Part 31 The same has
Page 33 and 34: 4.2 Low Power Part 33 Magnitude (dB
Page 35 and 36: 4.2 Low Power Part 35 4.2.3 Divider
Page 37 and 38: 4.2 Low Power Part 37 fundamental 1
Page 39 and 40: 4.3 1.3 GHz and 2.856 GHz phase loc
Page 49 and 50: 4.4 High Power Part for amplificati
Page 51 and 52: Acknowledgements I would like to th
Page 53 and 54: Figure 61: Blockdiagram low power p
Page 55 and 56: Figure 63: Blockdiagram of 1300 MHz
Page 57 and 58:
REFERENCES 57 References [1] vuv-fe
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Stability of the Master Oscillator for FLASH at DESY

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