THIAGARAJAR COLLEGE OF ENGINEERING: MADURAI – 625 015 ...

1. Antoniou, A. “Digital filters - Analysis, Design and Applications”, McGraw-Hill
International Editions, Electrical Engineering series, 2nd. ed., 1993,
2. Sanjit K. Mitra, “Digital Signal Processing – A Computer based Approach”, Tata McGraw
Hill, 2001.
3. Vinay K Ingle and John G Proakis, “ Digital Signal Processing using MATLAB”, Brroks
Cole, 1999
4. John G Proakis, “Digital Signal Processing: Principles, Algorithms and Applications”,
Pearson Education, 1995.
5. Brian D O Anderson and John B Moore, “ Optimal Filtering”, Dover Publications, 2005
D46 DIGITAL LOGIC WITH VHDL DESIGN
UNIT I: Design Concepts : Digital Hardware - Standard Chips Programmable Logic Devices – Custom –
Designed Chips – Design Process – Design of Digital Hardware – Basic Design Loop – Design of a Digital
hardware Unit – Introduction to CAD tools – Design - Entry Synthesis – Functional Simulation –
Introduction to VHDL – Representation of Digital Signals in VHDL – Writing Simple VHDL Code – How
Not to Write VHDL Code. (10 Periods)
UNIT II: Optimized Implementation of Logic Functions : Karnaugh Map – Strategy for Minimization –
Minimization of Product – of - Sums Forms – Incompletely Specified Functions – Multiple – output
Circuits – NAND and NOR Logic Networks – Multilevel Synthesis – Analysis of Multilevel Circuits –
Cubical Representation – Minimization using Cubical Representation – Practical Considerations – CAD
Tools. (10 Periods)
UNIT III: Combinational Circuit Building Blocks : Multiplexers – Decoders – Encoders – Code
Converters – Arithmetic Comparison Circuits – VHDL for Combinational Circuits-Assignment statements-
Selected signal assignment-Conditional signal assignment-Generate statements-Process statement-Case
statement. (10 Periods)
UNIT IV: Flip-Flops, Registers and Counters : Basic Latch – Gated SR Latch - Gated SR Latch with
NAND Gates – GATED D Latch – Master-Slave And Edge – Triggered D Flip-Flops – T Flip-Flop – JK
Flip-Flop – Summary Of Terminology- Resisters – Counters – Using Storage Elements With CAD Tools –
Using Registers and Counters with CAD Tools – Design Examples.
(10 Periods)
UNIT V: Synchronous Sequential Circuits: Basic Design Steps – State Assignment Problem – Mealy
State Model – Design of FSM Using CAD tools VHDL Code for Moore-type FSMs- Synthesis of VHDL
Code – Simulating and Testing the Circuit – Serial Adder Example – State Minimization – Counter Design
– FSM as an arbiter Circuit – ASM Charts. (10 Periods)
Text Book:
1. Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with VHDL Design” Tata
McGraw Hill edition, 2001.
Reference Books:
1. Navabi, “VHDL Modelling”, McGraw Hill, 1997
2. J.Bhaskar, “VHDL Primer”, Pearson Education, 1999.
D47 ANALOG COMMUNICATION LAB