SPICE Models for SIPMOS Components - Infineon

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Power Semiconductor Application Note AN_PSM1e
SPICE Models for SIPMOS Components
Purpose: Clarification of SIPMOS - SPICE models V1.0
Author: Dr. P. Türkes, Dr. M. März, P. Nance
1) Introduction
Powerful new-generation personal computers with a fast main processor and a math-coprocessor
allow circuit developers to benefit inexpensively from CAD methods, since such computers make it
possible to run easy-to-use network simulation programs.
A problem that arises, especially when simulating power electronics circuits, is that the typical power
electronics components, such as power MOSFETs, diodes and so on, do not figure in the standard
component libraries of simulators. In such cases, the manufacturer of these power components
supplies equivalent circuits (‘subcircuits’) which approach the typical behaviour of the power
components. Inevitably, such a subcircuit is made up of the standard components of the simulators.
So that these models can be used in as many common simulation programs as possible, the
subcircuit must be described in accordance with the original SPICE 2G6 version. The reason for this
approach is that, whilst compatibility between all available PC SPICE versions is only limited,
compatibility with the original version is unrestricted. However, simulations of the operation of the
component in ultimate regions is not possible with this method.
The next section describes the subcircuits which are used for the SIPMOS power transistors in the
libraries BUZ_L0.LIB and BSS_L0.LIB. The models are suitable to simulate the DC and AC behaviour
in standard circuits and under safe ambient conditions.
A section which describes the model is followed by an overview of the measurement and evaluation
methods for establishing the parameters which determine the behaviour of the SIPMOS transistor in
the subcircuit.
After this, the output and gate loading characteristics of the component are simulated on the basis of
the measurement circuits used and compared with the actual measurement.
Finally, and by way of example, a user circuit is simulated.
2) Model description
The SPICE basic model of the SIPMOS power transistors described below emerges from the nature
of the vertical MOS structure.
Fig. 1: SIPMOS structure

Power Semiconductor Application Note AN_PSM1e
No detailed description of such a vertical MOS structure is given here; please refer to the relevant
literature.
Network elements that emerge from the technological structure have already been drawn in the crosssection
of the component. For example, the drift distance is designated as resistance Rd.
The SPICE subcircuit for the SIPMOS transistor arising from the component cross-section above is
shown in Fig. 2. The various voltage interdependencies have been taken into account.
n-channel enhancement n-channel depletion
Fig. 2: The SIPMOS Level-1 SPICE transistor models
(The basic structure of the subcircuit applies both to power and small-signal transistors)
The network consists of equivalent components which describe on the one hand the DC and on the
other the AC and transient behaviour of the transistor. It is important to distinguish between the
following subcomponents:
DC-relevant subcomponents:
a) The inner MOSFET MBUZ describes the characteristic curves of the component and its transfer
characteristic.
b) The source resistance RS is for negative feedback to the gate at high currents.
c) The drain resistance, which may be voltage-dependent, is represented as ’depletion mode
MOSFET’ MVRD. The voltage dependence of the drain resistance is caused by modulation of
the conductivity in the drain region as a consequence of a field effect of the drain-source pn
junction. This field effect narrows the current path between the source islands of the MOSFET
when the drain-source voltage is applied; see Figure 1.
The sum of the resistances MBUZ, RS and MVRD gives the ‘on-state resistance’ of the
component.
d) The reverse diode DREV is for backward operation of the transistor.
AC-relevant subcomponents
a) The constant gate-source capacitance CGS models the switching time-constants.
b) The voltage-dependent gate-drain capacitance (or Miller capacitance) COX, together with the
diode DGD, describe the modelling of the gate charging process. COX is provided as a con-
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Power Semiconductor Application Note AN_PSM1e
stant capacitance to describe the gate-drain capacitance in the off-state and DGD as the
barrier-layer capacitance for this in the on-state. Depending on the working point, these two
parts of the gate-drain capacitance are switched to M2 and M3 by the two MOSFETs.
This means that the only purpose of subcomponents M2 and M3 is to act as auxiliary components
to set the working point of the voltage-dependent gate-drain capacitance.
d) The barrier-layer capacitance Cjo and the transfer time-constant TT of the reverse diode DREV
fully model the switching time-constants.
e) The lead inductances LG, LD and LS influence the rates at which the currents rise. In particular,
the source inductance LS causes current feedback to the gate circuit.
f) The auxiliary voltage source VGC sets the capacitance process.
This auxiliary voltage source makes it possible to take account of the influence of technological
steps which reduce the starting voltage of the MOSFET and at the same time shift the
capacitance curves toward higher voltages. This circuit variant is not used in all component
models. Such an auxiliary voltage source is used, for instance, in the types known as ’logic
level’ types.
In these, a constant charge, which can be represented according to the displacement law as a
fixed voltage source, is applied to the MOS capacitor.
g) Gate resistance RG
The gate resistance delays the recharging of the MOS capacitor during switching. The timeconstant
resulting from the combination of RG and CGS is the measure for the setting of the
resistance RG. The value of RG can only be determined directly with difficulty.
It is therefore suggested, as far as use of the model is concerned, that the switching
time-constant should be adapted to the conditions by means of external resistances in
the gate circuit.
The next section explains how to measure and calculate the parameters which describe the
equivalent components.
3) Parameter extraction
a) Parameters from the MOSFET input characteristic I d = I d (U g ) at U ds = const
The input characteristic of the component can be drawn with a characteristic recorder. Data
collection is simplified if a recorder with digital memory and a digital output is used.
The parameters to be extracted depend mainly on the basic model used to describe the
MOSFET current as a function of the applied voltages.
The basic model chosen for the inner MOSFET of this SIPMOS-SPICE description is
introduced in the literature as a ’LEVEL 1’ model and describes the MOSFET transfer function
Id = Id(Ug,Uds) as a function of only two parameters:
i) I d = Kp*((U gs - U t )*U ds - U ds 2 /2) triode region
ii) I d = Kp/2*(U gs - U t ) 2
saturation region
If current negative feedback via a source resistance Rs is to be taken into account, equation ii)
must be modified as follows:
iii) I
d
= Kp/2*(U
g
- U
t
- I
d
*R
s
) 2
Using this equation and a ’least mean square’ fit, the parameters transfer function Kp, starting
voltage Ut of the MOSFET and the value of the source resistance Rs are determined. Taking
the BUZ 12 as an example, this process is represented by comparison of the measurement
curve and the function i) adapted to it (Fig. 3). The corresponding evaluation routine is
programmed with the aid of the mathematical utility program MATHCAD.
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√
I d
A
Power Semiconductor Application Note AN_PSM1e
10
8
6
4
2
0
3.5 4 4.5 5 5.5 6 6.5 7
Fig. 3: Evaluation of the transfer characteristic
U DS [V]
b) Parameters from the characteristic I d = I d (U g = U cc )
UG = UDS
After evaluation of the transfer characteristic, the parameters Kp, Vt and Rs are known. This
makes it possible to calculate a characteristic Id (Ug,Uds) corresponding to the subcircuit (Fig. 2),
in order to determine the voltage-dependent drain resistance RD. In other words, the voltagedependent
resistance is determined as a current/voltage characteristic from the comparison of the
calculated and the simulated output characteristic.
I d [A]
50
40
30
20
10
0
standard
DMOS model
(SPICE)
measured
device
characteristic
UG = const.
0 0.25 0.5 0.75 1 1.25 1.5
U DS [V]
Fig. 4: Comparison of the calculated and the measured output characteristics
at Ug = 20V to determine the drain resistance (Example: BUZ12)
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I d [A]
Power Semiconductor Application Note AN_PSM1e
50
40
30
20
10
0
0 0.25 0.5 0.75 1 1.25 1.5
U DS (MVRD) [V]
Fig. 5: Drain resistance characteristic determined from the curves of Fig. 4
Apart from this, voltage dependency of the drain resistance may only be expected with components
having higher blocking voltages. Such behaviour is only weakly present in high-current types. Here
it is sufficient to include a constant resistance in the network instead of the auxiliary transistor
MVRD. This constant drain resistance can be worked out from the known on-state conductivity of
the component, the extracted source resistance and the MOSFET transfer characteristic.
c) Characteristic of the reverse diode
Semi-logarithmic extrapolation of the diode forward current gives the reverse current IS and the
’ideality factor’ N, which characterise the forward characteristic:
iv) I di = IS*(exp(U di /(N*UT)) - 1) where UT is the temperature voltage.
d) Parameters from AC characteristics
Capacitance parameters:
The basis for the measurement and thus for the evaluation is the subcircuit of the three
capacitances CDS and CGD of the MOS part and CJ of the reverse diode, in a star arrangement.
The measurements are made in configurations familiar from the application notes of the
capacitance bridge manufacturers. The measurement frequency is set to 1 MHz and the drainsource
voltage is varied in the working range at constant gate voltage. The result is a family of
characteristics for the voltage-dependent capacitances.
A typical family of measurement curves for CGS, CGD and CDS is shown in Figure 6.
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Power Semiconductor Application Note AN_PSM1e
10000
C [pF]
1000
100
C DS
C GD
C GS
0 5 10 15 20 25 30
U DS [V]
Fig. 6: Voltage-dependent capacitances CGS, CGD and CDS (BUZ100S)
It is evident even here that CGS is almost independent of the voltage, whereas CDS and
CGD show distinct voltage-dependent behaviour. The value of CGS can be taken directly
from such a measurement.
The two voltage-dependent capacitances CDS and CGD must now be introduced into the
network model as follows:
Taking the SPICE-specific description of a barrier layer capacitance in the SPICE diode
model as a starting point, it would seem natural to adapt the measured capacitance curves to
the SPICE barrier layer model. For the behaviour of CDS, this is easily done by adapting the
function
v) CDS = CDS0 * ( 1 + V
di
/V
j
) m
built into SPICE in order to determine the parameters CDS0, Vj, m.
The procedure for the gate-drain capacitance is exactly the same. The measured behaviour is
adapted to the function v) and the corresponding parameters are determined.
However, because of the properties of a MOS capacitance, it is essential to ensure that, when
the gate-drain voltage is negative, there is a constant capacitance COX. This is achieved by
the auxiliary circuit with the two MOSFETs M2 and M3, which switch in the barrier-layer
capacitance of the diode DGD when the drain-gate voltage is positive and the constant
capacitance COX when the drain-gate voltage is negative. Initially, the value of the parameter
COX is the gate-drain capacitance at Ugd = 0V. The MOSFET parameters for M2 and M3
must be set so that the MOSFETs switch on in the region of 0V and then exhibit a low
resistance. Dynamic parameters are not transfered to these MOSFETs.
e) Parameters from transient measurements, the transit time TT
In reverse operation of the MOSFET, charge carriers are injected into the reverse diode. For
this case, it is necessary to determine the parameter TT of the SPICE diode in order to be
able to describe the decay of charge carriers after recommutation of the diode. The
parameter TT is determined by measuring the carrier charge at the reverse diode.
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Power Semiconductor Application Note AN_PSM1e
f) The lead inductances LG, LS, LD
Intrinsic component inductances are determined by measuring the lengths and cross-sections
of the leads and then calculating the self-inductance, as derived in text books.
The parameter extraction method outlined here provides a simple way of determining the
parameter values needed for modelling the subcircuit.
The next section shows that, with the parameters determined, the SIPMOS power transistor model
presented here is capable of correctly simulating both the measurement results of the parameter
extraction circuits and an inverter circuit with inductive load.
4) Limits of the model
The simplified approach to SPICE modelling of SIPMOS transistors comes up against its limits
when the model is operated in a circuit in a range in which, in reality, the avalanche breakdown of
the reverse diode occurs. None of the phenomena that lie beyond the exponential rise of the
reverse blocking current, such as the activation of the parasitic bipolar transistor (not shown on the
cross-section), are reproduced by the SPICE simulation. Moreover, the effect of component
temperature rise is not taken into account. This problem can be tackled by including in the SPICE
model parameters determined at a higher temperature.
5) Modelling examples
The procedure for simulating typical circuits is explained below using a number of examples. First
the DC output characteristics are simulated, then transient characteristics are determined in some
standard circuits. Finally a DC chopper converter circuit is simulated in order to demonstrate how
powerful these models are.
i) Simulation of the output characteristic
Standard setup with drain-source voltage sweep and the gate voltage as a parameter.
The gate and the drain of the model network are connected to separate power supplies. This is the
simplest test circuit.
Fig. 7: Test circuit to simulate the output and transfer characteristics
When simulating the output characteristic and the transfer characteristic, only the DC card is used
for simulation control. The output and transfer characteristics are simulated in a range which
corresponds to the range of application of the measurements. With suitably prepared measurement
data, the result of the simulation is comparable to the result obtained by measurement.
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Power Semiconductor Application Note AN_PSM1e
Fig. 8: Comparison of simulation and measurement, using the example of the
output characteristic field at different gate voltages of the BUZ41AL
(IS-SPICE result)
ii) Gate charge
Simulation of the measurement circuit as shown in the data book
A transient simulation is demonstrated using the gate charge simulation. The essential parts of
the measurement circuit in the simulation correspond to the actual measurement setup. This
permits direct comparison of the simulated and the measured results when the simulation is
complete. The component used in this measurement circuit is the BUZ 12 AL.
Fig. 9: Measurement circuit for determining the behaviour of the gate
voltage
for operation with constant load current and constant gate control.
The equivalent circuit shown here reveals an essential point for the simulation of complex
circuits. The circuit to be simulated is first reduced to its essential elements.
The simulation parameters which determine the accuracy of calculation for current, voltage and
charge (abstol = tolerance on calculation of the absolute current, vntol = tolerance on calculation
of absolute voltage and chgtol = tolerance on calculation of absolute charge) are then adapted to
the problem. This step calls for a certain amount of caution and experience.
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The last step is the definition of the transient control instruction, in which both the final value and
the time control step width are set.
Fig. 10: Result of gate charge simulation (1) on the BUZ12AL and comparison with
the measured gate charge curve (2)
iii) Inverter with inductive load
This case shows how a SIPMOS-SPICE model is used in a DC chopper converter circuit.
In such a circuit, an inductive load is charged to a particular value of current via the pulse control
factor. During the „off“-phases of the switching transistor the inductive load drives the current
through a second transistor connected as a free-wheeling diode.
BUZ12AL
BUZ12AL
Fig. 11: DC chopper converter circuit with BUZ12AL
One result of simulating the starting of a DC chopper converter circuit is shown in Fig. 12. As
expected, the current (curve 0) rises with time in accordance with the coil values. At the same
time, the drain-source voltage of the switched-on MOSFET increases. The power dissipation
could thus be calculated from the two curves, leading to an estimate of the temperature rise of
the component.
This simulation also requires the simulation parameters for current, voltage and charge (abstol,
vntol and chgtol) to be set under the conditions mentioned above.
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Appendix:
Power Semiconductor Application Note AN_PSM1e
time in sec
Fig. 12: Coil current (0) and drain-source voltage (2) in a DC chopper converter
circuit as in Fig. 11
Note: The voltage peak in the simulation results from a numerical instability
a) Subcircuit of BUZ12AL (high-current MOSFET)
.SUBCKT BUZ12AL 1 2 3 */ 1:Gate 2: Source 3:Drain /*
LS 5 2 7N
LD 83 3 5N
RG 4 11 5.5M
RS 5 76 40M
D12AL 76 83 DREV
.MODEL DREV D CJO=2.925N RS=20M TT=500N IS=300P BV=50
M12AL 71 11 76 76 MBUZ
.MODEL MBUZ NMOS VTO=2.12 KP=24.66
M2 11 71 8 8 MSW
.MODEL MSW NMOS VTO=0.001 KP=10
M3 71 11 8 8 MSW
COX 11 8 5.194N
DGD 8 71 DCGD
.MODEL DCGD D CJO=5.194N M=0.516 VJ=0.072
CGS 76 11 2.1N
RDR 71 83 10M
LG 4 1 7N
.ENDS
b) Subcircuit of BUZ41A (high-voltage MOSFET)
.SUBCKT BUZ41A 1 2 3 */ 1:Gate 2: Source 3:Drain /*
LS 5 2 7N
LD 87 3 5N
RG 4 11 5.5M
RS 5 76 34M
D41A 76 87 DREV
.MODEL DREV D CJO=420P RS=20M TT=500N IS=300P BV=500
M41A 86 11 76 76 MBUZ
.MODEL MBUZ NMOS VTO=3.313 KP=7.66
M2 11 86 8 8 MSW
.MODEL MSW NMOS VTO=0.001 KP=10
M3 86 11 8 8 MSW
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Power Semiconductor Application Note AN_PSM1e
COX 11 8 2.5N
DGD 8 86 DCGD
.MODEL DCGD D CJO=250P M=0.675 VJ=1.301
CGS 76 11 870P
MDR 87 86 86 86 MVRD
.MODEL MVRD NMOS VTO=-13.1 KP=0.068
LG 4 1 7N
.ENDS
c) Subcircuit of BSP149 (n-channel depletion MOSFET)
SUBCKT BSP149 1 2 3 */ 1:Gate 2: Source 3:Drain /*
LG 95 1 7N
LS 5 2 7N
LD 97 3 5N
RG 95 99 5.5M
RS 5 76 578M
D149 76 97 DREV
.MODEL DREV D CJO=0.03N RS=20M TT=35N IS=300P BV=200
M149 98 99 76 76 MBUZ
.MODEL MBUZ NMOS VTO=-1.334 KP=1.022
M2 87 98 8 8 MSW
.MODEL MSW NMOS VTO=0.001 KP=5
M3 98 87 8 8 MSW
COX 87 8 0.08N
DGD 8 98 DCGD
.MODEL DCGD D CJO=59P M=0.542 VJ=0.979
CGS 76 99 225P
VGC 87 99 3
MHELP 98 98 97 98 MVRD
.MODEL MVRD NMOS VTO=-16.18 KP=0.34
.ENDS
d) Control instruction for transient simulation of the DC chopper converter
* Width and final value of time step
.TRAN 10U 2M
* Parameters for transient analysis and calculation accuracy for voltage (vntol), current
(abstol) and charge (chgtol)
.OPTIONS LIMPTS=5000 ITL1=2000 ITL4=1200 ITL5=150000
+ VNTOL=1M ABSTOL=1U CHGTOL=10P
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