MT-090: Sample-and-Hold Amplifiers - Analog Devices

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Figure 23: Using a SHA as a DAC Deglitcher MT-090 Rather than use a single ADC per channel in a simultaneous sampled system, it is often more economical to use multiple SHAs followed by an analog multiplexer and a single ADC (Figure 24). Similarly, in data distribution systems multiple SHAs can be used to route the sequential outputs of a single DAC to multiple channels as shown in Figure 25; although this is not as common, as multiple DACs usually offer a better solution. Figure 24: Simultaneous Sampling Using Multiple SHAs and a Single ADC Page 18 of 21
Figure 25: Data Distribution System Using Multiple SHAs and a Single DAC MT-090 A final application for SHAs is shown in Figure 26, where SHAs are cascaded to produce analog delay in a sampled data system. SHA 2 is placed in hold just prior to the end of the hold interval for SHA 1. This results in a total pipeline delay greater than the sampling period T. This technique is often used in multi-stage pipelined subranging ADCs to allow for the conversion delays of successive stages. In pipelined ADCs, a 50% duty cycle sampling clock is common, thereby allowing alternating clock phases to drive each SHA in the pipeline (see tutorial MT-024 for details on pipelined ADCs). Figure 26: SHAs Used for Analog Pipelined Delay Page 19 of 21
Page 1 and 2: Sample-and-Hold Amplifiers INTRODUC
Page 3 and 4: Figure 1: Basic Sample-and-Hold Cir
Page 5 and 6: Figure 4: Track-to-Hold Mode Pedest
Page 7 and 8: Figure 7: Effective Aperture Delay
Page 9 and 10: MT-090 Droop can be reduced by incr
Page 11 and 12: MT-090 Different capacitor material
Page 13 and 14: MT-090 drive currents reverse biase
Page 15 and 16: INTERNAL SHA CIRCUITS FOR IC ADCS M
Page 17: MT-090 Track mode linearity is larg
Page 21: Page 21 of 21 MT-090 11. Walt Keste

MT-090: Sample-and-Hold Amplifiers - Analog Devices

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