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The Signetics 2650 - The MESSUI Place

The Signetics 2650 - The MESSUI Place

The Signetics 2650 - The MESSUI

GETTING INTO MICROPROCESSORS The Signetics 2650 We continue our survey of microprocessor chips and systems with this article, which takes a more detailed look at the Signetics 2650 device and its currently available evaluation kits. Although a relatively recent entry into the market, the 2650 has a particularly powerful instruction set and very flexible interfacing requirements. It seems likely to become the preferred 8-bit device for general purpose microcomputers. The Signetics 2650 is an 8-bit microprocessor which is made using well proven N-channel MOS technology. It runs from a single +5V supply, which tends to simplify power supply requirements. All inputs and outputs are TTL compatible, and the chip requires only a single-phase clock signal input. As the chip operates in static mode, there is no minimum clock frequency. With the original 2650 chip, the maximum clock frequency was 1.25MHz, giving instruction cycle times of from 4.8 to 9.6 microseconds. However, the currently available 2650-1 chip is rated to operate up to 2MHz, reducing the instruction cycle times to the range 3.6 — 7.2us. The broad architecture of the 2650 chip is shown in the block diagram below. It uses an 8-bit bidirectional data bus, and a separate 15-bit address bus. This gives a direct addressing range of 32,768 bytes 50011511 MA by JAMIESON ROWE T ■ J•N 400•15.5 st ar. 41. ssalinoL 'IOM £005415 RI GIST1 • 051•540 4005151 5101511 0 11 500 5151 1D01• (32k), arranged in four pages of 8,192 bytes. There are seven 8-bit addressable general purpose registers, one of which is the accumulator RO. The remaining six make up the register stack, and are arranged in two groups of 3 selectable by one of the bits in the Program Status Word register (PSW). Apart from the register stack there is a subroutine return address stack, consisting of eight 15-bit registers. This allows storage of up to eight return addresses, and hence provides for up to eight levels of subroutine nesting. (A nested subroutine is a subroutine itself called by a subroutine.) The arithmetic and logic unit (ALU) performs arithmetic, logic and shifting functions. It operates on 8-bits in parallel, and uses carry-look-ahead logic. A second adder is used to increment the instruction address register (program atilt511, ST ar• INI 5 55.,55 5.0•It TT INT( 55101 /A VW/5n IIGT 1,41504 LINIS 5•TIRRI/51 1'O LOGIC 55045AM ST •T US .4050 oNST RUCTION 5(015115 Of COOING £50 CONTROL LOCK The basic architecture of the 2650 microprocessor chip showing maior data, address and control paths. MOLT ;(-,e-r7 counter), and also to calculate operand addresses for the indexed and relative addressing modes. This separate address adder, together with the separate instruction address and operand address registers allows complex addressing modes to be implemented with no increase in instruction execution time. The PSW is a special purpose register which contains status and control bits. The PSW bits may be tested, loaded, stored, preset or cleared using instructions which affect the PSW. Three of the bits act as the pointer for the return address stack; two others act as a "condition code" register, which is affected by the results of compare, test and arithmetic instructions and may be used by conditional branch instruction; other bits store overflow, carry, the selection bit for the two register groups, an interrupt inhibit bit, a carry enable bit, a logical/arithmetic compare select bit, and flag and sense bits for external bitserial interfacing. It has been said that the 2650 has the most minicomputer-like instruction set of any microprocessor currently available. There are 75 basic instructions, but many of these are actually subdivided into a number of variations. For example the eight arithmetic instructions may be performed either with, or without car- COTIOITIOM COO! 550 SITIOK5 LOOK THONG LOGIC DATA RUT CLOCK

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