Quick introduction to reverse engineering for beginners

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mov ecx, [esp+10h+var_10] mov edx, [esp+10h+sz] loc_D6: ; CODE XREF: f(int,int *,int *,int *)+B2 mov esi, [esp+10h+ar2] lea esi, [esi+edi*4] ; is ar2+i*4 16-byte aligned? test esi, 0Fh jz short loc_109 ; yes! mov ebx, [esp+10h+ar1] mov esi, [esp+10h+ar2] loc_ED: ; CODE XREF: f(int,int *,int *,int *)+105 movdqu xmm1, xmmword ptr [ebx+edi*4] movdqu xmm0, xmmword ptr [esi+edi*4] ; ar2+i*4 is not 16-byte aligned, so load it to xmm0 paddd xmm1, xmm0 movdqa xmmword ptr [eax+edi*4], xmm1 add edi, 4 cmp edi, ecx jb short loc_ED jmp short loc_127 ; --------------------------------------------------------------------------- loc_109: ; CODE XREF: f(int,int *,int *,int *)+E3 mov ebx, [esp+10h+ar1] mov esi, [esp+10h+ar2] loc_111: ; CODE XREF: f(int,int *,int *,int *)+125 movdqu xmm0, xmmword ptr [ebx+edi*4] paddd xmm0, xmmword ptr [esi+edi*4] movdqa xmmword ptr [eax+edi*4], xmm0 add edi, 4 cmp edi, ecx jb short loc_111 loc_127: ; CODE XREF: f(int,int *,int *,int *)+107 ; f(int,int *,int *,int *)+164 cmp ecx, edx jnb short loc_15B mov esi, [esp+10h+ar1] mov edi, [esp+10h+ar2] loc_133: ; CODE XREF: f(int,int *,int *,int *)+13F mov ebx, [esi+ecx*4] add ebx, [edi+ecx*4] mov [eax+ecx*4], ebx inc ecx cmp ecx, edx jb short loc_133 jmp short loc_15B ; --------------------------------------------------------------------------- loc_143: ; CODE XREF: f(int,int *,int *,int *)+17 ; f(int,int *,int *,int *)+3A ... 95
mov esi, [esp+10h+ar1] mov edi, [esp+10h+ar2] xor ecx, ecx loc_14D: ; CODE XREF: f(int,int *,int *,int *)+159 mov ebx, [esi+ecx*4] add ebx, [edi+ecx*4] mov [eax+ecx*4], ebx inc ecx cmp ecx, edx jb short loc_14D loc_15B: ; CODE XREF: f(int,int *,int *,int *)+A ; f(int,int *,int *,int *)+129 ... xor eax, eax pop ecx pop ebx pop esi pop edi retn ; --------------------------------------------------------------------------- loc_162: ; CODE XREF: f(int,int *,int *,int *)+8C ; f(int,int *,int *,int *)+9F xor ecx, ecx jmp short loc_127 ?f@@YAHHPAH00@Z endp SSE2-related instructions are: ∙ MOVDQU (Move Unaligned Double Quadword) — it just load 16 bytes from memory into XMM-register. ∙ PADDD (Add Packed Integers) — adding 4 pairs of 32-bit numbers and leaving result in first operand. By the way, no exception raised in case of overflow and no flags will be set, just low 32-bit of result will be stored. If one of PADDD operands — address of value in memory, address should be aligned by 16-byte border. If it’s not aligned, exception will be raised 71 . ∙ MOVDQA (Move Aligned Double Quadword) — the same as MOVDQU, but requires address of value in memory to be aligned by 16-bit border. If it’s not aligned, exception will be raised. MOVDQA works faster than MOVDQU, but requires aforesaid. So, these SSE2-instructions will be executed only in case if there are more 4 pairs to work on plus pointer ar3 is aligned on 16-byte border. More than that, if ar2 is aligned on 16-byte border too, this piece of code will be executed: movdqu xmm0, xmmword ptr [ebx+edi*4] ; ar1+i*4 paddd xmm0, xmmword ptr [esi+edi*4] ; ar2+i*4 movdqa xmmword ptr [eax+edi*4], xmm0 ; ar3+i*4 Otherwise, value from ar2 will be loaded to XMM0 using MOVDQU, it doesn’t require aligned pointer, but may work slower: movdqu xmm1, xmmword ptr [ebx+edi*4] ; ar1+i*4 movdqu xmm0, xmmword ptr [esi+edi*4] ; ar2+i*4 is not 16-byte aligned, so load it to xmm0 paddd xmm1, xmm0 movdqa xmmword ptr [eax+edi*4], xmm1 ; ar3+i*4 71 More about data aligning: Wikipedia: Data structure alignment 96
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Quick introduction to reverse engin
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1.16 C++ classes . . . . . . . . .
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Preface Here (will be) some of my n
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1.1 Hello, world! Let’s start wit
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1.2 Stack Stack — is one of the m
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(_snprintf() function works just li
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1.3 printf() with several arguments
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1.4 scanf() Now let’s use scanf()
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GCC replaced first printf() call to
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}; return 0; printf ("What you ente
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1.5 Passing arguments via stack Now
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1.6 One more word about results ret
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push OFFSET $SG741 ; ’a
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1.8 switch()/case/default 1.8.1 Few
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1.8.2 A lot of cases If switch() st
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loc_804840C: ; DATA XREF: .rodata:0
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et 0 _main ENDP Nothing very specia
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add esp, 1Ch xor eax, eax ; return
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C/C++ standard defines char type as
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eax=eax+ecx return eax ... and this
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mov eax, ecx imul edx sar edx, 1 mo
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; current stack state: ST(0) = resu
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; in local stack here 8 bytes still
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fld QWORD PTR _a$[esp-4] ; current
Page 49 and 50: In other words, fnstsw ax / sahf in
Page 51 and 52: 1.13 Arrays Array is just a set of
Page 53 and 54: mov [esp+70h+var_70], eax call _pri
Page 55 and 56: jge SHORT $LN1@main mov ecx, DWORD
Page 57 and 58: ebp 0x15 0x15 esi 0x0 0 edi 0x0 0 e
Page 59 and 60: 1.14 Bit fields A lot of functions
Page 61 and 62: So, let’s download Linux Kernel 2
Page 63: There are some redundant code prese
Page 66 and 67: y 10 just by dropping last digit (3
Page 68 and 69: _key$ = 8 ; size = 4 _len$ = 12 ; s
Page 70 and 71: 1.15 Structures It can be defined t
Page 72 and 73: call DWORD PTR __imp__GetSystemTime
Page 74 and 75: 1.15.4 Fields packing in structure
Page 76 and 77: }; int b; struct outer_struct { cha
Page 78 and 79: }; printf ("stepping=%d\n", tmp->st
Page 80 and 81: call ___printf_chk mov eax, esi shr
Page 82 and 83: mov edx, DWORD PTR _t$[ebp] or edx,
Page 84 and 85: 1.16 C++ classes I placed a C++ cla
Page 86 and 87: push ecx mov DWORD PTR _this$[ebp],
Page 88 and 89: call _ZN1c4dumpEv lea eax, [esp+20h
Page 90 and 91: 1.17 Unions 1.17.1 Pseudo-random nu
Page 92 and 93: xor eax, eax pop esi mov esp, ebp p
Page 94 and 95: Let’s compile it in MSVC 2010 (I
Page 96 and 97: comp() function: public comp comp p
Page 98 and 99: Some compilers can do vectorization
Page 102 and 103: GCC In all other cases, non-SSE2 co
Page 104 and 105: add ebx, edx lea esi, [esi+0] loc_8
Page 106 and 107: movdqa xmm1, XMMWORD PTR [ecx+16] a
Page 108 and 109: 1.20 x86-64 It’s a 64-bit extensi
Page 110 and 111: } x40 = a3 | x31; x41 = x24 & ~x37;
Page 112 and 113: or ebx, DWORD PTR _x6$[esp+36] mov
Page 114 and 115: and r11, r8 and rsi, r8 and r10, r1
Page 116 and 117: pop rdi pop rsi ret 0 s1 ENDP Nothi
Page 118 and 119: 2.1 LEA instruction LEA (Load Effec
Page 120 and 121: 2.3 npad It’s an assembler macro
Page 122 and 123: 2.4 Signed number representations T
Page 124 and 125: call function function: .. do somet
Page 126 and 127: 3.2 String Debugging messages are o
Page 128 and 129: .text:3011E91B DD 1E fstp qword ptr
Page 130 and 131: loc_80483F2: pop ebp retn _f endp 4
Page 132 and 133: loc_8048444: loc_8048448: loc_80484
Page 134 and 135: public f2 f2 proc near push ebp mov
Page 136 and 137: loc_804840A: loc_804842E: loc_80484
Page 138 and 139: mov esi, DWORD PTR _k$[esp+16] push
Page 140 and 141: or eax, edx retn f endp 4.1.8 Task
Page 142 and 143: 4.2 Middle level 4.2.1 Task 2.1 Wel
Page 144 and 145: mov [edx+eax], bl mov ebx, edi mov
Page 146 and 147: loc_80485AB: ; CODE XREF: f+1E0 ; f
Page 148 and 149: mov [ecx+eax], dl inc eax cmp ebx,
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Chapter 5 Tools ∙ IDA as disassem
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Chapter 7 More examples 147
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.text:00541050 arg_0 = dword ptr 4
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.text:005410F3 .text:005410F3 loc_5
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.text:005411A9 pop ebx .text:005411
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.text:00541249 .text:00541249 next_
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.text:005412FC mov esi, offset cube
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.text:005413DC call _fwrite ; write
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.text:005414A7 push ecx ; Filename
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.text:005413A3 mov ecx, [esp+44h+pa
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.text:00541408 push offset aRb ; "r
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}; }; return; fseek (f, 0, SEEK_END
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.text:005411B5 mov ebp, eax Check f
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.text:0054124C inc ebp .text:005412
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This instruction clears bit, in oth
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.text:005410CD add esp, 40h .text:0
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}; for (i=0; i
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}; tmp[y][z]=get_bit (row, y, z); f
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}; fread (buf, flen, 1, f); fclose
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7.2 SAP client network traffic comp
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.text:64413F68 .text:64413F68 loc_6
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.text:64405171 call dbg .text:64405
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.text:64404FF7 push offset aLogging
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.text:64405113 loc_64405113: .text:
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Now let’s dig deeper and find con
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.text:64411E0B .text:64411E0B loc_6
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Chapter 8 Other things 8.1 Compiler
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Chapter 9 Tasks solutions 9.1 Easy
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9.1.5 Task 1.5 Hint #1: Keep in min
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} 9.1.8 Task 1.8 Solution: two 100*
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#define PUSH(low, high) ((void) ((t
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} } ignore one or both. Otherwise,
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