The Red Brick Wall of Traditional Semiconductor Electronics The ...

“High “High-K”
K” Diele Dielectri Dielectrics: trics cs: Requirements
Dielectric constant between 15 and 40
Chemical Stability against silicon
– No tendency for silicide formation
– No tendency for silicon o xide interfacial layer formation
Compatibility with CMOS Process
– Includes thermal stability
– Selective etching
Important parameter:
– Interface trap density (D it ) impacts carrier mobility
– Sufficiently high K and suitable band offsets to Si impacts
leakage current (for FET and memory)
Epitaxia l?