The Red Brick Wall of Traditional Semiconductor Electronics The ...

The Red Brick Wall of Traditional
Semiconductor Electronics
H. Jörg Osten
Institute for Semiconductor Devices
and Electronic Materials
University of Hannover

150 Years of Electronics
Edison Effect
Lilienfeld
Patents
Diode &Triode
Vacuum Tubes
Point Contact
& Junction Transistors
I.C. MOS Silicon Gate
Scaling, Scaling
Traditional Equivalent
’70 ’80 ’90 ’00 ’10 ’20 ’30 ’40 ’50 ’60 ’70 ’80 ’90 ’00 ’10 ’20
19th Century 20th Century 21st Century

“I think there is a world market for
maybe five computers”
Thomas Watson Senior,
Chairman of IBM, 1943

The Birth of Microelectronics
23.12. 1947:
The first Ge point contact device
showed a current gain of 18
(Bell Laboratories)
Current Transfer + Resistor = Transistor

Silicon Wafer Today

The Intel Family
10 M
1M
A new processor every 2-3 years !
Transistors
100K
10K
4004
1975 1980 1985 1990 1995 2000
Pentium III
8080
8086
80286
80486
80386
Pentium
Pentium II

Electronics, Vol. 38, Nr. 8, April 19, 1965

Moore’s “Law”
The number of transistors per chip
doubles every 18 months

CPU MHz Trend
MHz
1000
100
10
8080
8086
286
Pentium(R)Pro Processor
Pentium(R) Processor
386TM
486TM
1
1970 1980 1990 2000 2010
YEAR
1.25x per year

DRAM Cost Per Function
100000
Price per bit (Millicents)
10000
1000
100
10
1
0,1
'65 '70 '75 '80 '85 '90 '95 2000

Semiconductor End Markets 2003
12%
12%
11%
10% 8%
30%
17%
PC
other Computer
Cell phones
other Commun.
Industrial/Military
Automotive
Consumer
Source: SIA 2003

What is the „ „Best „Best“ est“ “ Technology
Technology?
echnology?
Simplicity
Simplicity
Reliability
Reliability
Needed Needed tools tools
&
investments
Production cost
Production cost
Integration Integration in in
existing existing processes processes
CMOS
III/V III/V-Devices
Devices
Si Si-Bipolar
Bipolar
Si Si-BiCMOS
BiCMOS
SiGe SiGe-Bipolar
Bipolar
SiGe SiGe-BiCMOS
BiCMOS
......... .........
Needed Needed device device
parameter parameter
Power consumption
Power consumption
Maturity
Maturity
Environmental
issues issues

What is the „ „Best“
est“ Technology?
echnology?
The “best technology“ depends on
desired application
As cheap as possible
As established as possible
Performance only sufficiently high

Major Technologies 2003
Global market: $154.9 B
Billion $
13.3
8.3
25.8
25.8
10.3
6.2
34.3
15.7
9.7
5.5
Products
Discrete
Optoelectronics
Analog
MOS µ-processors
MOS µ-controllers
MOS DSP
MOS Logic
MOS DRAM
Flash EEPROMS
others
4%
6.6%
17%
more than 90 % is based on Si
more than 80 % is integrated
17%
22%
10%
5.4% 8.6%
6.3%
3.6%
Source: SIA 2003

It is revolutionary time ...
Processor: 30% more components per year,
doubling in speed every 1.5 years
Memory: 60% more capacity every year
Harddisk: 60% more capacity every year
Cost per function: 25% lower every year

Moore‘s Law Law:
: New Structures
1960‘s: Bipolar, Mesa, Metal gate
1970‘s: MOS, Poly-gate, LOCOS isolation
1980‘s: CMOS, W plugs, salicide process
1990‘s: STI isolation, BiCMOS, CMP,
multilevel metal, SiGe bipolar
2000‘s: Hetero MOS (strained silicon), …

Moore‘s Law Law:
: New Materials
1960‘s: Si, Al, SiO 2
1970‘s: Poly-Si, PSG, Al-Si, Si 3 N 4
1980‘s: BPSG, WSi 2 , Polyimide, SOG, TiN, TiN
1990‘s: Al-Cu, W, MoSi 2 , SiOF, Cu, SiGe,
TiSi 2 , CoSi 2 , Low-K ILD
2000‘s: High-K dielectrics, …?

CMOS Technology Breakthrough Takes Time…
Tool or Technology
Silicon epitaxy
APCVD silicon nitride
Ion implantation
TiW metallization
Charge-coupled devices (CCD)
Reactive ion etch (RIE)
Poly-Si emitter
Refractory gate
SIMOX (SOI via implantation)
Trench capacitors
Silicide (self-aligned)
Lightly-doped drain (LDD)
developed
1960
1965
1969
1970
1970
1975
1976
1976
1978
1979
1978
1980
In production
1964
1968
1973
1976
1981
1980
1984
1983
1989
1986
1985
1986
∆
4
4
4
6
11
5
8
7
11
7
7
6

Moore’s Law today today:
: New Capabilities
Resist, optics, mask (157nm, EUV, …)
Chemical-mechanical polishing
Deposition of high-K dielectrics
Low-K dielectrics (organics) integration
Thinner conformal barrier metals
Higher thermal conductivity materials
Atomic layer conformal deposition

Example: Hetero Heterojunction
junction Bipolar
ipolar Transistor (HBT)
Poly SiGe:C/Si
STI
W
SiGe:C
W
Emitter
window
Active region
As doped
emitter
XTEM image of a SiGe:C HBTs
Thin, heteroepitaxial
base layer
IHP 2001

HBT: Bor Boron
on Outdiffusion – the Key Problem
n-emitter (Si) p-base (SiGe) n-collector (Si)
Boron doping

HBT: Bor Boron
on Outdiffusion – the Key Problem
n-emitter (Si) p-base (SiGe) n-collector (Si)
Boron doping

Boron Outdiffusion: The Problem
Conduction band for heavily p-doped Si and SiGe (schematically)
npn-Si
npn-Si/SiGe/Si
Parasitic barriers

Material Solution:
Suppression of Boron Outdiffusion by Carbon
SiGe
B concentration
BORON
Annealing
Depth (nm) Depth (nm)
SIMS investigations on real devices
SiGe:C
B concentration

SUMMARY: Dopant Diffusion in Si SiGe SiGe:C Ge:C :C
Model of C outdiffusion provides quantitative
description
– Coupled diffusion of C and Si point defects
Suppressed B diffusion due to C incorporation
– Interstitial undersaturation due to C outdiffusion
– diffusivity reduction of ~20 for < 10 20 cm -3 C
C suppresses also transient enhanced diffusion (TED)
during damage annealing
Boron and phosphorous diffusion is suppressed by C
– Interstitial-mediated dopant diffusion
Antimony and arsenic diffusion is enhanced by C
– Vacancy-mediated dopant diffusion

SiGe:C Heterojunction Bipolar Transistor
f T or f max (GHz)
75
70
65
60
55
50
45
40
35
30
- First realization with MBE 1997 -
10 -3
f max
V CE = 2 V
Emitter Area 0.5 x 5 µm²
R SBi = 2.3 kΩ
f T
Collector Current (A)
10 -2
Ring Oscillator Delay
CML-type, FI/FO = 1
25 HBTs, 0.9 x1.3 µm²
td ± σ =
(12.9 ± 0.2) ps
best value: 12.6 ps
Osten et al. IEDM 97
Meanwhile both frequencies are above 200 GHz
Si-based analog circuits for mobile communication

Modular Integration: BiCMOS ffor
for or Everybody
“bipolar step
proce ss step
“corrected”
CMOS
CMOS
classical
BiCMOS
bipolar
modul
modular
odular
BiCMOS

Modular Integration of SiGe:C HBTs in into
to CMOS
CMOS
digital
+
HBT
=
BiCMOS
• IHP module can be integrated into nearly any CMOS process
• No changes in CMOS flow (modular integration)
• CMOS libraries can be re-used
• Adds only 4 additional masks to the process
• Requires only epi-SiGe:C CVD as a new step

Prognosis ….
“There is no reason anyone
would want a computer in
their home”
Ken Olsen
President, Chairman and
founder of Digital, 1977

The Coming Years
Consult the
oracle
ITRS Roadmap

The ITRS Consortium
onsortium
TWG Members by Regions TWG Members by Affiliations
Japan
222
26%
19%
Taiwan
161
Korea
64
8%
USA
324
39%
8%
Europe
68
Source: 2001 ITRS - Exec. Summary
Research Inst. /
Consortia / Other
University 1% 10
193 23%
22%
Equipment /
Materials
Suppliers 185
Chip Makers
445
54%

The Plan for Globalization - ITRS Working Groups
International
Technology
Working Groups
(ITWG)
Design
Test
Front End Processes
Interconnect
Lithography
Process Integration
Assembly & Packaging
Factory Integration
International Crosscut Technology
Working Group (ICCT WG)
Environment
Safety &
Health
Metrology Defect
Reduction
Modeling &
Simulation
http://public.itrs.net

The latest ITRS Roadmap ( (selected selected example example)
Year of Production:
DRAM Half-Pitch [nm]:
Overlay Accuracy [nm]:
MPU Gate Length [nm]:
CD Control [nm]:
T OX (equivalent) [nm]:
Junction Depth [nm]:
Metal Cladding [nm]:
Inter-Metal Dielectric K:
2001
130
46
90
8
1.3-1.6
48-95
16
3.0-3.6
2003
100
35
65
5.5
1.1-1.8
33-66
12
3.0-3.6
2005
80
28
45
3.9
0.8-1.3
24-47
9
2.6-3.1
2007
65
23
35
3.1
0.6-1.1
18-37
7
2.3-2.7
2010
45
18
25
2.2
0.5-0.8
13-26
5
2.1
2016
22
9
13
1.1
0.4-0.5
7-13
Solution known R&D needed Solution unknown
2.5
1.8

The Red Brick Wall of Microelectronics
Year of Production:
DRAM Half-Pitch [nm]:
Overlay Accuracy [nm]:
MPU Gate Length [nm]:
CD Control [nm]:
T OX (equivalent) [nm]:
Junction Depth [nm]:
Metal Cladding [nm]:
Inter-Metal Dielectric K:
2001
130
46
90
8
1.3-1.6
48-95
16
3.0-3.6
2003
100
35
65
5.5
1.1-1.8
33-66
12
3.0-3.6
2005
2.6-3.1
2007
0.6-1.1
18-37
2.3-2.7
Solution known R&D needed Solution unknown
80
28
45
3.9
0.8-1.3
24-47
9
65
23
35
3.1
7
2010
45
18
25
2.2
0.5-0.8
13-26
5
2.1
2016
22
9
13
1.1
0.4-0.5
7-13
2.5
1.8

Ultrathin Gate oxide oxide: : 30 nm Transistor
30 nm FET (Intel)

Need for Alternative Gate Dielectrics
Production
year
Technology
Node
(nm)
Gate dielectric
(SiO2 equivalent)
thickness
(Å)
Gate bias, Vdd
(V)
Leakage current
for SiO2 @ Vdd
(for max. EOT)
(A/cm²)
2001 130 13 - 16 1.1 > 0.1
2002 115 12 - 16 1.0 > 0.1
2003 100 11 - 16 1.0 > 0.1
2004 90 9 - 14 1.0 > 1
2005 80 8 - 13 0.9 > 2
2006 70 7 - 12 0.9 > 5
2007 65 6 -11 0.7 > 10
2010 45 5 - 8 0.6 > 100
2013 32 4 - 6 0.5
2016 22 4 - 5 0.4

Alternatives
Needed: thicker gate dielectric
BUT: The capacity cannot be changed!
C ~ K A / t
Solution: Materials with higher dielectric constant (High-K)
For a given capacitance, the possible layer thickne ss scale s with K
Capacitance scales linearly with thickness
Equivalent Oxide Thickne ss: EOT = t * 3.9/K

“High “High-K”
K” Diele Dielectri Dielectrics: trics cs: Requirements
Dielectric constant between 15 and 40
Chemical Stability against silicon
– No tendency for silicide formation
– No tendency for silicon o xide interfacial layer formation
Compatibility with CMOS Process
– Includes thermal stability
– Selective etching
Important parameter:
– Interface trap density (D it ) impacts carrier mobility
– Sufficiently high K and suitable band offsets to Si impacts
leakage current (for FET and memory)
Epitaxia l?

Search for Suitable Binary Oxides
H not solid at 1000K He
Li Be radioactive B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba * Lu Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra ** Lr Rf Db Sg Bh Hs Mt
* Lanthanoids La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb
** Actinoids Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No

Search for Suitable Binary Oxides
Si + MOx M+SiO2 ; MSiz + SiO2 ; M + MSixOy
H not solid at 1000K He
Li Be radioactive B C N O F Ne
Na Mg Also not suitable Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba * Lu Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra ** Lr Rf Db Sg Bh Hs Mt
* Lanthanoids La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb
** Actinoids Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No

Praseodym
Praseodymium
ium Oxid Oxide: xide: : Leakage Current
J g (A/cm -2 )
10 2
10 0
10 -2
10 -4
10 -6
10 -8
10 -10
10 -12
16 Au/Pr 2O 3/n-Si capacitors
1.9 x 10 -3 cm², EOT = 1.4 nm.
-2 0 2 4 6 8
V g (V)
Leakage current density for different
dielectrics with EOT = 1.4 nm.
Material Jg (A/cm ²)
@ Vg = 1V
Pr2O3
HfO2
ZrO2
SiO2
7*10 -9
1*10 -4
5*10 -4
~ 1
SiO2 (3 nm ) ~ 10 -4
Osten et al. IEDM 2000
Lowest reported values for leakage current

Pr 2O 2O3 Growth 3 Growth on Si(111)
5 nm
epi Si
h-Pr 2 O 3
(111) Si
X-HREM of a 6 nm
thick, hexagonal Pr 2 O 3
film grown epitaxially
on a Si(111) substrate.
Si overgrowth leads to the formation of epitaxial,
(111) oriented silicon.
Novel tunneling devices?

Epita Epitaxial
xial Growth of Heterolayers

Pseudomorphic Growth (Strained Layer)
compressive
strained SiGe
(pseudomorphic)
Si substrate

Relaxed Layer ( (Misfit Misfit Dislocations)
relaxed SiGe
mf dislocation
Si substrate

Virtual Substrate (Strained Strained Si Layer Layer)
tensile
strained Si
Relaxed
SiGe
Si Substrate

Band Gap for Strained SiGe and silicon
Band Gap (eV)
at 90 K
1.2
1.1
1.0
0.9
0.8
Strained SiGe
on Si
Relaxed SiGe
Strained Si
on relaxed SiGe
0.7
0.0 0.2 0.4 0.6 0.8 1.0
Ge Concentration
Strain reduces the band gap

SiGe Valley Splitting: Conduction Band
Strained SiGe on Si
[001]
[100]
[010]
[001]
Unstrained Si
6-fold
degenerated
[010]
[100]
Strained Si on
relaxed SiGe
[001]
Intervalley scattering can be reduced
Increase in carrier mobility
[010]
[100]

Strain and Carrier Mobility
Normalized Mobility
2,5
2,0
1,5
NMOS
PMOS
1,0
0 10 20 30 40
Ge Concentration (%)
of the Substrate
Strained Si on relaxed SiGe

State State-of State-of-the-Art
of-the the-Art Art
CMOS with
• 50 nm Gate length
• Strained Silicon
• 1.2 nm SiO 2
• Nickel silicide
1.2 nm
1.2nm
SiO 2
silicide
Strained Si
INTEL: IEDM Dez. 2002

Scaling will go on

Moore’s “ “Law “Law” Law”
The number of transistors per chip
doubles every 18 months
Execution to Moore’s Law is
becoming more material dependent
Further scaling will reach
physical limits

Material Complexity is Compounding
Number of New Fab Materials
Compared to the 0.35 micron Baseline
50
45
40
35
30
25
20
15
10
5
0
0.25 micron
0.18 micron
0.13 micron
0.13 micron
(300 mm)
Revolutionary:
Characterized by or
resulting in radical change.
Evolutionary:
A gradual process in which
something changes into a
different and usually more
complex or better form.
Source: INTEL

Evolutionary Changes
CMP: Composite abrasive slurries
SILICON: Double-Sided Polished
PHOTORESIST: 193 nm
DIELECTRICS: Fluorine- & Carbon-Doped SiO 2
METALS
– Ta Barrier
– Salicides
– Target Assembly

Revolutionary Changes
LOW K DIELECTRICS
– Spin-on polymers
– Porous materials
HIGH K GATE DIELECTRICS
– Metal ox ides
– Mixed silicates
METALS
– Dual Damascene Copper
– Advanced Bump Metallurgy instead of bonding
– Atomic Layer Deposition

Revolutionary Changes
CHEMICAL-MECHANICAL POLISHING (CMP)
– Fixed & bonded abrasive pads
– Abrasive-free slurries
SILICON
– Isotopically-enriched Si (28)
– Si on Insulator (FD or PD-SOI)
PHOTORESIST
– 157 nm
– EUV
CARRIER: FOUP

Power Density Continues to Get Worse
Watt/cm 2
1000
100
10
1
1985
P446
P648
1990
P650
P852
1995
P854
P856
2000
P858
P860
2005
P1262
P1264
2010

Future Drivers
Logic process technologies are driven by
3 key technology areas:
Transistor performance
– Gate oxide quality, channel mobility, …
– Leakage currents
Patterning / etching of nanometer lines
Low RC interconnects

Lithography: Yesterday, Today, and Tomorrow

Bridging the SubWavelength Gap

CPU Multi Multi-layer layer Metal Increase Trend
# of Metal Layers
8
7
6
5
4
3
2
1
0
1980-2µ
1984-1.5µ
1987-1.0µ
1990-0.8µ
1993-0.6µ
1995-0.35µ
1997-0.25µ
1999-0.18µ
2001-0.13µ
2003-0.09µ

0.5µm
P-WELL P-W WELL ELL
N-WEL WEL L
P+ Substrate
Epi
P-WELL P-W WELL ELL
N-WEL WEL L
Epi

RC Delay
Assumption
Assumption: : two parallel
interconnects will be
treated as a capacitor
C = LW K ox ε 0 /t ox
R = ρ met L/W t met
t met
RC ~ ρ met K ox L²/t ox t met
Only a problem for long interconnects
interconnects!
t ox

RC Delay
Strategies
Strategies:
RC ~ ρ met K ox L²/t ox t met
- lowest possible resistivity
- thick interlayer dielectric
- thick metal layer
Limited by global design issues
Interlayer Interlayer with low K ox
(low low-K K dielectrics
dielectrics, , e.a. polymers
polymers)

Groups of Low Low-K Materials
Reducing dielectric constant k
Decreasing polarity
1
Decreasing density
Groups of materials Bulk dielectric constant Deposition
SiO 2 3.9 - 4.3 K CVD
Fluorinated oxide1 3.4 - 3.9 low-K CVD
Organosilicate glass1,2 2.5 - 3.0 low-K CVD
Organic polymer 1 2.5 - 3.0 low-K CVD/SOD
Porous organic polymer 1,2 2.0 - 2.5 ultra low-K SOD
Porous organic polymer 1,2 1.5 - 1.9 extreme low-K SOD
2

Calculated Delay vs. Technology Generation
Delay (ps)
45
40
35
30
25
20
15
10
5
0
Gate Delay
Cu + low-K
Al + SiO 2
Total (Cu + low-K)
Total (Al + SiO )
2 600 500 400 300 200 100
Pitch Size (nm)
Al: 3.0 µΩcm
Cu: 1.7 µΩcm
SiO2: κ = 3.9
Low K: κ = 2.0
Al & Cu: 0.8 µm thick
50 µm long
Interconnect optimized circuit design will be needed

Cost of a Chip Factory
“Second Moore’s Law”
Fab cost doubles every 3 years

Worldwide Semiconductor Sales
1975 1975-2005
2005
$Billions
250
200
150
100
50
0
1975
1977
1979
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003*
2005*
Source: SIA Fall 2002 Forecast
* Forecast

$35
$30
$25
$20
$15
$10
$5
$0
Intel
Toshiba
NEC
Samsung
TI
Top 22 Chip Manufacturers 2000
STMicro
Final 2000 numbers
from Dataquest*
Motorola
Hitachi
Infineon
Micron
Hyundai
Philips
Mitsubishi
Fujitsu
TSMC*
Lucent
AMD
IBM
'98 ($B)
'99 ($B)
'00 ($B)
Source: Dataquest, *TSMC and UMC annual reports — the latter don't sell chips into the market
Matsushita
Sony
Sharp
UMC*

The Need for Globalization
manufacturer
manufacturer
90’s 21 st Century
Technology
Economics
Global
Semiconductor
Industry

Mega Business Trends
Cost of Fab, instead of technology
breakthrough, impacts global industry food
chain
– size matter; CPU, DRAM alliance
– Foundry fab (TSMC and others)
Migration to Developing Country will
accelerate
– Foundry to Asia (Taiwan, China…)
– Fabless design to Taiwan, Israel, Russia, India…

Asia Pacific Leads
$Billions
90
80
70
60
50
40
30
20
10
0
Regional Semiconductor Market
2001 2002* 2003* 2004* 2005*
Americas Europe Japan Asia Pacific
Source: SIA Fall 2002 Forecast
*2002 Grow th Rates

Growth of the Internet
Mill.
10000
1000
100
World population
TV & Telephone
PC
“Internetter Internetter”
10
‘95 ‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02 ‘03 ‘04

Wireless Internet
Wireless (of course!)
– But much more than wireless access to the net
Personal
– Accessed by personalized, handheld terminals
– “Wearable computers”
Location aware
– Information & services you need where you happen to be
Context aware
– You need a ticket at the train station
Transaction based

Web Tablet

Nanoelectronics

Other New Concepts (here: Memories)

Visions
Integration of Opto and Microelectronics on one Chip

New Device Concepts
Gate Oxide
Body
Drain
Silicon Film
Buried Oxide
Substrate
Poly Gate
Source
Body
BOX
Source Drain
Source
Gate
Drain
Si fin - Body!

V S
Beyond the classical FET
1) MOSFET
V S
V G
2) SBFET
V G
V D
V D
3) CNTFET
4) Molecular transistors?
V G
V S
V D

Scaling will reach physical limits….
10 nm MOSFET Molecule
or
?

Carbon Nanotubes

Summary
Innovations on all levels are needed for future progress
– Materials (high-K, low-K, new metals, SOI,…)
– Device concepts (3D integration, …)
– IC architectures (interconnect optimized design, …)
The „classica l“ microelectronic (CMOS, …) is getting
closer to its limits
– Material limits
– Technical limits
– Economical limits (too expensive)
Nanoelectronics
– Devices with small number of electrons
– Molecular approaches
– Fabrication by self organization
– Various quantum effects (spintronic, quantum computing)