Xilinx XAPP551 Viterbi Decoder Block Decoding - Trellis ...

Implementation
X-Ref Target - Figure 18
BER
10 -1
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
BER vs Eb/No
3 4 5 6 7 8
Eb/No (dB)
9 10 11 12 13
Figure 18: Effect of Incorrect Trellis Construction in Tail Biting
Packet Contains Less Than One Traceback Length
CL3 Continuous
CL3 3 Blocks
CL3 2 Blocks
X551_13_120304
In this case the packet of data is less than the traceback length. Thus, the decoder does not
have enough data to construct the trellis, start at the correct point in the trellis, and perform the
correct training. Therefore, copies of the packet data are repeated before and after the actual
packet block. The repeated packet data is traceback length to allow construction and training of
the data.
In the example shown in Figure 19, the packet length is 27 bits and the traceback length is
42 bits. Because tail biting is being performed, the last Z bits of the packet are used to initialize
the decoder. A traceback-length block of data is the first input to the Viterbi decoder from the
circular buffer. The block consists of the last 15 bits of the packet followed by the 27 packet bits.
The 27-bit block being decoded is then input, indicated by assertion of the BLOCK_IN signal,
followed by another 27-bit block and the first 15 bits of the next block, which is used for
traceback training. The Viterbi decoder outputs the 27-bit packet indicated by the RDY signal and
the BLOCK_OUT signal.
XAPP551 (v2.0) July 30, 2010 www.xilinx.com 16