Xilinx XAPP551 Viterbi Decoder Block Decoding - Trellis ...

More documents

Recommendations

Info

Viterbi Block Decoding This method has these disadvantages: Extra bits have to be transmitted, reducing the code rate. If there are N bits in the packet, (N + Z)/R bits are transmitted, where Z is the number of zeros set by the constraint length - 1 and R is the encoder code rate. The extra bits consume additional transmission time and slightly reduce the energy-per-bit to noise-power-spectral-density ratio (Eb/No) for a given probability of error. Typically, the overall effect is insignificant except when N is very small. X-Ref Target - Figure 3 DATA_IN d 0 DATA_IN Tail Biting Input packet first bit d 0 d 1 d 2 Encoder state during transmission of first output symbol + DATA_OUT_V(1) Figure 3: Convolution Encoding for Trellis Zero Termination Tail biting attempts to overcome the problem of transmitting extra termination bits experienced by trellis termination. The tail biting technique has these advantages: The code rate is not affected. N/R bits are transmitted. The error correction properties of the convolution code are not affected. The disadvantages are: Because training is required to determine the correct start state and initial traceback state, decoding latency is increased over trellis termination. Receiver complexity is slightly increased. Tail biting can be done by: 1. Using the last Z data bits of the packet to initialize the encoder shift register prior to transmission of the packet (number of bits Z = constraint length - 1). No output symbols are transmitted during encoder initialization. This means that the encoder start state and end state for the packet are identical. It also implies that the entire packet must be available at XAPP551 (v2.0) July 30, 2010 www.xilinx.com 4 + + + d N–1 0 0 DATA_OUT_V(0) 0 0 0 0 0 0 DATA_OUT_V(1) DATA_OUT_V(0) 0 0 0 0 0 0 0 0 Input packet last bit Shift N+6 input bits into encoder and transmit a total of N+6 output symbols 0 0 Input packet (N+6 bits) Encoder state after transmission of last output symbol X551_02_011405
Implementation the encoder before the first symbol is transmitted. Figure 4 illustrates this method for an example with constraint length 7. The encoder is initialized to the last six bits of the packet, and the first symbol is formed when DATA_IN = d0. The last symbol of the packet is formed when dN-1 is on DATA_IN. One more shift puts the encoder back into the initial state. The decoder can then begin traceback of the packet from that state. 2. Initializing the encoder with the first Z data bits of the packet—again not transmitting any output symbols during this time. The remaining (N - Z) data bits are then encoded and transmitted, followed by the first Z bits. This has the same effect of causing the start and end states to be identical. The advantage of this method is that it does not require the entire packet before encoding starts. However, the bits are out of sequence at the receiver. X-Ref Target - Figure 4 DATA_IN d0 DATA_IN Input packet first bit Figure 4: Convolution Encoding for Tail Biting Termination Implementation All termination methods presented can be implemented with the Convolutional Encoder [Ref 1] and Viterbi decoder [Ref 2]. Trellis Truncation Encoding Input packet last bit d 0 d 1 d 2 d N–7 d N–6 d N–5 d N–4 d N–3 d N–2 d N–1 Input packet (N bits) Encoder state during transmission of first output symbol Convolutional encoding can be implemented using the Convolutional Encoder (version 6.2 or later). However, because the encoder is relatively simple, another option is to write RTL code for the encoder. In the example shown in Figure 5, a 270-bit packet is input into the convolutional encoder, resulting in 270 symbols. Each symbol is 2 bits for a 1/2 code rate. XAPP551 (v2.0) July 30, 2010 www.xilinx.com 5 + + + DATA_OUT_V(0) d N-1 d N-2 d N-3 d N-4 d N-5 d N-6 + DATA_OUT_V(1) Shift N input bits into encoder and transmit a total of N output symbols DATA_OUT_V(0) d N-1 d N-2 d N-3 d N-4 d N-5 d N-6 DATA_OUT_V(1) Encoder state after transmission of last output symbol X551_20_111109
Page 1 and 2: XAPP551 (v2.0) July 30, 2010 Summar
Page 3: Viterbi Block Decoding X-Ref Target
Page 7 and 8: Implementation X-Ref Target - Figur
Page 9 and 10: Implementation block is not an issu
Page 11 and 12: Implementation X-Ref Target - Figur
Page 13 and 14: Implementation Packet Contains Mult
Page 15 and 16: Implementation This technique relie
Page 17 and 18: Recommendations Refer to Tail Bitin
Page 19 and 20: Reference Designs Table 2: Descript
Page 21: Revision History Revision History N

Xilinx XAPP551 Viterbi Decoder Block Decoding - Trellis ...

Create successful ePaper yourself

Delete template?

Save as template?