VLSI - YMCA University of Science & Technology

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Elective II VLSI Testing and Design for Testability Physical defects and their modeling; stuck at faults; Bridging Faults; Fault collapsing. Fault Simulation: Deductive, Parallel and Concurrent; Critical Path Tracing. Test Generation for Combinational Circuits: D-Algorithm, Boolean Difference, PODEM, and ATPG. Random, Exhaustive and Weighted Random Test Pattern Generations Aliasing and its effect on Fault coverage. PLA Testing: cross-point Fault Model, Test Generation, Memory testing: Permanent Intermittent and Pattern Sensitive Faults; Delay Faults and Hazards; Test Generation Techniques; Test Generation for Sequential Circuits. Scan Design. Scan path and LSSD, BILBO Concept of Redundancy, spatial redundancy, Time redundancy Recent trends in VLSI testing: Genetic Algorithms, Parallel Algorithms, Neural networks, nano scale testing Text books: 1. VLSI Testing: digital and mixed analogue digital techniques Stanley L. Hurst Pub:Inspec/IEE ,1999
Low Power VLSI Design Low power Basics Need for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits. Emerging Low power approaches. Physics of power dissipation in CMOS devices. Device & Technology Impact on Low Power Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device innovation. Power estimation Simulation Power analysis: SPICE circuit simulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems. . Low Power Design Circuit level: Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes, low power digital cells library Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-computation logic Low power Architecture & Systems: Power & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design. Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip & package co design of clock network Algorithm & architectural level methodologies: Introduction, design flow, Algorithmic level analysis & optimization, Architectural level estimation & synthesis. Text: 1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002 2. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997 References: 1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000
Page 1 and 2: Syllabus & Scheme for M.Tech. (VLSI
Page 3 and 4: Second Semester Subject Code Title
Page 5 and 6: Elective - I Sr. No. Subject Code T
Page 7 and 8: Digital VLSI Design (E603V) UNIT I
Page 9 and 10: Embedded System-I MICROCONTROLLER 8
Page 11 and 12: IC Fabrication Technology Environme
Page 13 and 14: Embedded System Design-II THE PIC M
Page 15 and 16: Nanotechnology Unit - I Atomic stru
Page 17 and 18: Embedded Control System INTRODUCTIO
Page 19: CAD System Environment Familiarity
Page 23: Algorithms for VLSI Design Automati

VLSI - YMCA University of Science & Technology

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