ARM Software reference manual

Instruction se!
MOV
causes the operand to be placed unchanged in the destination register,
for example,
MOV R0,R1,LSL#2
MVN causes the operand to be evaluated and its bitwise inverse to be placed
in the destination register. The contents of register 1 are shifted left by 2
bits and transferred to register 0, for example,
MVN R2,R3
Register ORR 2 is set to the bitwise inverse of the contents of register 3.
performs a bitwise OR on operand] and operand2. The result is stored
in the destination register.
RSB subtracts operand] from operand2. The result is stored in the
destination register.
RSC subtracts operandi from operand2 if the carry flag is set. If the carry
flag is clear, operand2—operand1-1 is calculated. The result is stored in the
destination register.
sac subtracts operand2 from operandi if the carry flag is set. If the carry
flag is clear, operandl—operand2-1 is calculated. The result is stored in the
destination register. This instruction can be used to implement multi-word
subtractions.
sus subtracts operand2 from operand]. The result is stored in the
destination register, for example:
SUBS R4,R2,R0 ;Do least significant word
;of subtraction
SBC R5,R3,R1 ;Do most significant word,
;taking account of the borrow
;This does the 64 bit subtraction
;(R5,R4)-(R3,R2)-(R1,R0)
The result is stored in the destination register.
TEQ performs a bitwise exclusive OR between operand] and operand2.
TST performs a bitwise AND operation between operand] and operand2.
In the case of TEQ and TST the N and V flags are altered according to the
result, V is unchanged and C is set to the last bit shifted out by the barrel
shifter, or is unchanged if no shifting took place.
ARM software 11