EGR 680 S'11 Assignment #8 - Claymore

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EGR680 S’11 4 8. Under Debugger window, select Run -> Connect to Target. Accept the default settings and click OK. Then select Run -> Run to start the debugger. Your software will be downloaded and processor will be suspended automatically (breakpoint) at the first statement in the main. Keep your Hyper Terminal window and Debugger window in such a way that you can see both of them simultaneously. 9. Now select Control -> Continue so that your application runs and halts at another breakpoint. You should see some message displayed in your Hyper Terminal based on your placement of breakpoint. You can keep pressing ‘C’ and your application will run and stop at the next breakpoint. 10. You might want to keep track of the variables that you have declared in your software while running your program. For that, go to View -> Local Variables and you should see Local Variables window as shown in Figure 5. Figure 5: Local Variables window 11. You can change the dip-switch settings and then press ‘C’ or you can press ‘C’ while keeping the pushbutton pressed and you will see the new value highlighted in green. 12. You can also look at the memory map by clicking on View -> Memory and it displays a Memory window as shown in Figure 6. You can type in the address of the memory in Address field and hit Enter. Figure 6: Memory Window Copyright 2011 GVSU School of Engineering
EGR680 S’11 5 13. You need to type in the memory location pertaining to your Dip-switch and Push button GPIO and then run your program. You should see the change in the value at that memory location. 14. You can click on Run -> Disconnect to terminate the debugging session and close the tools. Part II – Writing Test Benches in Verilog (using Tasks) Based on the material (on Tasks and Functions) distributed/discussed in lecture, lets see how a test bench can be written using Tasks. 1. Download “memory_trans.v” and “memory_test.v” from the course website. Create a project in Xilinx ISE and add both the verilog files into your project. NOTE: memory_test.v is created by selecting New Source and then selecting Verilog Test Fixture. 2. The design involves a 2K memory (8-bit data and 8-bit address bus). The test bench uses two tasks (one to write the data to memory and other to read the contents of memory). You will run the simulation and verify if you actually read the correct data from the memory. 3. If you don’t read the correct data then you need to identify the problems and make appropriate changes to the test bench. Conclusion Software debugging was performed using Xilinx’s built-in software debugger. Test bench was written in Verilog using tasks and the functionality of the sample design was verified using Xilinx simulator. Laboratory Deliverables • None Copyright 2011 GVSU School of Engineering
Page 1 and 2: EGR680 S’11 1 Objectives Due Date
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EGR 680 S'11 Assignment #8 - Claymore

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