EGR 680 S'11 Assignment #8 - Claymore

EGR680 S’11 1
Objectives
Due Date: None
Software Debugging and Writing Test benches
• To guide you through the process of software debugging
• To learn writing test benches in Verilog
Part I – Software Debugging
Copyright 2011 GVSU School of Engineering
EGR 680 S’11
Assignment #8
1. Copy your Lab6 project into C:\lab8 directory. Open XPS and browse to the folder
containing your project. Click system.xmp to open the project.
2. Start a terminal session
• Baud rate: 115200
• Data bits: 8
• Parity: none
• Stop bits: 1
• Flow control: none
3. Connect and power up the board. Download the bitstream by selecting Device Configuration
Download Bitstream
Note: Once the bitstream is downloaded, you should see the DONE LED ON and Dip- Switch
and Push Button status displayed on terminal window.
4. Now, your hardware is programmed and functioning. Since you want to debug your
software, you will be running your software using debugger. Go to Debug -> Launch XMD
to open an XMD session. If this is your first time running the XMD tool you will see a XMD
Debug Options window (Figure 1). The selection should be similar to Figure 1 and then click
OK.
Note: Your application should be running when you perform step #4 (mentioned above)

EGR680 S’11 2
Figure 1: Setting up XMD Debug options
5. Either you will see a DOS window as shown in Figure 2 or you might have to click on Debug
-> Launch XMD t o see a DOS window. This will halt the running process (your
program). Make sure that your Power PC (ppc) target is connected to XMD at port 1234 and
power is applied to the board.
Figure 2: XMD connected to Power PC at port 1234
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EGR680 S’11 3
6. Select Debug -> Launch Software Debugger to open another window (Debugger) as
shown in Figure 3. Select TestApp_Peripheral as the software application then click OK.
Figure 3: Software Debugger
7. You will set the breakpoint by clicking on the line (left side) and the breakpoint should be set
(indicated by red dot) as shown in Figure 4.
Figure 4: Setting Breakpoint
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EGR680 S’11 4
8. Under Debugger window, select Run -> Connect to Target. Accept the default settings
and click OK. Then select Run -> Run to start the debugger. Your software will be
downloaded and processor will be suspended automatically (breakpoint) at the first statement
in the main. Keep your Hyper Terminal window and Debugger window in such a way
that you can see both of them simultaneously.
9. Now select Control -> Continue so that your application runs and halts at another
breakpoint. You should see some message displayed in your Hyper Terminal based on your
placement of breakpoint. You can keep pressing ‘C’ and your application will run and stop at
the next breakpoint.
10. You might want to keep track of the variables that you have declared in your software
while running your program. For that, go to View -> Local Variables and you should see
Local Variables window as shown in Figure 5.
Figure 5: Local Variables window
11. You can change the dip-switch settings and then press ‘C’ or you can press ‘C’ while
keeping the pushbutton pressed and you will see the new value highlighted in green.
12. You can also look at the memory map by clicking on View -> Memory and it displays a
Memory window as shown in Figure 6. You can type in the address of the memory in
Address field and hit Enter.
Figure 6: Memory Window
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13. You need to type in the memory location pertaining to your Dip-switch and Push button GPIO
and then run your program. You should see the change in the value at that memory location.
14. You can click on Run -> Disconnect to terminate the debugging session and close the tools.
Part II – Writing Test Benches in Verilog (using Tasks)
Based on the material (on Tasks and Functions) distributed/discussed in lecture, lets see how a
test bench can be written using Tasks.
1. Download “memory_trans.v” and “memory_test.v” from the course website. Create a
project in Xilinx ISE and add both the verilog files into your project.
NOTE: memory_test.v is created by selecting New Source and then selecting Verilog Test
Fixture.
2. The design involves a 2K memory (8-bit data and 8-bit address bus). The test bench uses two
tasks (one to write the data to memory and other to read the contents of memory). You will
run the simulation and verify if you actually read the correct data from the memory.
3. If you don’t read the correct data then you need to identify the problems and make
appropriate changes to the test bench.
Conclusion
Software debugging was performed using Xilinx’s built-in software debugger. Test bench was
written in Verilog using tasks and the functionality of the sample design was verified using
Xilinx simulator.
Laboratory Deliverables
• None
Copyright 2011 GVSU School of Engineering