Chapter 07 Display Subsystem.pdf

Public Version 

This chapter describes the Display Subsystem for the device. 

Chapter 7 

SPRUGN4L–May 2010–Revised June 2011 

Display Subsystem 

NOTE: This chapter contains information that is ©2005-2008 MIPI Alliance, Inc. All rights reserved. 

MIPI Alliance Member Confidential. 

All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No 

part(s) of this document may be disclosed, reproduced or used for any purpose other than as 

needed to support the use of the products of TI. 

See Device 37xx MIPI Disclaimer for details. 

NOTE: This chapter gives information about all modules and features in the high-tier device. To 

check availability of modules and features, see Section 1.5, AM/DM37x Family and your 

device-specific data manual. In unavailable modules and features, the memory area is 

reserved, read is undefined, and write can lead to unpredictable behavior. 

NOTE: This document is strictly for wireless/cellular software developers using AM/DM37x 

application processors, which are not available for the broad market through authorized 

distributors. 

Topic ........................................................................................................................... Page 

7.1 Display Subsystem Overview .......................................................................... 1542 

7.2 Display Subsystem Environment ..................................................................... 1547 

7.3 Display Subsystem Integration ........................................................................ 1599 

7.4 Display Subsystem Functional Description ....................................................... 1616 

7.5 Display Subsystem Basic Programming Model .................................................. 1690 

7.6 Display Subsystem Use Cases and Tips ........................................................... 1761 

7.7 Display Subsystem Register Manual ................................................................ 1795 

SPRUGN4L–May 2010–Revised June 2011 Display Subsystem 

Copyright © 2010–2011, Texas Instruments Incorporated 

1541


Display Subsystem Overview www.ti.com 

7.1 Display Subsystem Overview 

The display subsystem provides the logic to display a video frame from the memory frame buffer (either 

SDRAM or SRAM) on a liquid-crystal display (LCD) panel or a TV set. The display subsystem integrates 

the following elements: 

• Display controller (DISPC) module 

• Remote frame buffer interface (RFBI) module 

• Display serial interface (DSI) complex I/O module and a DSI protocol engine 

• DSI PLL controller that drives a DSI PLL and high-speed (HS) divider. 

• NTSC/PAL video encoder 

The display controller and the DSI protocol engine are connected to the L3 and L4 interconnect; the RFBI 

and the TV out encoder modules are connected to the L4 interconnect. 

NOTE: The DSI complex I/O module, and the DSI PLL controller are not connected to an L3 or L4 

interconnect. Specific display subsystem registers manage their programmable features. 

Figure 7-1 shows a block diagram of the display subsystem. 

1542 Display Subsystem SPRUGN4L–May 2010–Revised June 2011 

Copyright © 2010–2011, Texas Instruments Incorporated

Device 

PRCM 

L4 interconnect 


System DMA 

controller 

(sDMA) 

MPU 

subsystem 

interrupt 

controller 

IVA2.2 

subsystem 

interrupt 

controller 

System 

control 

module 

L3 clock 

L4 clock 

Functional clock1 

Functional clock2 

54-MHz clock 

4 

DSS_L3_ICLK 

DSS_L4_ICLK 

DSS1_ALWON_FCLK 


DSS_TV_FCLK 

DSI1_PLL_FCLK 

DSI2_PLL_FCLK 

DSS_LINE_TRIGGER 

DSS_DMA_REQ[3:0] 

DSS_IRQ 

Display 

controller 

Syncs 

DSI 

protocol 

engine 

Display subsystem 

Digital data 

24 

TV syncs 

Data 

Controls 


www.ti.com Display Subsystem Overview 

Figure 7-1. Display Subsystem Highlight 

Remote 

frame buffer 

interface 

TV out 

encoder 

Video DAC 

stage 

TVACEN 

TVOUTBYPASS 

COMP_EN 

DSI 

complex I/O 

DSI 

PLL 

controller 

DSS_PCLK 

DSS_VSYNC 

DSS_HSYNC 

DSS_ACBIAS 

DSS_DATA[17:6] 

DSS_DATA[23:18] 

TVINT 

Composite/Luma 

DSS_DATA[5:0] 

DSI_DX0 

DSI_DY0 

DSI_DX1 

DSI_DY1 

DSI_DX2 

DSI_DY2 

Status 

Chroma 

PLL control 

Pin multiplexing 

Pin multiplexing 

DSI PLL 

HS divider 

GPIO2 

dss_pclk 

dss_vsync 

dss_hsync 

dss_acbias 

dss_data[17:6] 


cvideo1_out 

cvideo2_out 

cvideo1_vfb 

cvideo2_vfb 

cvideo1_rset 

vdda_dac 

vssa_dac 

dss_data[0]/dsi_dx0 

dss_data[1]/ dsi_dy0 

dss_data[2]/ dsi_dx1 


dss_data[4]/ dsi_dx2 


NOTE: For more information about connecting the LOCK, RECAL, and TVINT signals through the 

GPIO2 and GPIO3 modules, see Chapter 25, GPIO. 

The display subsystem includes the following main features: 

• Display controller 

– Display modes 

vdds_dsi 

vdd_dsi 

vss_dsi 

camdss-001 

• Programmable pixel display modes (1, 2, 4, 8, 12, 16, and 24 bits-per-pixel [BPP] modes) 

• Programmable display size supported: 



1543



• XGA - 1024 x 768 VESA timings at 60 fps (pixel clock = 63.5 MHz) 

• WXGA - 1280 x 800 VESA timings at 59.91 fps (pixel clock = 71 MHz) 

• SXGA+ - 1400 x 1050 direct drive of LCD with minimal blanking at 50 fps (pixel clock = 75 

MHz) 

• HD 720p - 1280 x 720 at 60 fps (pixel clock = 74.25 MHz) 

• 256 x 24-bit entries palette in red, green, and blue (RGB) 

• Programmable pixel rate up to 75 MHz 

NOTE: The panel size is programmable and can be any width that is a multiple of 8 pixels (line 

length) in the range [1:2048] pixels (in the case of the RFBI mode, the minimum transfer 

size is a byte). The maximum resolution is 2048 (lines) x 2048 (pixels). 

– Display support 

• Four types of displays are supported: Passive (super-twist nematic [STN]) and active (thin-film 

transistor [TFT]) colors, passive (STN), and active (TFT) monochromes. 

• 4-/8-bit monochrome passive matrix panel interface support (15 grayscale levels supported 

using dithering block) 

• 8-bit color passive matrix panel interface support (3375 colors supported for a color panel using 

dithering block) 

• 12-/16-/18-/24-bit active matrix panel interface support (replicated or dithered encoded pixel 

values) 

• Remote frame buffer support through the RFBI module 

• Partial display through the RFBI module 

• Second 24-bit digital output 

• Multiple-cycle output format on 8-/9-/12-/16-bit interface time division multiplexing (TDM) 

• HDMI through external bridge 

– Signal processing 

• Overlay support for graphics (ARGB, RGBA, RGB, or Color Look-Up Table (CLUT)) and video1 

(YCbCr 4:2:2, RGB), video2 (YCbCr 4:2:2, or ARGB, RGBA, RGB) 

• Programmable video resizer independent horizontal and vertical resampling: Upsampling (up to 

x8) and downsampling (down to 1/4), maximum input width of 1024 pixels in 5-tap mode, and 

2048 pixels in 3-tap configurations; no limitation on input height 

• Rotation 90-, 180-, and 270-degrees with DISPC DMA engine 

• Transparency color key (source and destination) 

• Synchronized buffer update 

• Programmable video color space conversion YCbCr 4:2:2 into RGB 

• Hardware cursor 

• Gamma curve support on LCD output 

• Multiple-buffer support 

• Mirroring support 

• Programmable color phase rotation (CPR) 

• Alpha blending support (no rescaling in ARGB or RGBA formats), with pre-multiplied alpha 

control 

– Advanced 

• Self-refresh using the DMA FIFO 

• Arbitration between high/low priority (graphics video1 and video2) 

• FIFO handcheck in STALL mode 

– Power modes: Low-power saving modes 

• RFBI (MIPI® DBI protocol) 

– Access to remote frame buffer (RFB) direct microprocessor unit (MPU) interface 

• Sends commands to the RFB panel through the L4 interconnect 

• Sends data, received from the display controller or from the MPU through the DISPC pixel data 

bus, to the RFB panel 




www.ti.com Display Subsystem Overview 

• Reads data/status from the RFB to the L4 interconnect 

– RFB interface 

• 8-/9-/12-/16-bit 8086-series parallel interface 

• Two programmable configurations for two devices connected to the RFBI module 

– Data formats 

• Programmable pixel modes (12-/16-/18-/24-BPP modes in RGB format) 

• Programmable output formats on one/multiple cycles per pixel (data from the display controller 

and from the L4 interconnect) 

– Interconnect/FIFO 

• One slave port with DMA request and interconnect FIFO of 24x32-bit depth (for write access to 

DSS.RFBI_DATA register only) 

• One video port FIFO of 8 × 24-bit depth receiving data from the display controller 

• MIPI DSI 

– Transfer pixels and data received on the video port or L4 interconnect to the display through the 

DSI DSI_PHY 

– The maximum resolution supported on the video port is XGA at 60 fps with 24-bit pixels (maximum 

pixel clock of 67 MHz) for low voltage. 

– Supports video mode and command mode 

– Bidirectional data link support (only one data lane is used in reverse direction in command mode) 

– Supports up to two data-configurable lanes, in addition to the clock signaling (minimum of one data 

link and maximum of two, depending on speed, signal integrity requirements, and number of 

displays) 

– Maximum data rate of up to 900 Mbps per data pair 

– Data splitter for 2-data lane configuration 

– Error-correction code (ECC) and check-sum generation 

– Burst support for the video mode 

– RGB16, RGB18 packed and nonpacked, and RGB24 formats supported for video mode 

– Serial configuration port (SCP) for the DSI_PHY complex I/O and DSI PLL 

– Connection to the DSI_PHY complex I/O through PPI 

– Data interleaving support for one synchronous stream (video mode) from the display controller and 

up to three interleaved asynchronous streams (command mode) from the interconnect concurrently 

– Data interleaving supports up to four interleaved asynchronous streams (command mode) from the 

interconnect or video port when there is no video mode 

– MIPI DCS support (transparent to the protocol engine, no decoding and interpretation of the 

information from and to the peripheral) 

– Supports selection between low-power state and HS mode between HS packet transfers 

– Generic data type (DT) support 

NOTE: The DSI pins are multiplexed with LCD parallel outputs. 

• Video encoder 

– NTSC/PAL encoder outputs with the following standards: 

• NTSC-J, M 

• PAL-B, D, G, H, I 

• PAL-M 

– CGMS-A as described in the CEA-608-x Standard. 

– Input data interface compatible with the following protocols: 

• 24-bit input bus compatible with external sync 

• RGB 4:4:4 

– Dual output data 10-bit interface for two internal digital-to-analog converters (DACs) that support: 

• Composite video (CVBS) 

• Separate video (S-video) 



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– TV output data supports ITU-R BT 470-7 recommendation standard for consumer market 

– Master clock input 13.5 MHz, 27 MHz (supports ITU-R 601 sampling for NTSC/PAL), and 54 MHz 

– Programmable horizontal sync, vertical timing, and waveforms 

– Programmable subcarrier frequency and SCH 

– Internal test pattern generation (color bar, flat field, color burst) 

– 2x/4x oversampling 

– Supports square pixel sampling (NTSC: 12.27 MHz, 24.54 MHz, 49.09 MHz PAL: 14.75 MHz, 

29.5 MHz, 59 MHz) 

CAUTION 

In square pixel mode, an external clock generator is required to provide 

sampling frequencies. 

– TV detection gating pulse generation 




www.ti.com Display Subsystem Environment 

7.2 Display Subsystem Environment 

This section describes the two main functions handled by the display subsystem: 

• LCD support 

• TV display support 

7.2.1 LCD Support 

LCD panels can be connected to the display subsystem of the device using parallel and/or serial 

interfaces. 

Table 7-1 provides more details on the supported interfaces to LCD panels, and the respective pad and 

signal configurations. 



1547


Display Subsystem Environment www.ti.com 

Table 7-1. LCD Interface Signals and Configurations 

Pads and Signals Configuration Possible Operational Interfaces 

Pad names at Pads Property Basic signal multiplexing on pads Additional signal multiplexing on Simultaneous Sequential 

device level pads 

boundary. 

Parallel Parallel Serial Interface, Parallel Parallel "1. Parallel "1. Parallel "1. Parallel 

Interface, Interface, RFBI DSI. Interface, Interface, RFBI Interface, Interface, Interface, 

Bypass Mode. mode. Bypass Mode. mode. Bypass mode RFBI-0 mode RFBI-0 mode 

24-bit 16-bit 16-bit 

2. Serial 2. Serial 2. Parallel 

Interface, DSI (2 Interface, DSI (2 Interface, 

data lanes)" data lanes)" RFBI-1 mode 

16-bit" 

dss_hsync Display DISPC_HSYNC RFBI_CS0 DISPC RFBI (CS0) RFBI (CS0) 

subsystem 

dss_vsync DISPC_VSYNC RFBI_WR RFBI RFBI 

dss_pclk DISPC_PCLK RFBI_RD 

dss_acbias DISPC_ACBIAS RFBI_A0 

dss_data0 DISPC_DATA_L RFBI_DA0 DSI_DX0 DSI DSI RFBI_DA [0-5] 

CD0 

dss_data1 DISPC_DATA_L RFBI_DA1 DSI_DY0 

CD1 

dss_data2 DISPC_DATA_L RFBI_DA2 DSI_DX1 

CD2 


CD3 

dss_data4 DISPC_DATA_L RFBI_DA4 DSI_DX2 

CD4 


CD5 

dss_data6 DISPC_DATA_L RFBI_DA6 DISPC_DATA_L RFBI_DA [6-15] RFBI_DA [6-15] 

CD6 CD [6-17] 

dss_data7 DISPC_DATA_L RFBI_DA7 

CD7 


CD8 


CD9 


CD10 


CD11 


CD12 

1548Display Subsystem SPRUGN4L–May 2010–Revised June 2011 




Table 7-1. LCD Interface Signals and Configurations (continued) 




boundary. 








16-bit" 


CD13 

dss_data14 DISPC_DATA_L RFBI_DA14 RFBI_DA [6-15] RFBI_DA [6-15] 

CD14 

dss_data15 Display DISPC_DATA_L RFBI_DA15 DISPC_DATA_L 

subsystem CD15 CD [6-17] 

dss_data16 DISPC_DATA_L RFBI_TE_VSYN "RFBI(sync0)" "RFBI(sync0)" 

CD16 C0 

dss_data17 DISPC_DATA_L RFBI_HSYNC0 

CD17 

dss_data18 DISPC_DATA_L RFBI_TE_VSYN DISPC_DATA_L RFBI_DA0 DISPC_DATA_L RFBI_DA [0-5] "RFBI(sync1)" 

CD18 C1 CD0 CD [0-5] 

dss_data19 DISPC_DATA_L RFBI_HSYNC1 DISPC_DATA_L RFBI_DA1 

CD19 CD1 

dss_data20 DISPC_DATA_L RFBI_CS1 DISPC_DATA_L RFBI_DA2 RFBI (CS1) 

CD20 CD2 

dss_data21 DISPC_DATA_L DISPC_DATA_L RFBI_DA3 

CD21 CD3 


CD22 CD4 


CD23 CD5 

SPRUGN4L–May 2010–Revised June 2011 Display Subsystem1549 




Table 7-1. LCD Interface Signals and Configurations (continued) 




boundary. 








16-bit" 

sys_boot0 System control DISPC_DATA_L DISPC_DATA_L 

module CD18 CD [18-23] 

sys_boot1 DISPC_DATA_L 

CD19 


CD20 


CD21 


CD22 


CD23 

The DISPC_DATA_LCD[23:18] data is additionally multiplexed on the sys_boot device pads to allow simultaneous availability of the DSI interface 

and the complete parallel 24-bit DSS interface. 

NOTE: The DISPC_DATA_LCD[5:0] data multiplexed with the DSI signals on dss_data[5:0] pads is limited to up to 60 MHz pixel clock 

frequency. If the parallel 18/24-bit interface in bypass mode with a pixel clock above 60 MHz is required, the DISPC_DATA_LCD[5:0] 

multiplexed on dss_data[23:18] pads, and DISPC_DATA_LCD[23:18] multiplexed on sys_boot pads must be used. 

NOTE: Table 7-1 shows only the DSS capabilities of supporting simultaneous and sequential LCD interfaces due to the additional signal 

multiplexing, without describing explicitly all possible configurations. 

For more information on signals multiplexing, see Chapter 13, System Control Module. The parallel interface connectivity is detailed in 

Section 7.2.1.1, Parallel Interface. For more details on the serial interface, see Section 7.2.1.2, DSI Serial Interface. 





7.2.1.1 Parallel Interface 

In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI. 

The display controller provides the required control signals to interface the memory frame buffer (SDRAM 

or SRAM) directly to the external displays. The display controller is connected to the memory through the 

L3 interconnect and has its own DMA (with embedded FIFOs) to read data from the system memory. The 

L3 interconnect is the master port, while the L4 interconnect is the slave port of the display subsystem. 

The display controller has two I/O pad modes at the module level: 

• RFBI mode (RFBI enabled), which implements the MIPI DBI 2.0 protocol 

• Bypass mode (RFBI disabled), which implements the MIPI DPI 1.0 protocol 

The DSS.DISPC_CONTROL[16:15] GPOUT[1:0] bits control selection of the display subsystem modules 

(see Table 7-2). 

Table 7-2. I/O Pad Mode Selection 

DSS.DISPC_CONTROL[16] GPOUT1 DSS.DISPC_CONTROL[15] GPOUT0 Mode 

0 0 Reset 

0 1 RFBI mode 

1 0 Invalid 

1 1 Bypass mode 

The RFB of the LCD panel is connected directly to the RFBI module of the device. The RFBI controls the 

reads/writes from/to the RFB. The RFBI receives the output from the DISPC (which takes data from the 

memory) and generates the signals to control the LCD panel. Through the RFBI, the MPU can send 

commands or parameter/display data to the LCD panel and directly set the DISPC registers to read/write 

the data from/to the memory in the LCD panel. The RFBI can manage up to two LCD panels when the 

serial interface is not used. 

7.2.1.1.1 Parallel Interface in RFBI Mode (MIPI DBI Protocol) 

Figure 7-2 shows the LCD support parallel interface in RFBI mode (example for 16-bit data interface). 



1551



controller 

RFBI 

RFBI_DA[15:0] 

RFBI_RD 

RFBI_WR 

RFBI_A0 

RFBI_CS0 

RFBI_TE_VSYNC0 

RFBI_HSYNC0 

RFBI_TE_VSYNC1 

RFBI_HSYNC1 



Figure 7-2. LCD Support Parallel Interface (RFBI Mode) 

RFBI_CS1 


dss_pclk 

dss_vsync 

dss_acbias 

dss_hsync 

dss_data16 

dss_data17 

dss_data18 

dss_data19 

dss_data20 

LCD 

panel 1 

with RFB 

LCD 

panel 2 

with RFB 

NOTE: Configure the DSS.RFBI_CONTROL[3:2] CONFIGSELECT bit field to drive signals for LCD 

1 only, LCD 2 only, or both LCD 1 and LCD 2. 

Table 7-3 describes the interface signals to/from the LCD panel in RFBI mode. 

Signal Name Type (1) Description 

RFBI_DA[15:0] I/O RFBI I/O data 

Table 7-3. LCD Interface Signals (RFBI Mode) 

RFBI_RD O Read access signal 

RFBI_WR O Write access signal 

RFBI_A0 O Command/data selection signal 

RFBI_CS0 O Chip-select (CS) signal for LCD 1 

RFBI_CS1 O CS signal for LCD 2 

RFBI_TE_VSYNC0 I Tearing effect (TE) synchronization signal (TE or VSYNC for LCD panel 1) 

RFBI_HSYNC0 I HSYNC from LCD panel 1 

RFBI_TE_VSYNC1 I TE synchronization signal (TE or VSYNC for LCD panel 2) 

RFBI_HSYNC1 I HSYNC from LCD panel 2 

(1) I = Input, O = Output 

• RFBI_DA[15:0]: The pixel data comprises the RFBI pixel data (bits 15:0). A write/read command must 

be sent to the LCD panel to send/read the data. 

Before any data access, the application must send commands and parameters when it is necessary to 

configure an LCD panel. The data is used as input in read operations during production test and also 

to read the status of the registers in the LCD panel and pixels from the embedded frame buffer in the 

LCD panel module. RFBI_DA is multiplexed at the chip-level boundary with dss_data [15:0]. 

• RFBI_RD: This is the read-enable signal used to indicate when a read from the embedded memory in 

the LCD panel is ongoing. The RFBI registers describe the behavior of the read signal (off/on/cycle 

time). The polarity of the read-enable signal is programmable. This signal is multiplexed at the 



dss-002

DSS_L4_ICLK 

TE 

VSYNC 

HSYNC 



chip-level boundary with dss_pclk. The read is used to get status/data information from the LCD panel. 

• RFBI_WR: The write-enable signal is used to indicate when a write is ongoing. The RFBI registers 

describe the behavior of the write signal (off/on/cycle time). The polarity of the write-enable signal is 

programmable. This signal is multiplexed at the chip-level boundary with dss_vsync. 

• RFBI_A0: The signal is asserted to indicate its status: Command or data. The polarity is programmable 

and the status of the signal depends on the RFBI registers written by the application 

(CMD/READ/STATUS/PARAM/PIXEL). The register in use by the hardware defines the status of 

RFBI_A0. The order of the writes/reads to the RFBI registers CMD/READ/STATUS/PARAM/PIXEL 

defines the transitions of A0. This signal is multiplexed at the chip-level boundary with dss_acbias. 

• RFBI_CSx: The signal is the chip-select (CSx) asserted to indicate which LCD panel is selected and 

must be ready to receive/transmit commands and data. When RE or WE is on, CSx must not be 

changed (x = 0 for LCD panel 1; x = 1 for LCD panel 2). CS0 is multiplexed at the chip-level boundary 

with dss_hsync, and CS1 is multiplexed at the chip-level boundary with dss_data[20]. 

• RFBI_TE_VSYNCx: Based on the trigger mode selected, the signal is the TE pulse signal or the LCD 

panel VSYNC (vertical synchronization) pulse signal. RFBI_TE_VSYNCx is used by the TE logic as the 

synchronization signal to send the pixel to the LCD panel. 

To select the trigger mode, configure the DSS.RFBI_CONFIGi[3:2] TRIGGERMODE bit field (0x0: 

Internal trigger mode with the DSS.RFBI_CONTROL[4] ITE bit, 0x1: External trigger mode with the TE 

signal RFBI_TE_VSYNCx, 0x2: External trigger mode with the RFBI_TE_VSYNCx, and 

RFBI_HSYNCx signals with the programmable line counter). 

These signals are multiplexed at the chip-level boundary with dss_data[16] (RFBI_TE_VSYNC0) and 

dss_data[18] (RFBI_TE_VSYNC1) (LCD panel 1: x = 0; LCD panel 2: x = 1). 

• RFBI_HSYNCx: The HSYNC pulse signals indicate to the RFBI module when horizontal 

synchronization occurs. The polarity of the HSYNC signals is programmable. The minimum pulse width 

of the signal is two L4 cycles. RFBI_HSYNC is used by the TE logic as a synchronization signal to 

send the pixel to the LCD panel. These signals are multiplexed at the chip-level boundary with 

dss_data[17] (RFBI_HSYNC0) and dss_data[19] (RFBI_HSYNC1) (LCD panel 1: x = 0; LCD panel 2: x 

= 1). 

7.2.1.1.1.1 Description of the TE Pulse Signal 

The externally-generated TE synchronization signal is a logical OR or AND operation between the HSYNC 

and VSYNC signals (see Figure 7-3). The logical operation (OR or AND) depends on the HSYNC and 

VSYNC signals polarity. The VSYNC signal indicates to the RFBI module when vertical synchronization 

occurs; the HSYNC signal indicates to the RFBI module when horizontal synchronization occurs. 

Figure 7-3. External Generation of TE Signal Based on Logical OR Operation Between HSYNC and 

VSYNC (Active-High) 

The RFBI module detects the VSYNC and HSYNC pulses embedded in the received signal. VSYNC is 

detected based on the minimum pulse width defined by the DSS.RFBI_VSYNC_WIDTH register. 

HSYNC is detected based on the minimum pulse width defined by the DSS.RFBI_HSYNC_WIDTH 

register. 

The signal is generated from external logic based on the VSYNC/HSYNC of the LCD panel. The 

automatic trigger can be programmed based on the RFBI_TE signal or use a bit field in the RFBI registers 

to start data capture. 



dss-003 

1553



controller 

DISPC_DATA_LCD[23:0] 

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 



The polarity of the TE signal is programmable. The HSYNC and VSYNC pulses embedded in the TE 

signal have the same polarity, which is active high for an ORed signal and active low for an ANDed signal. 

The minimum pulse width of the signal is two L4 cycles. Hardware resets the line counter when the 

VSYNC occurs and increments it at every HSYNC. Transfer to the LCD panel begins when the line 

counter reaches the programmable line number. 

7.2.1.1.2 Parallel Interface in Bypass Mode (MIPI DPI Protocol) 

When bypass mode is enabled, the display controller must be set to use it. 

Figure 7-4 shows the LCD support parallel interface in bypass mode. 

Figure 7-4. LCD Support Parallel Interface (Bypass Mode) 

RFBI 


dss_pclk 

dss_vsync 

dss_hsync 

dss_acbias 

Table 7-4 describes the interface signals to/from the LCD panel in bypass mode. 

Table 7-4. LCD Interface Signals (Bypass Mode) 


DISPC_DATA_LCD[23:0] O LCD data from the display controller module 

DISPC_PCLK O Pixel CLK from the display controller module 

DISPC_VSYNC O VSYNC from the display controller module 

DISPC_HSYNC O HSYNC from the display controller module 

DISPC_ACBIAS O ACBIAS from the display controller module 

(1) I = Input, O = Output, I/O = Input/Output 

LCD 

panel 

• DISPC_DATA_LCD[23:0]: The panel pixel data comes directly from the display controller module. 

DISPC_DATA_LCD is connected at the chip-level boundary with dss_data[23:0]. 

• DISPC_PCLK: This signal is the pixel clock that comes directly from the display controller. This signal 

is multiplexed at the chip-level boundary with dss_pclk. 

• DISPC_VSYNC: Uses the vertical synchronization signal from the display controller. The LCD frame 

clock (VSYNC) toggles after all the lines in a frame are transmitted to the LCD panel and a 

programmable number of line clock cycles has elapsed both at the beginning and at the end of each 

frame. This signal is multiplexed with dss_vsync at the chip-level boundary. 

• DISPC_HSYNC: Uses the horizontal synchronization signal from the display controller. The LCD line 

clock (HSYNC) toggles after all pixels in a line are transmitted to the LCD panel and a programmable 

number of pixel clock wait-states elapse, both at the beginning and at the end of each line. This signal 

is multiplexed on the chip-level boundary with dss_hsync. 

• DISPC_ACBIAS: Uses the ac-bias signal from the display controller. 

– In passive matrix technology, the ac-bias signal is configured to transition each time a 

programmable number of line clocks occurs. To prevent a dc charge within the screen pixels, the 

power and ground supplies of the panel are periodically switched. The DISPC signals the panel to 

switch the polarity by toggling the ac-bias pin. 



dss-004

LCD 

controller 

output 

pins 

Pixel clock 



– In active matrix technology, the ac-bias signal acts as an output-enable signal to indicate when data 

must be latched using the pixel clock. This signal is multiplexed on the chip-level boundary with 

dss_acbias. 

7.2.1.1.3 LCD Output and Data Format for the Parallel Interface 

This section describes the pixel data bus and shows timing diagrams of transactions and synchronizations 

in both RFBI and bypass modes. 

Figure 7-5 through Figure 7-11 show the pixel data bus for bypass mode, depending on the use of 4-, 8-, 

12-, 16-, 18-, or 24-pixel data output pins. In RFBI mode, the pixel data bus is reformatted in accordance 

with the input and output data bus width. 

Table 7-5 lists the number of displayed pixels per pixel clock cycle based on the type of display panel. 

Table 7-5. Number of Displayed Pixels per Pixel Clock Cycle Based on Display 

Type 

Display Panel Number of Displayed 

Pixels per Pixel Clock Cycle 

Monochrome 4-bit 4 

Monochrome 8-bit 8 

Passive matrix color 8/3 

Active matrix 1 

• Passive matrix technology, Monochrome mode 

Monochrome displays use either a 4-bit or 8-bit interface. Each bit represents one pixel (on or off), 

which means that either 4 or 8 pixels are sent to the LCD at each pixel clock. 

Figure 7-5 and Figure 7-6 show 4- and 8-bit monochrome displays, respectively. 

Figure 7-5. LCD Pixel Data Monochrome4 Passive Matrix 

Pix1 

Pix2 

Pix3 

Pix4 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[2] 

dss_data[3] 

Pixel data [3:0] 



dss-005 

1555


controller 

output pins 

Pixel clock 

LCD 

controller 

output pins 

Pixel clock 

(Pix3) G 

(Pix3) R 

(Pix2) B 

(Pix2) G 

(Pix2) R 

(Pix1) B 

(Pix1) G 

(Pix1) R 



Figure 7-6. LCD Pixel Data Monochrome8 Passive Matrix 

Pix1 

Pix2 

Pix3 

Pix4 

Pix5 

Pix6 

Pix7 

Pix8 

(Pix6) R 

(Pix5) B 

(Pix5) G 

(Pix5) R 

(Pix4) B 

(Pix4) G 

(Pix4) R 

(Pix3) B 

(Pix8) B 

(Pix8) G 

(Pix8) R 

(Pix7) B 

(Pix7) G 

(Pix7) R 

(Pix6) B 

(Pix6) G 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[2] 

dss_data[3] 

dss_data[4] 

dss_data[5] 

dss_data[6] 

dss_data[7] 

Pixel data [7:0] 

• Passive matrix technology, color mode 

Color passive displays use 8-bit data input lines. In a given pixel clock cycle, each line represents one 

color component (red, green, or blue). 

Figure 7-7 shows an 8-bit color passive matrix display. 

Figure 7-7. LCD Pixel Data Color Passive Matrix 

dss-006 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[2] 

dss_data[3] 

dss_data[4] 

dss_data[5] 

dss_data[6] 

dss_data[7] 

• Active matrix technology 

Active matrix displays bypass the STN dithering logic block and the output FIFO. Each line represents 

one pixel. 

Figure 7-8 through Figure 7-11 show 12-, 16-, 18-, and 24-active matrix displays, respectively. 



Pixel 

data 

[7:0] 

dss-007

LCD 

controller 

output pins 

Pixel clock 

(Pix1) B0 

(Pix1) B1 

(Pix1) B2 

(Pix1) B3 

(Pix1) G0 

(Pix1) G1 

(Pix1) G2 

(Pix1) G3 

(Pix1) R0 

(Pix1) R1 

(Pix1) R2 

(Pix1) R3 

(Pix2) B0 

(Pix2) B1 

(Pix2) B2 

(Pix2) B3 

(Pix2) G0 

(Pix2) G1 

(Pix2) G2 

(Pix2) G3 

(Pix2) R0 

(Pix2) R1 

(Pix2) R2 

(Pix2) R3 



Figure 7-8. LCD Pixel Data Color12 Active Matrix 

(Pix3) B0 

(Pix3) B1 

(Pix3) B2 

(Pix3) B3 

(Pix3) G0 

(Pix3) G1 

(Pix3) G2 

(Pix3) G3 

(Pix3) R0 

(Pix3) R1 

(Pix3) R2 

(Pix3) R3 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[2] 

dss_data[3] 

dss_data[4] 

dss_data[5] 

dss_data[6] 

dss_data[7] 

dss_data[8] 

dss_data[9] 

dss_data[10] 

dss_data[11] 



Pixel 

data 

[11:0] 

dss-008 

1557

LCD 

controller 

output pins 

Pixel clock 

LCD 

controller 

output pins 

Pixel clock 

(Pix1) B0 

(Pix1) B1 

(Pix1) B2 

(Pix1) B3 

(Pix1) B4 

(Pix1) R0 

(Pix1) R1 

(Pix1) R2 

(Pix1) R3 

(Pix1) R4 

(Pix1) B0 

(Pix1) B1 

(Pix1) B5 

(Pix1) R0 

(Pix1) R3 

(Pix1) R4 

(Pix1) R5 

(Pix2) B0 

(Pix2) B1 

(Pix2) B2 

(Pix2) B3 

(Pix2) B4 

(Pix2) R0 

(Pix2) R1 

(Pix2) R2 

(Pix2) R3 

(Pix2) R4 

(Pix2) B0 

(Pix2) B1 

(Pix2) B5 

(Pix2) R0 

(Pix2) R3 

(Pix2) R4 

(Pix2) R5 




(Pix3) B0 

(Pix3) B1 

(Pix3) B2 

(Pix3) B3 

(Pix3) B4 

(Pix3) R0 

(Pix3) R1 

(Pix3) R2 

(Pix3) R3 

(Pix3) R4 


(Pix3) B0 

(Pix3) B1 

(Pix3) B5 

(Pix3) R0 

(Pix3) R3 

(Pix3) R4 

(Pix3) R5 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[2] 

dss_data[3] 

dss_data[4] 

dss_data[11] 

dss_data[12] 

dss_data[13] 

dss_data[14] 

dss_data[15] 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[5] 

dss_data[12] 

dss_data[15] 

dss_data[16] 

dss_data[17] 

Pixel 

data 

[15:0] 

dss-009 

Pixel 

data 

[17:0] 



dss-010

LCD 

controller 

output pins 

DISPC_FCLK 

DISPC_PCLK 

DISPC_DATA_STALL 

DISPC_LCD_DATA[23:0] 

Pixel clock 

(Pix1) B0 

(Pix1) B1 

(Pix1) B7 

(Pix1) G0 

(Pix1) G7 

(Pix1) R0 

(Pix1) R5 

(Pix1) R6 

(Pix1) R7 

(Pix2) B0 

(Pix2) B1 

(Pix2) B7 

(Pix2) G0 

(Pix2) G7 

(Pix2) R0 

(Pix2) R5 

(Pix2) R6 

(Pix2) R7 

4_DISPC_CLK_cycle_for_assertion 



7.2.1.1.4 Transaction Timing Diagrams 

• Timing diagrams in flow control mode 


(Pix3) B0 

(Pix3) B1 

(Pix3) B7 

(Pix3) G0 

(Pix3) G7 

(Pix3) R0 

(Pix3) R5 

(Pix3) R6 

(Pix3) R7 

Pixel data 

dss_data[0] 

dss_data[1] 

dss_data[7] 

dss_data[8] 

dss_data[15] 

dss_data[16] 

dss_data[21] 

dss_data[22] 

dss_data[23] 

PIXELS 1 PIXELS 2 PIXELS 3 PIXELS 4 PIXELS 5 

Pixel 

data 

[23:0] 

– Stall signal 

The stall signal is used in RFBI and DSI modes. In the case of RFBI mode, it is used to indicate 

when the display controller must stop sending data over the LCD output interface. The RFBI 

module asserts the stall signal to stop data output by the display controller. It is deasserted to 

indicate when new data must be outputted by the display controller. 

Figure 7-12. RFBI Data Stall Signal Diagram 

dss-011 

1_DISPC_CLK.cycle_after_for_de_assertion 

To avoid underflow of the DMA FIFO, the FIFO handcheck feature can be enabled by setting the 

DSS.DISPC_CONFIG[16] FIFOHANDCHECK bit to 1. The fullness of the FIFOs associated with 

the pipelines used for the LCD output is checked when the STALL signal is inactive before 

providing data to the pipeline. This prevents emptying the FIFO when the RFBI module requests 

data and there is not enough data in the display controller DMA FIFO. This feature must be enabled 

only when the STALL mode is used (DSS.DISPC_CONTROL[11] STALLMODE bit set to 1). 

When the FIFO handcheck feature is activated, the pixel transfer to the RFBI module during STALL 

inactivity period can be stopped (no DISPC_PCLK pulse) and restarted when there is enough data 

in the FIFO. The FIFO handcheck ensures that underflow cannot occur for the pipelines associated 

with the LCD output in RFBI mode. Figure 7-13 details the RFBI data stall with FIFO handcheck 

mode activated. 



dss-134 

1559

DISPC_FCLK 

DISPC_PCLK 

DISPC_DATA_STALL 

DISPC_LCD_DATA[23:0] 

L4_CLK 

RFBI_A0(D/C) 

RFBI_CSi 

(with i = 0, 1) 

RFBI_WR 

DISPC_CLK_cycles_for_assertion 

1_DISPC_CLK_cycle_for_de_assertion 

PIXELS 1 PIXELS 2 PIXELS 3 

WECycleTime 

CSOnTime 

CSOffTime 

WEOffTime 

WEOnTime 



Figure 7-13. RFBI Data Stall Signal Diagram With Handcheck 

– RFBI timing diagrams 

Table 7-6 lists the programmable timing fields. Figure 7-14 through Figure 7-16 show timing diagrams 

of read/write transactions to the LCD panel for the RFBI mode. 

Table 7-6. Programmable Timing Fields in RFBI Mode 

Timing Name Register Field Description 

CSOnTime DSS.RFBI_ONOFF_TIMEi[3:0] CS assertion time from start access time 

CSONTIME (with I = 0 or 1) 

CSOffTime DSS.RFBI_ONOFF_TIMEi[9:4] CS deassertion time from start access time 

CSOFFTIME (with I = 0 or 1) 

WeCycleTime DSS.RFBI_CYCLE_TIMEi[5:0] The time when A0 becomes valid until write cycle 

WECYCLETIME (with I = 0 or 1) completion 

WEOnTime DSS_RFBI_ONOFF_TIMEi[13:10] WE assertion delay time from start access time 

WEONTIME (with I = 0 or 1) 

WEOffTime DSS_RFBI_ONOFF_TIMEi[19:14] WE deassertion delay time from start access time 

WEOFFTIME (with I = 0 or 1) 

RECycleTime DSS.RFBI_CYCLE_TIMEi[11:6] The time when A0 becomes valid until read cycle 

RECYCLETIME (with I = 0 or 1) completion 

REOnTime DSS_RFBI_ONOFF_TIMEi[23:20] RE assertion delay time from start access time 

REONTIME (with I = 0 or 1) 

REOffTime DSS.RFBI_ONOFF_TIMEi[29:24] RE assertion delay time from start access time 

REOFFTIME (with I = 0 or 1) 

CSPulseWidth DSS.RFBI_CYCLE_TIMEi[17:12] The time when write cycle time or read cycle time 

CSPULSEWIDTH (with I = 0 or 1) completes 

Figure 7-14. Command Data Write 

WECycleTime 

CSOnTime 

RFBI_DA[15:0] DATA0 DATA1 



dss-135 

dss-012

L4_CLK 

RFBI_A0(D/C) 

RFBI_CSi 

(with i = 0, 1) 

RFBI_RD 

RFBI_DA[15:0] 

L4_CLK 

RFBI_A0(D/C) 

RFBI_CSi 

(with i = 0, 1) 

RFBI_RD 

RFBI_WR 

RFBI_DA[15:0] 

RECycleTime 

CSOffTime 

CSOnTime 

REOnTime 

AccessTime 

CSOnTime 

REOffTime REOffTime 

CSOffTime 

CSOnTime 



Figure 7-15. Display Data Read 

DATA0 DATA1 

Figure 7-16. Read to Write and Write to Read 

RECycleTime WECycleTime 

CSPulseWidth CSPulseWidth 

CSOffTime CSOffTime 

CSOnTime 

CSOnTime 

READ0 WRITE0 READ1 

• Timing diagrams in bypass mode 

Figure 7-17 through Figure 7-32 show timing diagrams of synchronization signals and pixel clock in 

bypass mode for both passive matrix and active matrix panels. The display controller directly drives 

these signals, which are related to the programmable fields described in Table 7-7. 

Table 7-7. Programmable Fields in Bypass Mode 

Name Register Description 

PPL DSS.DISPC_SIZE_LCD[10:0] PPL bit field value + 1 Pixels per line (PPL) 

LPP DSS.DISPC_SIZE_LCD[26:16] LPP bit field value + 1 Lines per panel 

HBP DSS.DISPC_TIMING_H[31:20] HBP bit field value + 1 Horizontal back porch 

HFP DSS.DISPC_TIMING_H[19:8] HFP bit field value + 1 Horizontal front porch 

HSW DSS.DISPC_TIMING_H[7:0] HSW bit field value + 1 Horizontal synchronization pulse width 

VBP DSS.DISPC_TIMING_V[31:20] VBP bit field value Vertical back porch 



dss-013 

dss-014

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 

HSW VSW VBP HBP 

DISPC_DATA_LCD[23:0] PIXELS 

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 




Table 7-7. Programmable Fields in Bypass Mode (continued) 

Name Register Description 

VFP DSS.DISPC_TIMING_V[19:8] VFP bit field value Vertical front porch 

VSW DSS.DISPC_TIMING_V[7:0] VSW bit field value + 1 Vertical synchronization pulse width 

ONOFF DSS.DISPC_POL_FREQ[17] ONOFF bit DISPC_HSYNC and DISPC_VSYNC pixel clock 

control 

RF DSS.DISPC_POL_FREQ[16] RF bit DISPC_HSYNC and DISPC_VSYNC pixel clock 

edge control 

IEO DSS.DISPC_POL_FREQ[15] IEO bit Invert DISPC_ACBIAS 

IPC DSS.DISPC_POL_FREQ[14] IPC bit Invert DISPC_PCLK 

IHS DSS.DISPC_POL_FREQ[13] IHS bit Invert DISPC_HSYNC 

IVS DSS.DISPC_POL_FREQ[12] IVS bit Invert DISPC_VSYNC 

• Active matrix timing configuration 1 

– DSS.DISPC_POL_FREQ[17] ONOFF bit = 0 

– DSS.DISPC_POL_FREQ[16] RF bit = 0 

The DISPC_HSYNC and DISPC_VSYNC signals are driven on the opposite edge of DISPC_PCLK 

from the pixel data. 

– DSS.DISPC_POL_FREQ[15] IEO = 0 

The DISPC_ACBIAS signal is active high. 

– DSS.DISPC_POL_FREQ[14] IPC = 0 

The pixel data are driven on the rising edge of DISPC_PCLK. 

– DSS.DISPC_POL_FREQ[13] IHS = 0 

The DISPC_HSYNC signal is active high. 

– DSS.DISPC_POL_FREQ[12] IVS = 0 

The DISPC_VSYNC signal is active high. 

Figure 7-17. Active Matrix Timing Diagram of Configuration 1 (Start of Frame) 

Figure 7-18. Active Matrix Timing Diagram of Configuration 1 (Between Lines) 

HSW HBP HFP HSW HBP 

PIXELS 

PIXELS 



dss-015 

dss-016

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC* 

DISPC_HSYNC* 

DISPC_ACBIAS* 


* Active Low signals 

HFP 

HSW 

VFP VSW 

HBP 

PIXELS PIXELS 

HSW 



Figure 7-19. Active Matrix Timing Diagram of Configuration 1 (Between Frames) 

Figure 7-20. Active Matrix Timing Diagram of Configuration 1 (End of Frame) 


PIXELS 

VBP 

HSW 

VFP 

HSW HBP 

HSW HSW 



The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK. 


The DISPC_ACBIAS signal is active low. 


The pixel data is driven on the falling edge of DISPC_PCLK. 


The DISPC_HSYNC signal is active low. 


The DISPC_VSYNC signal is active low. 


VSW VBP 

HBP 

dss-017 

dss-018 

PIXELS 



dss-019 

1563

DISPC_PCLK 

DISPC_VSYNC* 

DISPC_HSYNC* 

DISPC_ACBIAS* 


*Active-low signals 

DISPC_PCLK 

DISPC_VSYNC* 

DISPC_HSYNC* 

DISPC_ACBIAS* 


*Active Low signals 

DISPC_PCLK 

DISPC_VSYNC* 

DISPC_HSYNC* 

DISPC_ACBIAS* 


* Active Low signals 


HFP 




HSW 

Pixels Pixels 


VFP VSW 

VBP 

HSW 

HBP 

PIXELS PIXELS 



HSW HBP 

HSW HSW 

PIXELS 



The DISPC_HSYNC and DISPC_VSYNC signals are driven on the rising edge of DISPC_PCLK. 











VFP 

dss-020 

dss-021 

dss-022

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 




HFP 




HSW 

VFP 

PIXELS 


PIXELS PIXELS 


VSW 

HSW 

VBP 

HBP 

PIXELS PIXELS 


• Passive matrix timing configuration 

HSW HBP 

HSW 

PIXELS 



The DISPC_HSYNC and DISPC_VSYNC signals are driven on the opposite edge of DISPC_PCLK 

from the pixel data. 




VFP 

HSW 

dss-023 

dss-024 

dss-025 

dss-026 

1565

DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


DISPC_PCLK 

DISPC_VSYNC 

DISPC_HSYNC 

DISPC_ACBIAS 


PIXELS 

HSW 

VSW 

PIXELS 

HFP HSW HBP 

HFP HSW 

PIXELS 

PIXELS 


HFP VFP VSW VBP 

HSW 










7.2.1.2 DSI Serial Interface 

Figure 7-29. Passive Matrix Timing Diagram (Start of Frame) 

Figure 7-30. Passive Matrix Timing Diagram (Between Lines) 

Figure 7-31. Passive Matrix Timing Diagram (Between Frames) 

PIXELS 

HBP 

Figure 7-32. Passive Matrix Timing Diagram (End of Frame) 

VFP 

HSW HBP 

HSW HSW 

PIXELS 

PIXELS 

Figure 7-33 shows a typical connection between the DSI modules and a compliant panel display. 



dss-027 

dss-028 

dss-029 

dss-030



controller 

DSI protocol 

engine and 

DSI complex 

I/O 

DSI_DX0 dss_data0 

DSI_DY0 

DSI_DX1 

DSI_DY1 

DSI_DX2 

DSI_DY2 

VDDA_DSI 

(supply) 

VSSA_DSI 

(ground) 



Figure 7-33. Typical DSI Connection 

vss 

dss_data1 

dss_data2 

dss_data3 

dss_data4 

dss_data5 

vdda_dsi 

vssa_dsi 

Digital ground 

NOTE: The DSI pins are multiplexed in mode 1 with some LCD parallel pins. See Chapter 13, 

System Control Module, for more details on pad multiplexing. 

7.2.2 LCD Support With MIPI DSI 1.0 Protocol and Data Format 

This section summarizes the MIPI® DSI1.0 protocol and data format. 

NOTE: Copyright ©2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member 

Confidential. 

7.2.2.1 Physical Layer 

Table 7-8 lists the DSI interface I/O. 

(1) 

Table 7-8. I/O Description for DSI Serial Interface 

Signal Name I/O (1) Description Value at Reset 

LCD panel DSI 

Power IC 

dsi_dx0 line 1 I/O Serial data/clock input/output N/A 

dsi_dy0 


dsi_dy1 


dsi_dy2 

I/O = Input/Output 



dss-194



NOTE: Each serial line (line 1, line 2, and line 3) can be used as clock lane or data lane. All 

polarities are supported. The MIPI DSI 1.0 protocol requires at least one clock line and one 

data lane. 

Lanes support four operating modes: 

• HS mode: High-speed transmit mode 

• LP mode: Low-power transmit mode (also called low-power state [LPS]) 

• ULPS: Ultra-low power state used between two transmissions 

• Off mode: Lane is off. 

7.2.2.1.1 Data/Clock Configuration 

From the device point of view, the DSI interface consists of six input/output signals representing three 

differential signals: The serial clock and one or two serial data. The minimum configuration is one data pair 

and one clock pair. 

• The data signal carries the bit-serial data. The DSI transmitter in the host sends the data in-quadrature 

with the DDR clock in high speed mode; otherwise, the clock is extracted from the received data in 

low-speed mode. The data is transmitted byte-wise least significant bit (LSB) first. 

• The clock signal carries the DDR clock signal in high speed transmission. 

• Software users must configure the order of the data lanes to indicate the byte order while splitting the 

byte stream for each DSI_PHY into bytes. 

Table 7-9 details all the DSI lanes configuration. 

Table 7-9. DSI Lane Configuration 

DSI DSI_PHY Lane 

Data/Clock Lane Position 

Configuration 1 2 3 

Description 

Mode CLK + DATA1 CLK DATA1 Not used Single data lane 

Mode CLK + DATA1 + 

DATA2 

CLK Not used DATA1 

DATA1 CLK Not used 

Not used CLK DATA1 

DATA1 Not used CLK 

Not used DATA1 CLK 

CLK DATA1 DATA2 Two data lanes 

CLK DATA2 DATA1 

DATA1 CLK DATA2 

DATA2 CLK DATA1 

DATA1 DATA2 CLK 

DATA2 DATA1 CLK 





NOTE: 

7.2.2.1.2 ULPS 

• The byte on Dn is sent before the byte on Dn+1, all the combinations of data and clock 

are supported through programming of the DSS.DSI_COMPLEXIO_CFG1 register. The 

CLOCK_POSITION and CLOCK_POL bit fields configure which lane transmits the clock 

and define its polarity. Four bit fields (DATA1_POSITION, DATA1_POL, 

DATA2_POSITION, and DATA2_POL) configure the data lanes and their polarity. The 

DATA2_POSITION bit field can be set to 0; in this case, only the data lane defined in 

the DATA1_POSITION bit field is used, and data is transmitted on only one clock lane 

and one data lane. 

• The configuration of the DSI complex I/O (number of data lanes, position, differential 

order) must not be changed while DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE bit is set 

to 1. For the hardware to recognize a new configuration of the complex I/O (done in 

DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow this sequence: 

First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next reset the DSS.DSI_CTRL[0] IF_EN 

to 0, then set DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1, and finally, set again the 

DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the DSI complex I/O 

configuration is undetermined. 

• Only DATA1 is bidirectional in command mode. The low-power received information is 

always sent by the display panel using DATA1. Since any lane of the DSI complex I/O 

can be configured as data lane DATA1, all lanes of the complex I/O are bidirectional 

Each lane can be put in ultra-low power state (ULPS) by software configuration. The ULPS mode requires 

all the following conditions: 

• The lane must be in stop state. 

• For data lanes, no data must be pending in the DSI module. 

• For data lane 1, no BTA should have been sent. The DSI module should have control of the bus. 

The control of each lane is independently controlled by the DSS.DSI_COMPLEXIO_CFG2 register. 

7.2.2.2 Video Port (VP) Interface 

NOTE: The signals described in this section are internal and not bounded outside the device. This 

section aims at helping software users understand the internal connections between the 

display controller (DISPC) and the DSI protocol engine. 

Table 7-10 summarizes the video interface signals. This interface is used to connect the display controller 

to the DSI protocol engine to send real time data streams. Note that only the active matrix timings are 

supported by DSI protocol engine. The HSYNC/VSYNC/DE/DATA signals are driven on the rising or 

falling edge of the pixel clock (VP_PCLK). 


Table 7-10. Video Interface for DSI Protocol Engine 

VP_HSYNC I Horizontal sync signal 

VP_VSYNC I Vertical sync signal 

VP_DATA[23:0] I Parallel output data: Bits 0 to 23 

VP_PCLK I Pixel clock. In case of STALL configuration, it is used to indicate when new data 

is on the data bus during the clock period of VP_CLK. The VP_PCLK is 

generated from VP_CLK through division. The clock ratio is defined in the 

DSS.DSI_CTRL[4] VP_CLK_RATIO bit and must be aligned with the 

configuration of the clock divisor in the display controller 

(DSS.DISPC_DIVISOR[7:0] PCD bit field). 

VP_DE I Data enable 

(1) 

I = Input, O = Output 





Signal Name Type (1) 

Table 7-10. Video Interface for DSI Protocol Engine (continued) 

Description 

VP_STALL O The stall signal must be deasserted to receive pixel and asserted to stop 

receiving pixel. (It can be used only while the display controller is configured in 

STALL mode; in that mode, HSYNC and VSYNC are not generated). 

VP_CLK I Display controller internal clock. It is a free-running clock. 

NOTE: 

• The polarities of VP_HSYNC and VP_VSYNC are programmable by setting the 

DSS.DSI_CTRL register. 

• The maximum frequency for VP_CLK is 173 MHz at nominal voltage, and 96 MHz at low 

voltage. 

• Clocks VP_CLK and VP_PCLK can have the same frequency. 

• The number of bits to be captured on the video port is defined in the 

DSS.DSI_CTRL[7:6] VP_DATA_BUS_WIDTH bit field. 

• VP_DE is connected to the dss_acbias signal in the display controller, and its polarity 

can be controlled by setting the DISPC_POL_FREQ[15] IEO bit. 

The data received on the video port can be stored into the line buffer memories or sent directly on the DSI 

interface in two cases: 

• The line buffer size is too small compared to the line from the display controller. 

• There is no line buffer instantiated. If there is no line buffer, the burst mode, defined as frequency burst 

mode, cannot be used. Only the transparency burst mode is supported. 

NOTE: The DSS.DSI_CTRL[13:12] LINE_BUFFER bit field defines the number of lines to be used 

for transferring data from the video port to the DSI link. 

7.2.2.2.1 Video Port Used for Video Mode 

If the video port is used for video mode, the VP_STALL is not used. Table 7-11 lists the active signals on 

the video port. 

Table 7-11. Video Interface in the Context of Video Mode 


VP_HSYNC I Horizontal sync signal 

VP_VSYNC I Vertical sync signal 

VP_DATA[23:0] I Parallel output data: bits 0 to 23 

VP_PCLK I Pixel clock. 

VP_DE I Data enable 

VP_CLK I It is a free running clock used as the display controller functional clock. The 

maximum frequency is 173 MHz at nominal voltage, and 96 MHz at low voltage. 


Three video modes are available: 

• No line buffer: The data received on the video port are directly output of the DSI port without buffering. 

The ration of VP_CLK and the DSI high-speed (HS) clock period must ensure identical throughput on 

the two ports (the two clocks must be generated using the same PLL; the subsystem must provide 

such configuration). 

• One line buffer: 

– The data are first stored in the line buffer; once all the data for one line are received, the DSI 

protocol engine sends the whole line. The software must adjust timings to allow for the storage of 

all line data into the line buffer before sending to DSI outputs. The synchronization packets are 

never stored into the line buffer. 

• Two line buffers: 





– One line is stored when the second line is output on the DSI port. It allows burst capability. While 

receiving the first line of the frame, there is no RGB packets sent because the line buffers are 

empty. To send the last line of the frame, a dummy line must be provided by the display controller 

to flush the line buffers. The synchronization packets are never stored into the line buffer. 

NOTE: If more active lines are received on the video port than the number defined in the 

DSS.DSI_VM_TIMING3[15:0] VACT bit field, the extra lines are discarded by the DSI 

protocol engine. These lines are treated as blanking lines. 

Figure 7-34, Figure 7-35, and Figure 7-36 show these three video modes. 



1571

VP waveforms: 

DSI waveform: 

t L 

V 

S BL 

LP H S BL 

LP 

H 

S 

H SA 

... 

PCLK 

VSYNC 

HSYNC 

DE 

DATA[23:0] PIXELS 

V 

E BL 

LP H S BL 

LP 

H 

H 

E 

B 

P 

PCLK 

VSYNC 

HSYNC 

DE 

DATA[23:0] 

PCLK 

VSYNC 

HSYNC 

DE 


Active matrix timing – Start of frame ( (first one) ) 

... 

H 

S BL 

LP 

RGB HFP 


Active matrix timing – Between lines 

DATA[23:0] PIXELS PIXELS 

PCLK 

VSYNC 

HSYNC 

DE 

HFP 

HSW 

VFP VSW 


t L t L t L 

Not used for the first frame 

... 

Active video area 

H 

S 

H 

S 

A 

H 

H 

E 

BP 

H 

S BL 

LP 

... 

RGB HFP 

H 

S BL 

LP 

VSA lines VBP lines VFP lines 

t L 



Figure 7-34. DSI Video Mode Without Burst (No-Line Buffer) 

PIXELS PIXELS 

VACT lines 

VBP 

HSWHBP 

Active matrix timing – Between frames 

VFP 

HSW HBP 

HSW HSW 

Active matrix timing – End of the frame (last one) 

*(VSA + VBP + VACT + VFP) 

t L t L t L 



B 

H LL 

S 

P 

L 

V 

P 

M 

S 

dss-136

VP waveforms: 

DSI waveform: 

V 

S 

tL 

BL 

LP 

H 

S 

tL 

BL 

LP 

H 

S 

H 

S 

A 

... 

V 

E 

H 

E 

PCLK 

VSYNC 

HSYNC 

DE 


PCLK 

VSYNC 

HSYNC 

tL 

DE 

DATA[23:0] 

PCLK 

VSYNC 

HSYNC 


DE 

BL 

LP 

H 

S 

tL 

tL 

BL 

LP 


... 

H 

S 

tL 

BL 

LP 

RGB HFP 

Active matrix timing – Start of the frame (firts one) 


Active matrix timing – between lines 


PCLK 

VSYNC 

HSYNC 

DE 

HFP 

HSW 

VFP VSW 


Active matrix timing – between frames 

Active matrix timing – End of the frame (last one) 

tL * (VSA + VBP + VACT + VFP) 

... 



HBP 

Extended HBP due to 

buffering 



Figure 7-35. DSI Video Mode Without Burst (One-Line Buffer) 

VACT lines 

PIXELS PIXELS 

H 

S 

H 

S 

A 

H 

E 

VBP 

HSWHBP 

HSW HBP 

HSW HSW 

Reduced HFP due to buffering 

VFP 

H 

S 

tL 

BL 

LP 

... 

RGB HFP 


HBP 


H 

S 

tL 

BL 

LP 

Buffer 

H 

S 

tL 

B 

L 

L 

P 

L 

V 

P 

S 

M 

dss-137 

1573

VP waveforms: 

Dummy line 

(not stored in the buffer ) 

DSI waveform: 

V 

S 

t L 

BL 

LP 

H 

S 

BL 

LP 

H 

S 

H 

S 

A 

... 

V 

E 

H 

E 

PCLK 

VSYNC 

HSYNC 

DE 


PCLK 

VSYNC 

HSYNC 

H 

B 

P 

DE 

DATA[23:0] 

PCLK 

VSYNC 

HSYNC 

DE 

BL 

LP 

H 

S 

BL 

LP 


... 

H 

S 

RGB HFP 

Active matrix timing – Start of the frame (first one) 


BL 

LP 

Active matrix timing – Between lines 


PCLK 

VSYNC 

HSYNC 


DE 

HFP 

HSW 

VFP VSW 


t L t L t L t L 

Active matrix timing – Between frames 

Active Matrix Timing – End of the frame (last one) 

t L* (VSA + VBP + VACT + VFP) 

... 



t L 



Figure 7-36. DSI Video Mode With Burst (Two-Line Buffers) 

VACT lines 

PIXELS PIXELS 

H 

S 

H 

S 

A 

VBP 

H 

H 

B 

E 

P 

HSWHBP 

VFP 

HSW HBP 

HSW HSW 

H 

S 

t L 

BL 

LP 

RGB HFP 



... 

H 

S 

tL 

BL 

LP 

H 

S 

Buffer 1 

Buffer 2 

tL 

B 

L 

L 

P 

L 

V 

P 

S 

M 

dss-138



NOTE: In Figure 7-34, Figure 7-35, and Figure 7-36: 

• When HSync start and Hsync end short packets are not generated (HSA does not exist), 

HBP signal must be different from 0. 

• The software must ensure that VBP is always defined so that there is at least one 

HSYNC during VBP. 

• In blanking low-power mode (BL-LP), two options are possible 

– The lane remains in ULPS, and the DSI_CTRL[20] BLANKING_MODE bit is set to 

0x0. 

– Dummy bytes are sent during LP with the DSI_CTRL[20] BLANKING_MODE bit set 

to 0x1; the number of sent bytes is determined by the DSI_VM_TIMING6[15:0] 

BL_LP_INTERLEAVING bit field. 

If the signal VP_DE is not asserted during enough VP_PCLK cycles to be able to capture the number of 

bytes defined in the word count of the header, the module must send the valid data received on the video 

port followed by bytes of 0s to match the required number of bytes to transmit. The VP_PCLK must be 

present during all extra cycles where the DSI protocol engine is expecting pixels. 

If the VP_DE signal is asserted for too many VP_PCLK cycles, the module should stop capturing the data 

on the video port while the number of bytes to capture, as defined in the word count field of the header, is 

reached. 

The HS must check that the received synchronization events on the video port (VSYNC and HSYNC) are 

within the synchronization window based on expected timings. If the timings (internal and received) are 

out of sync, the interrupt for out-of-sync must be generated and the interface must be disabled 

(DSS.DSI_CTRL[0] IF_EN bit is automatically reset by hardware). The unsynchronization window is 

defined by the DSS.DSI_VM_TIMING2[27:24] WINDOW_SYNC bit field. 

7.2.2.2.2 Video Port Used on Command Mode 

If the video port is used for command mode, the VP_HSYNC, VP_VSYNC, and VP_DE signals are not 

used. Table 7-12 describes the active signals on the video port. 

Table 7-12. Video Interface in the Context of Command Mode 


VP_DATA[23:0] I Parallel output data: bits 0 to 23 

VP_PCLK I One pulse is generated every time new data is output on the data bus 

VP_STALL O The stall signal must be deasserted to receive pixel and asserted to stop 

receiving pixel. (It can be used only while the display controller is configured in 

STALL mode; in that mode, HSYNC and VSYNC are not generated). 

VP_CLK I Display controller internal clock: It is a free running clock used as the display 

controller functional clock. The maximum frequency is 173 MHz at nominal 

voltage and 96 MHz at low voltage. 


NOTE: The stall signal must be deasserted to receive pixels and asserted to stop receiving pixels. 

Figure 7-37 and Figure 7-38 show the VP_STALL signal assertion and deassertion on rising and falling 

edges, respectively. 

NOTE: In DSI command mode, the display controller must be configured in stall mode by setting 

the DSS.DISPC_CONTROL[11] STALLMODE bit to 1. 



1575

VP_CLK 

VP_PCLK 

VP_STALL 

VP_DATA[23:0] 

VP_CLK 

VP_PCLK 

VP_STALL 

VP_DATA[23:0] 



Figure 7-37. Stall Timing With Pixel on Rising Edge 

ALWAYS_1_period_of_VP.CLK 

4_VP.CLK_cycles_for_assertion 

PIXELS #1 PIXELS #2 PIXELS #3 PIXELS #4 PIXELS #5 

ALWAYS_1_period_of_VP.CLK 


PIXELS #1 PIXELS #2 PIXELS #3 PIXELS #4 PIXELS #5 

1_VP.CLK_cycles_after_rising_edge_pclk 

Figure 7-38. Stall Timing With Pixel on Falling Edge 

dss-187 

1_VP.CLK_cycles_after_for_de-assertion 

To stop the transfer, the VP_STALL signal must be asserted when the last data is output. The data can be 

output on the rising or falling edge of the VP_PCLK through registers in the display controller module. The 

case with data output on falling edge of VP_PCLK is supported by the DSI protocol engine. 

The VP_PCLK clock is generated from VP_CLK; these two clocks are balanced. Assertion and 

deassertion of VP_PCLK is done on the rising edge of VP_CLK. The width of the VP_PCLK pulse 

depends on the configuration of the clock divisor in the display controller (DSS.DISPC_DIVISOR[7:0] PCD 

bit field). In the DSI protocol engine, the information is defined in the DSS.DSI_CTRL[4] VP_CLK_RATIO 

bit and must be aligned with the display controller configuration. 

Deassertion of the VP_STALL signal must occur at least 4 VP_CLK cycles before assertion of VP_PCLK. 

Assertion of VP_STALL must occur one cycle VP_CLK after deassertion of VP_PCLK for the last pixel to 

be transferred. The VP_CLK clock is generated by the display controller under software control. It can be 

kept running between assertion and deassertion of VP_STALL. 

The word count (WC) defined in the DSS.DSI_VCn_LONG_PACKET_HEADER register for the virtual 

channel (VC)associated with the video port, indicates the number of bytes to receive (one line or two lines 

can be used, depending on the WC and size of the line buffer). The total size defined in the WC of the 

header register cannot exceed the size of the line buffer multiplied by the number of buffer lines. 

The stall assertion/deassertion depends on the number of bytes to be received considering the size of the 

video port bus defined in the DSS.DSI_CTRL[7:6] VP_DATA_BUS_WIDTH bit field. 

Figure 7-39 shows the data flow in command mode using the video port. 



dss-188

VP_CLK 

VP_PCLK 

VP_STALL 

VP_DATA[23:0] 

DSI link 

ALWAYS_1_period_of_VP.CLK ALWAYS_1_period_of_VP.CLK 


1_VP.CLK_cycles_after_risir 


PIXELS #1 PIXELS #2 PIXELS #3 PIXELS #4 PIXELS #5 PIXELS #1 PIXELS #2 PIXELS #3 PIXELS #4 PIXELS #5 

RGB HS 

or 

LP 

Buffer Buffer 

Start as soon 

as last data is 

received in the 

buffer 



Figure 7-39. Data Flow in Command Mode Using the Video Port 

Two command modes are available: 

RGB HS 

... or 

LP 

... 

Start as soon 

as last data is 

received in the 

buffer 

HS 

or 

LP 

HS packet, LP 

packet, or LP 

with no data 

• One line buffer: The data are stored in the line buffer before being sent. 

• Two line buffers: The two lines are used if the word count defined in the 

DSS.DSI_VCn_LONG_PACKET_HEADER register is bigger than the line size; otherwise, one line 

buffer is used. 

NOTE: In command mode, the video port can only be used in one or two line buffer configuration. 

The no-line buffer configuration is not allowed. 

The packets can be sent using high-speed or low-speed. 

NOTE: The DCS command in the payload can be inserted automatically using the DSI_CTRL[24] 

DCS_CMD_ENABLE bit. If TE is used, hardware automatically inserts the DCS Write Start 

command for the first packet of the frame transfer and the DCS Write Continue command for 

all subsequent packets. 

7.2.2.2.3 Burst Mode 

When the burst mode is enabled, the video port receives data from the display controller at the pixel clock. 

The DSI protocol engine buffers the data in its own line FIFO (double-line buffer of 1024 x 24-bit pixels 

maximum). The read speed of the line can be twice the pixel clock to increase the blanking time of the 

video mode and to allow command mode traffic to be interleaved during the blanking period. The burst 

mode uses a dual-line buffer. 

The DSI port can output data from one line buffer while the second one is accessed by the video port. The 

two processes are concurrent but they do not access the same line at the same time. The DSI transfer 

can start only when the whole video port line is transferred into a line buffer. The switch is controlled by 

the VP_HS signal on the video port side and by internal signal on the DSI port indicating that the last data 

for the current line has been written into the line buffer. 

NOTE: The line buffers are used to store the pixels only. The synchronization codes are not stored 

in the line buffers. They must be sent according to the video port timings. 



dss-139 

1577

Data 

lane 1 

All data lanes finish at the same time. 

LPS SoT Byte 0 Byte 2 Byte 5 Byte N-6 Byte N-4 Byte N-2 EoT LPS 

Data 

lane 2 


The number of bytes, N, is not an integer multiple of the number of lanes (2). 

Data 

lane 1 

Data lane 2 finishes 1 byte earlier than lane 1. 


Data 

lane 2 

LPS SoT Byte 1 Byte 3 Byte 4 Byte N-4 Byte N-2 EoT LPS 

Key: 

LPS: Low-power state 

SoT: Start of transmission 

EoT: End of transmission 

Data 

lane 1 


Key: 






7.2.2.3 Multilane Layer 

Peripherals do not typically have high bandwidth requirements for returning data to the host processor. To 

keep designs simple and improve interoperability, all DSI-compliant systems must use only Lane 1 in LP 

mode for returning data from a peripheral to the host processor. 

7.2.2.3.1 SoT and EoT in Multilane Configurations 

Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple 

of the number of lanes, some lanes may run out of data before others. Therefore, the lane management 

layer, as it buffers up the final set of less-than-N bytes, deasserts its valid data signal into all lanes for 

which there is no further data. Although all lanes start simultaneously with parallel SoTs, each lane 

operates independently and may complete the HS transmission before the other lanes, sending an EoT 

one cycle (byte) earlier. 

7.2.2.3.2 Lane Splitter 

The lane splitter can split the byte stream into 2 lanes (for 1 lane, the splitter is bypassed). Figure 7-40 

and Figure 7-41 show the byte position into each serial link for 1 and 2 data lane configurations. The byte 

stream always starts from lane 1. It finishes on one of the lanes, depending on the number of bytes to 

send and the number of lanes. The splitter module is only used when packets are sent using high-speed 

mode (HS). In low-power mode (LP), only one data lane is used (Lane 1). 

Figure 7-40. Two Data Lane Configuration 

Figure 7-41. One Data Lane Configuration 



dss-140 

dss-329

Data LPS 

lane 1: 

Data LPS 

lane 2: 

Key: 




Data lane 2 finishes 1 byte earlier than data lane 1. 

SoT Byte 0 Byte 2 

Byte N-1 Byte M-3 Byte M-1 EoT 

SoT Byte 1 Byte 3 

Byte 0 Byte M-2 EoT LPS 

Short 

packet 

Long 

packet 

Long 

packet 

LPS LPS LPS LPS 

LPS 

ST SP ET ST PH Data PF ET ST PH Data PF ET ST SP ET 

Key: 



In case of back-to-back packets, the byte stream is considered as a single packet by the splitter module. 

Figure 7-42 shows the example of two packets sent back to back. N bytes for the first packet and M bytes 

for the second one. 

7.2.2.4 Protocol Layer 

Figure 7-42. Two Packets Using Two-Data Lane Configuration (Example) 

The low level protocol (LLP) is a byte-oriented protocol. It supports short and long packet formats. The 

DSI protocol layer defines how the display data is transported onto the physical layer. Packets can be sent 

using high-speed or low-speed mode. LLP is selected through DSI registers. The features of the DSI 

protocol layer are: 

• Transport of arbitrary data (payload independent) 

• 8-bit word size 

• Support for up to four interleaved VCs on the same link 

• Special packets for frame start, frame end, line start, and line end information 

• Descriptor for the type, pixel depth, and format of application-specific payload data 

• ECC for 1-bit or 2-bit error detection in the header 

• 16-bit checksum code for error detection 

Figure 7-43 shows the protocol layer with short and long packets. 

7.2.2.4.1 Short Packet 

Figure 7-43. Protocol Layer With Short and Long Packets 

ST: Start of transmission ET: End of transmission 

PH: Packet header PF: Packet footer 

LPS: Low-power state SP: Short packet 

Short 

packet 

Figure 7-44 shows the structure of the short packet. A short packet must contain an 8-bit data ID followed 

by two command or data bytes and an 8-bit ECC; a packet footer must not be present. Short packets must 

be 4 bytes in length. The ECC byte allows correction of single-bit errors and detection of 2-bit errors in the 

short packet. 



dss-143 

LPS 

dss-142 

1579

Data ID 

Word count 

(WC) 

32-bit 

packet 

header 

(PH) 

ECC 

Data ID 

Short packet 

data field 

ECC 

32-bit short packet (SP) 

Data type (DT) = 0x01 – 0x37 

Data 0 



Figure 7-44. Short Packet Structure 

dss-144 

NOTE: The short packets can be sent in low-power mode or in high-speed mode. 

7.2.2.4.2 Long Packet 

Figure 7-45 shows the structure of the low-level protocol long packet. A long packet must consist of three 

elements: A 32-bit packet header (PH), an application-specific data payload with a variable number of 

bytes, and a 16-bit packet footer (PF). The packet header is further composed of three elements: An 8-bit 

data identifier, a 16-bit word count, and 8-bit ECC. The packet footer has one element, a 16-bit checksum. 

Long packets can be from 6 to 65,541 bytes in length. 

Figure 7-45. Long Packet Structure 

Data 1 

Data 2 

Data WC-3 

Data WC-2 

Packet data: 

Length = word count (WC) * data word 

width (8 bits). There are no restrictions 

on the values of the data words. 

Data WC-1 

16-bit 

checksum 

16-bit 

packet 

footer 

(PF) 

• The data identifier defines the VC for the data and the DT for the application-specific payload data. 

• The word count defines the number of bytes in the data payload between the end of the packet header 

and the start of the packet footer. Neither the packet header nor the packet footer must be included in 

the word count. 

• The ECC byte allows single-bit errors to be corrected and 2-bit errors to be detected in the packet 

header. This includes the data identifier and the word count fields. 

After the end of the packet header, the receiver reads the next word count * bytes of the data payload. 

There are no limitations on the value of a data word within the data payload block, that is, no embedded 

codes are used. Once the receiver has read the data payload, it reads the checksum in the packet footer. 

The host processor must always calculate and transmit a checksum in the packet footer. Peripherals are 

not required to calculate a checksum. Also note the special case of zero-byte data payload: If the payload 

has length 0, then the checksum calculation results in (0xFFFF). If the checksum is not calculated, the 

packet footer must consist of 2 bytes of all zeros (0x0000). In the generic case, the length of the data 

payload must be a multiple of bytes. In addition, each data format may impose additional restrictions on 

the length of the payload data, that is, multiple of 4 bytes. Each byte is transmitted LSB first. Payload data 

may be transmitted in any byte order, restricted only by data format requirements. Multibyte elements 

such as word count and checksum must be transmitted least-significant byte first. 

NOTE: The long packets can be sent in low-power mode or high-speed mode. 



dss-145

Data in 

B7 

B6 

B5 

B4 

B3 

VC DT 

Virtual channel 

(VC) 

Channel 

detect 



7.2.2.4.3 Data Identifier 

The data identifier byte contains the virtual VC ID value and the DT value, as shown in Figure 7-46. The 

VC ID is contained in the 2 MSBs of the data identifier byte. The DT value is contained in the 6 LSBs of 

the data identifier byte. DI[7:6]: These 2 bits identify the data as directed to one of four VCs. DI[5:0]: 

These six bits specify the DT. 

7.2.2.4.4 Virtual Channel ID - VC Field, DI[7:6] 

Figure 7-46. Data Identifier Structure 

Data identifier (DI) byte 

B2 

Data type 

(DT) 

The host can service up to four peripherals with tagged commands or blocks of data using the VC ID field 

of the header for packets targeted at different peripherals. The VC ID enables one serial stream to service 

two or more virtual peripherals by multiplexing packets onto a common transmission channel. Note that 

each packet sent in a single transmission have its own VC assignment and can be directed to different 

peripherals. The VC ID is defined in the DSS.DSI_VCn_SHORT_PACKET_HEADER and 

DSS.DSI_VCn_LONG_PACKET_HEADER registers for short and long packets, respectively. It should not 

be modified by hardware. There is one set of registers for each VC. Each set of registers defines the 

characteristics of the traffic between the host and the display associated with the VC. 

Figure 7-47 shows the VC controller. 

7.2.2.4.5 Data Type Field DT[5:0] 

Virtual channel control 

B1 

B0 

dss-146 

Figure 7-47. Virtual Channel Controller 

Channel identifier Channel configuration 

Channel 0 

Channel 1 

Channel 2 

Channel 3 

The DT field specifies whether the packet is a long or short packet type and the packet format. The DT 

field, along with the word count field for long packets, informs the receiver on how many bytes to expect in 

the remainder of the packet. This is necessary because there are no special packet start/end sync codes 

to indicate the beginning and end of a packet. This permits packets to convey arbitrary data, but it also 

requires the packet header to explicitly specify the size of the packet. 

7.2.2.4.6 Pixel Data Formats in Video Mode 

The host can send different pixel formats in video mode. Table 7-13 summarizes the pixel formats 

supported by the DSI interface in video mode. 



dss-147 

1581



Table 7-13. Pixel Data Format in Video Mode 

Mode Description 

RGB888 (using 24-bit container) RGB888 


RGB666 (18-bit packet using 18-bit container) RGB666_PACKET 

7.2.2.4.7 Synchronization Codes 


Each frame can be identified by two synchronization codes: One for the start of vertical synchronization 

pulse (VSSC) and one for the end of the vertical synchronization pulse (VSEC). Each line can be identified 

by two synchronization codes: One for the start of horizontal synchronization pulse (HSSC) and one for 

the end of the horizontal synchronization pulse (HSEC). The synchronization events may not be required 

by the display (peripheral): They are optional. Users can program which sync events are generated to the 

display from the timings received from the display controller in video mode. When data are received on the 

L4 interconnect slave port, the synchronization codes are not automatically generated by the protocol 

engine. They can be provided on the L4 interconnect port by writing to the registers with limited timing 

control. It is highly recommended to use the video port from the display controller to receive the 

synchronization events to automatically generate the short synchronization packets to the peripheral. 

When the DSI protocol engine detects that the VSYNC signal from the display controller transitions from 

inactive to active state, the VSSC short packet replaces the following HSSC corresponding to the following 

HSYNC synchronization short packet (if the generation is enabled). When the transition from active to 

inactive state is detected, the VSEC short packet is generated (if the generation is enabled) replacing the 

HSSC synchronization packet corresponding to the following HSYNC. When the DSI protocol engine 

detects that the HSYNC signal from the display controller transition from inactive to active state, the HSSC 

short packet is generated (if the generation is enabled). When the transition from active to inactive state is 

detected, the HSEC short packet is generated (if the generation is enabled). For the first frame, any 

HSYNC and data received on the video port before the first VSYNC should be ignored. Because the first 

VSYNC sent to the display is also recognized as a HSYNC for the first line, there should be no HSYNC 

sent for the first line. To send the synchronization codes, the DSI protocol engine uses the short packets. 

Table 7-14 summarizes the 6-bit DT synchronization code values. 

Table 7-14. Synchronization Codes 

Synchronization Code Value Comments 

V sync start code (VSSC) 0x1 Optional 

V sync end code (VSEC) 0x11 Optional 

H sync start code (HSSC) 0x21 Optional 

H sync end code (HSEC) 0x31 Optional 

7.2.2.4.8 Blanking 

To keep the DSI link in HS state while using the video mode, during blanking periods, the long blanking 

packets are sent to the display. The DSS.DSI_VM_TIMINGi (I between 1 and 7) registers define the size 

of the long blanking packets after: 

• Horizontal sync start code (short packet) 

• Horizontal sync end code (short packet) 

• Vertical sync start code (short packet) 

• Vertical sync end code (short packet) 

• Pixels (long packet) 

Table 7-15 defines the short packet values for the synchronization packets: 





Table 7-15. Sync Short Packet Values 

Virtual Sync Code Header Header (2nd Byte): Header (3rd Byte): Header (ECC) 

Channel ID (1st Byte) Data Field LSB Data Field MSB 

0x1 0x1 See note following this 

table 

0x0 0x11 0x11 

0x21 0x21 

0x31 0x31 

0x1 0x41 

0x1 0x11 0x51 

0x21 0x61 

0x31 0x91 0x0 0x0 

0x1 0x81 

0x2 0x11 0x81 

0x21 0xA1 

0x31 0xB1 

0x1 0xC1 

0x3 0x11 0xD1 

NOTE: 

0x21 0xC1 

0x31 0xF1 

• If the ECC is enabled by setting the DSS.DSI_VCn_CTRL[8] ECC_TX_EN bit to 1 for 

the VC in video mode, the ECC value is calculated; otherwise, 0x00 is used for the 

blanking long packets and sync short packets. If the CRC is enabled by setting the 

DSS.DSI_VCn_CTRL[7] CS_TX_EN bit to 1 for the VC in video mode, the check-sum 

value is calculated; otherwise, 0x00 is used for the blanking long packets. 

• In other cases, when the DSS.DSI_VCn_CTRL[7] CS_TX_EN bit is set to 0, the value 

0x00 is always used for the CRC (long packets). When the DSS.DSI_VCn_CTRL[8] 

ECC_TX_EN bit is set to 0, the value 0x00 is used for the ECC for short and long 

packets, except when the header is provided by the register, since the ECC field is 

available in the register. It can be used to generate invalid ECC values when the header 

is provided by the register. 

The link [lane(s) and clock separately] can be put in ULPS mode. While using the blanking values formerly 

defined, the packets (short and long) are considered in HS mode. 

Timing parameters VSA, VBP, VFP, HSA, HBP, HFP, VACT, and t L are defined in the 

DSS.DSI_VM_TIMINGx (x between 1 and 7) register. HSA, HBP, HFP, and t L are defined using the byte 

clock unit (TxByteClkHS) and also in low-power clock cycles (TxClkEsc). VSA, VBP, VFP, and VACT are 

defined in term of number of lines. When the HS blanking packets are sent during the blanking periods, 

the parameters are used to determine the blanking packet payload size (taking into account the 4-byte 

header and the 2-byte check sum). 

The configuration of the display controller timing generator must be used when the display controller 

timings are used to generate the DSI HS video mode transfer. 

Special care must be taken in the case of the last line of the frame. The LPS transition is required when 

the link is in HS mode for the whole frame. 

When BTA is sent for the data packets, the following blanking period cannot be used for sending any data 

from the TX FIFO. When the blanking period starts with one HS packet from one VC, it can only be 

followed by another HS packet from the same VC, or by trigger (BTA for example). When there is no more 

HS data to send for this VC, the lane is in LPS. When the blanking period starts with one LP packet from 

one VC, it can only be followed by another LP packet from the same VC, by another VC, by trigger (BTA 



1583

V 

S 

BL 

LP 

H 

S 

BL 

LP 

H 

S 

H 

S 

A 

... 

V 

E 

H 

E 

H 

B 

P 

BL 

LP 

H 

S 

BL 

LP 

... 

H 

S 

BL 

LP 

RGB HFP 

t L* (VSA + VBP + VACT + VFP) 

t L t L t L t L t L t L t L t L 



t L 



for example), or by extra LP NULL packets. If the trigger has been sent, it is not possible to send any 

more data. When there is no more data from the TX FIFO to send in LP mode or the trigger has been 

sent, the lane is put into LPS. If the lanes must be kept in HS mode during blanking periods (except for 

the last blanking period of the frame), the HS blanking packets must be used. In case one trigger is sent 

at the beginning of the blanking period, the rest of the blanking period is in ULPS. 

Figure 7-48 and Figure 7-49 show a nonburst transfer in DSI video mode with, and without VE and HE, 

respectively. 

Figure 7-48. DSI Video Mode: Nonburst Transfer With VE and HE 

... 

VACT lines 

H 

S 

H 

S 

A 

H 

E 

H 

B 

P 

H 

S 

BL 

LP 

... 

RGB HFP 



H 

S 

BL 

LP 

H 

S 

B 

L 

L 

P 

L 

P 

M 

V 

S 

dss-148

V 

S 

BL 

LP 

H 

S 

BL 

LP 

H 

S 

H 

B 

P 

... 

H 

S 

BL 

LP 

H 

S 

BL 

LP 

... 

H 

S 

BL 

LP 

RGB HFP 

t L* 

(VSA + VBP + VACT + VFP) 


VSA lines VBP lines 

t L 



Figure 7-49. DSI Video Mode: Nonburst Transfer Without VE and HE 

... 

VACT lines 


H 

S 

H 

B 

P 

H 

S 

BL 

LP 

... 

RGB HFP 

H 

S 

BL 

LP 

VFP lines 

NOTE: HSA timing is not used and does not have to be programmed when HE short packet is not 

generated. 



H 

S 

B LL 

P 

L 

P 

M 

V 

S 

dss-149 

1585

V 

S 

BL 

LP 

H 

S 

BL 

LP 

H 

S 

H 

B 

P 

... 

H 

S 

BL 

LP 

H 

S 

BL 

LP 

... 

H 

S 

BL 

LP 

BL 

RGB HFP 

LP 

t (VSA + VBP + VACT + VFP) 

L* 


VSA lines VBP lines 

t L 



Figure 7-50. DSI Video Mode: Burst Transfer Without VE and HE 

... 

VACT lines 


H 

S 

H 

B 

P 

H 

S 

BL 

LP 

BL 

RGB HFP 

LP 

... 

H 

S 

VFP lines 

NOTE: HSA timing is not used and does not have to be programmed when HE short packet is not 

generated. 

In Figure 7-49 and Figure 7-50, if HSync end short packet is not generated (HSA does not exist), HBP 

must be other than 0. 

7.2.2.4.9 Frame Structures 

Figure 7-51 shows the general DSI frame structure. 



BL 

LP 

H 

S 

B 

L 

L 

P 

L 

P 

M 

V 

S 

dss-150

Packet footer, PF 


Line blanking 

FE 

Line blanking 

FE 

FS 

FS 



Figure 7-51. DSI General Frame Structure 

Frame blanking 

Frame of pixels 




Data per line is a multiple of 8 bits. 

Key: 

PH – Packet header PF – Packet footer 

FS – Frame start FE – Frame end 

LS – Line start LE – Line end 

Figure 7-52 shows the general frame structure using burst mode. 

Packet header, PH 


Video mode 



dss-151 

1587



Line blanking 

FE 

Line blanking 

FE 



Figure 7-52. DSI General Frame Structure Using Burst Mode 


FS 





Key: 




FS 




Video mode 

Figure 7-53 shows the general frame structure using burst mode and interleaving. 



dss-152





FE 

FE 


Panel 2 


Panel 2 





Figure 7-53. DSi General Frame Structure Using Burst Mode and Interleaving 

Line blanking 

Line blanking 





Panel 1 


Key: 




FS 

FS 




Panel 1 

Video mode 

Command mode 



dss-153 

1589



7.2.2.4.10 Virtual Channels 

The DSI protocol layer transports VCs. The purpose of VCs is to separate different data flows, which are 

interleaved in a same data stream. Each VC is identified by a unique channel identification number in the 

packet header. The channel identification number is encoded in 2-bits. The DSI protocol engine 

determines the channel identifier number to be used for generating the packet header and multiplexes the 

interleaved data streams. The DSI protocol engine supports multiple concurrent VCs: Up to 4. Table 7-16 

summarizes the VC values used for each channel. 

Table 7-16. Virtual Channel Values 

Virtual Channel Number Value 

Virtual channel 0 0x0 




In the case of multiple displays connected to the single DSI port on the host, a hub may be used to root 

the data stream to the appropriate display based on the VC ID. Typically, VC ID 0x0 is used for the 

primary display and 0x1 for the secondary. The hub may have its own VC ID to provide communication 

capability between the host and the hub. 

7.2.2.5 Pixel Data Formats 

This section summarizes how the DSI supported pixel data formats in video mode are transmitted over the 

serial interface. For pixel formats in command mode. The DSI protocol engine can cope with all data 

formats given that the data line length sent through the DSI physical protocol is a multiple of a pixel. This 

condition is required for the DSI protocol engine to work properly. 

7.2.2.5.1 24 Bits per Pixel - RGB Color Format, Long Packet 

Figure 7-54 shows the RGB888 format. 



Virtual channel ID 

Data ID 

. . . 

Word count 

ECC 

0 

R 

0 

1 byte 1 byte 1 byte 

7 0 7 0 

R G G B 

8b 

7 0 

8b 

7 0 

8b 

Pixel 1 

1 byte 2 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 

Data type 



Figure 7-54. 24 Bits per Pixel RGB Color Format, Long Packet 

8b 8b 8b 8b 8b 8b 8b 8b 8b 

Pixel 1 Pixel 2 Pixel 3 

Packet header Variable size payload (first three pixels in 9 bytes) 

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 

8b 8b 8b 8b 8b 8b 8b 8b 8b 

Pixel n –2 Pixel n–1 Pixel n 

. . . 

Variable size payload (last three pixels packed in 9 bytes) 

7 

B 

7 

2 bytes 

Checksum 

Packet footer 

Packed pixel stream 24-bit format is a long packet used to transmit image data formatted as 24-bit pixels 

to a video mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a 

payload of length WC bytes, and a two-byte checksum. The pixel format is red (8 bits), green (8 bits), and 

blue (8 bits), in that order. Each color component occupies one byte in the pixel stream; no components 

are split across byte boundaries. Within a color component, the LSB is sent first, the MSB last. 

7.2.2.5.2 18 Bits per Pixel (Loosely Packed) - RGB Color Format, Long Packet 

Figure 7-55 details the RGB666 format. 



dss-154 

1591


1 byte 

Data type 

Data ID 

. . . 

2 bytes 

Word count 


ECC 

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 

6b 6b 6b 6b 6b 6b 6b 6b 6b 

Packet header Variable size payload (first three pixels in 9 bytes) 

1 byte 1 byte 


0 12 

7 0 12 7 0 12 

R R G G B 

0 

6b 

5 0 

6b 

5 0 

6b 

Pixel 1 



6b 6b 6b 6b 6b 6b 6b 6b 6b 

Pixel n– 2 

Pixel n– 1 



Figure 7-55. 18 Bits per Pixel (Loosely Packed) RGB Color Format, Long Packet 

. . . 

Variable size payload (last three pixels packed in 9 bytes) 

7 

B 

5 

Pixel n 

2 bytes 

Checksum 

Packet footer 

In the 18-bit pixel loosely-packed format, each R, G, or B color component is six bits but is shifted to the 

upper bits of the byte, such that the valid pixel bits occupy bits [7:2] of each byte. Bits [1:0] of each 

payload byte representing active pixels are ignored. As a result, each pixel requires three bytes as it is 

transmitted across the link. This requires more bandwidth than the packed format, but requires less 

shifting and multiplexing logic in the packing and unpacking functions on each end of the link. This format 

is used to transmit RGB image data formatted as pixels to a video mode display module that displays 

18-bit pixels. The packet consists of the DI byte, a two-byte WC, an ECC byte, a payload of length WC 

bytes, and a two-byte checksum. The pixel format is red (6 bits), green (6 bits), and blue (6 bits) in that 

order. Within a color component, the LSB is sent first, the MSB last. 

7.2.2.5.3 18 Bits per Pixel (Packed) - RGB Color Format, Long Packet 

Figure 7-56 details the RGB666_PACKED format. 



dss-155


1 byte 

Data type 

Data ID 

. . . 

2 bytes 

Word count 


ECC 

1 byte 1 byte 1 byte 1 byte 1 byte 1 byte 

6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 

Packet header Variable size payload (first four pixels packed in 9 bytes) 

1 byte 1 byte 

0 

R 

0 

1 byte 1 byte 

5 

R 

5 

6 7 0 

GG 

G 

0 1 2 


Pixel 4 


6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 

Pixel n– 3 

Pixel n– 2 

3 4 

G B 

5 0 

6b 6b 6b 

Pixel 1 



Figure 7-56. 18 Bits per Pixel (Packed) RGB Color Format, Long Packet 

7 0 1 

B B B 

3 4 5 

1 byte 

. . . 

Pixel n– 1 

Pixel n 

Variable size payload (last four pixels packed in 9 bytes) 

2 bytes 

Checksum 

Packet footer 

Packed pixel stream 18-bit format (packed) is a long packet. It is used to transmit RGB image data 

formatted as pixels to a video mode display module that displays 18-bit pixels The packet consists of the 

DI byte, a two-byte WC, an ECC byte, a payload of length WC bytes, and a two-byte checksum. Pixel 

format is red (6 bits), green (6 bits), and blue (6 bits), in that order. Within a color component, the LSB is 

sent first, the MSB last. With this format, it is strongly recommended that the total line width be a multiple 

of four pixels (nine bytes). 

7.2.2.5.4 16 Bits per Pixel - RGB Color Format, Long Packet 

Figure 7-57 details the RGB565 format. 



dss-156 

1593


1 byte 2 bytes 1 byte 1 byte 1 byte 1 byte 1 byte 2 bytes 

. . . 

Data type 

Data ID 

0 

R 

0 



Figure 7-57. 16 Bits per Pixel RGB Color Format, Long Packet 

1 byte 1 byte 

4 5 7 0 2 3 

R G G G G B 

5b 

4 0 2 3 

6b 

5 0 

5b 

Pixel 1 

5b 6b 5b 5b 6b 5b 

Word count ECC 

. . . Checksum 

Pixel 1 

Packet header Variable size payload 

7 

B 

4 

. . . 

Pixel n 

Checksum 

Packed pixel stream 16-bit format is a long packet used to transmit image data formatted as 16-bit pixels 

to a video mode display module. The packet consists of the DI byte, a two-byte WC, an ECC byte, a 

payload of length WC bytes, and a two-byte checksum. Pixel format is five bits red, six bits green, five bits 

blue, in that order. Note that the green component is split across two bytes. Within a color component, the 

LSB is sent first, the MSB last. 

7.2.3 TV Display Support 

The TV display path includes the following modules: 

• Display controller 

• Video encoder 

• Video DAC stage comprising two single 10-bit DACs (AVDAC1 and AVDAC2) with video amplifiers 

The display controller module receives synchronization signals from the video encoder and synchronously 

sends pixel data to the video encoder with these signals. The digital output of the display controller is 

always a 24-bit RGB value based on a pixel request from the video encoder. 

The video encoder converts RGB video signals to conform to the NTSC/PAL standard analog video. The 

video encoder includes an integrated synchronization signal generator and two single channel video 

digital-to-analog converters (DACs) with video amplifiers, data manager, luma stage, chroma stage, 

modulator, and a control interface. 

The video encoder also provides the synchronization signals to the display controller: VSYNC, active 

VIDeo (AVID), and field ID (FID). 

Figure 7-58 is a block diagram of the TV display interface (S-video mode, DC coupled, High Full Scale 

Swing). 



dss-157



controller 



controller 

Video 

encoder 

Video 

encoder 



Figure 7-58. TV Display Interface (S-video mode, DC coupled, High FS Swing) 

DAC Stage 

DAC1 

amplifier 

(luma) 

DAC2 

amplifier 

(chroma) 

DAC Stage 

DAC1 

amplifier 

+ 

+ 

+ 

+ 

DAC2 

amplifier 

(unused) 

cvideo1_vfb 

cvideo1_out 

cvideo2_out 

cvideo2_vfb 

cvideo1_rset 

vssa_dac 

Rout1 

Rout2 

Rset 

Analog TV set 

Luminance input 

Chrominance input 

vdda_dac Power IC 

cvideo1_vfb 

cvideo1_out 

cvideo2_out 

cvideo2_vfb 

cvideo1_rset 

vssa_dac 

Rout 1 

NC 

NC 

Rset 

Composite 

connector 

camdss_GN3-001 

Figure 7-59 is a block diagram of the TV display interface (Composite mode, DC coupled, High Full Scale 

Swing). 

Figure 7-59. TV Display Interface (Composite Mode, DC coupled, High FS Swing) 

Composite input 


Figure 7-60 is a block diagram of the TV display interface (Composite mode, AC coupled, Low Full Scale 

Swing). 



dss-191 

1595



controller 



controller 

Video 

encoder 

Video 

encoder 

* (Rout1 and Rout2 loads can be integrated in the amplifier, 

and thus not needed as external components) 



Figure 7-60. TV Display Interface (Composite Mode, AC coupled, Low FS Swing) 

DAC Stage 

DAC1 

amplifier 

+ 

+ 

DAC2 

amplifier 

(unused) 

+ 

DAC2 

amplifier 

(unused) 

Cout 

cvideo1_out 

cvideo1_vfb 

cvideo2_out 

cvideo2_vfb 

cvideo1_rset 

vssa_dac 

Rout 1 

NC 

NC 

Rset 

Composite input 

Composite 

connector 


NOTE: In composite video mode, the video DAC2 chroma output must be disabled by setting the 

DSS.VENC_OUTPUT_CONTROL[2] CHROMA_ENABLE bit to 0. 

Figure 7-61 is a block diagram of the TV display interface (Bypass mode, Dual Channel). 

Figure 7-61. TV Display Interface (Bypass Mode, Dual Channel) 

DAC Stage 

DAC1 

amplifier 

+ 

cvideo1_vfb 

cvideo1_out 

cvideo2_vfb 

cvideo2_out 

cvideo1_rset 

vdda_dac 

vssa_dac 

(Rout1)* 

NC 

(Rout2)* 

Table 7-17 describes the interface signals to/from the TV set for TV display support. 

NC 

Rset 

Video amplifier 

Power IC 



dss-401 

dss-402



Pin Name Type (1) 

Table 7-17. TV Display Interface Pins 

Description 

cvideo1_out O Analog luma or composite video output. An external resistor Rout1 is 

connected between this node and the cvideo1_vfb pin. Note that this is the 

output node that drives the load (75 Ω). 

cvideo2_out O Analog chroma video output. An external resistor Rout2 is connected 

between this node and the cvideo2_vfb pin. This is the output node that 

drives the load (75 Ω). 

cvideo1_vfb O Amplifier feedback node. An external resistor Rout1 is connected between 

this node and cvideo1_out. 

cvideo2_vfb O Amplifier feedback node. An external resistor Rout2 is connected between 

this node and cvideo2_out. 

cvideo1_rset I/O External resistor pin to set the reference current of the AVDAC1. The value 

of the resistor (Rset) depends on the mode of operation. Refer to 

Table 7-18, Typical values for Rout, Rset and Cout. 

vdda_dac Power Analog supply voltage for the video DAC stage 

vssa_dac Power Analog ground for the video DAC stage 

(1) O = Output, Power = Power pin 

Table 7-18 lists the typical values for the Rout1/2 and Rset resistors and the Cout capacitor, for different 

modes of the TV display interface. 

Table 7-18. Typical values for Rout, Rset and Cout 

S-video, DC Composite, DC Composite, AC Bypass, Dual Unit 

coupled, High FS coupled, High FS coupled, Low FS channel 

Swing Swing Swing 

Rout 1 2700 2700 2700 1500 Ohm 

Rout 2 2700 N/A N/A 1500 Ohm 

Rset 4700 4700 6800 10000 Ohm 

Cout N/A N/A 220 N/A µF 



1597



CAUTION 

• High full-scale swing is the default mode. Low-swing mode does not comply 

with the NTSC and PAL video standards. It must be used only for backward 

compatibility to the OMAP35x. 

• All resistor values in Table 7-18 must be within ± 1% tolerance range. 

• cvideo1_out and cvideo2_out are very high-frequency analog signals and 

must be routed with extreme care. As a result, the path of these signals 

must be as short as possible, and as isolated as possible from other 

interfering signals. 

• During board design, the onboard traces and parasites must be matched for 

the two channels. cvideo1_vfb and cvideo2_vfb pins are the most sensitive 

pins in the TV out system. The onboard parasitic capacitance associated 

with these two pins must be less than 0.5 pF. Low onboard resistance is 

required for the traces that connect the Rout1/Rout2 to the 

cvideo1_vfb/cvideo2_vfb and TV OUT pins (cvideo1_out and cvideo2_out). 

The resistance on those trace affects output impedance matching. 

Therefore, Rout1 and Rout2 resistors are suggested to be placed as close 

as possible to the device pins. The onboard traces lead to the TV OUT pins 

must have a characteristic impedance of 75 Ω starting from the closest 

possible place to the device pin output. 

• If the TV output is not used, the following configurations for the AVDACs 

pins must be applied: 

– Configuration 1 

7.2.3.1 TV Output and Data Format 

• cvideo1_out must be grounded. 

• cvideo1_vfb must be grounded. 

• cvideo2_out must be grounded. 

• cvideo2_vfb must be grounded. 

• cvideo1_rset must be grounded. 

• vdda_dac must be grounded. 

• vssa_dac must be grounded. 

– Configuration 2 

• cvideo1_out must be floating, left unconnected. 

• cvideo1_vfb must be floating, left unconnected. 

• cvideo2_out must be floating, left unconnected. 

• cvideo2_vfb must be floating, left unconnected. 

• cvideo1_rset must be floating, left unconnected. 

• vdda_dac must be grounded. 

• vssa_dac must be grounded. 

• To avoid current leakage, the following bits must be set to 0: 

– DSS.DSS_CONTROL[5] 

DAC_POWERDN_BGZ 

– DSS.VENC_OUTPUT_CONTROL[2:0] 

– PRCM.CM_FCLKEN_DSS[2] EN_TV 

– CONTROL.CONTROL_DEVCONF[18] TVOUTBYPASS 

The output data to the TV set are the analog composite data from the video DAC stage. The following 

video standards are supported: 

• NTSC-J, M 

• PAL-B, D, G, H, I 

• PAL-M 




www.ti.com Display Subsystem Integration 

7.2.3.2 Digital-to-Analog Converters 

The video DAC stage includes the following main features: 

• 1.1-V digital power supply, 1.8-V analog power supply 

• 10-bit resolution 

• DNL within 1 LSB and INL within 1 LSB (in bypass mode) 

• Sample rate of up to 60 mega samples per second (MSPS) 

• Support composite/S-video DC or AC coupled output 

• Support TVOUT buffer bypass mode (DAC-only mode) 

• Full-scale voltage output: minimum 1.2 Vpp with a 75-Ω load 

• Internal TV detect feature 

• Signal-to-noise ratio (SNR) is 54 dB (taking into account the ac coupling) 

• Suitable for low-power consumer video applications 

• Power-down mode with less than 12-µA standby current 

• Differential gain error and differential phase error: within 3 percent and 1 degree, respectively 

NOTE: To enhance the TV color display, it is highly recommended to set the 

DSS.DSS_CONTROL[4] DAC_DEMEN bit. 

For more information about the video DAC stage architecture and configuration, see 

Section 7.4.7.7, Video DAC Stage – Architecture and Control. 

7.3 Display Subsystem Integration 

This section describes the integration of the display subsystem and details clocks, resets, hardware 

requests, and power modes. 

Figure 7-62 shows the integration of the display subsystem in the device. 



1599

PRCM 

DSS_L3_ICLK 

DSS_L4_ICLK 



DSS_TV_FCLK 



System DMA 

controller 

(sDMA) 

MPU subsystem 

interrupt controller 

IVA2.2 subsystem 


STANDBY/WAIT 

handshake 

S_DMA_5 

S_DMA_[71:74] 

M_IRQ_25 

IVA2_IRQ[13] 

System 

control module 

CONTROL_DEVCONF1[11] 

CONTROL_DEVCONF1[18] 

CONTROL_AVDACx [ 20 : 16] 

DSS_L3_ICLK 

DSS_L4_ICLK 



DSS_TV_FCLK 

Device 

DSI1_PLL_FCLK 

DSI2_PLL_FCLK 


DSS_DMA_REQ[3:0] 

4 

DSS_IRQ 


controller 

Syncs 

DSI 

protocol 

engine 


Display Subsystem Integration www.ti.com 

Figure 7-62. Display Subsystem Integration 


Digital 

data 

24 

Data 

Controls 

Remote 

frame buffer 

interface 

TV out 

back-end 

Video DAC 

Stage 

TVACEN 

TVOUTBYPASS 

COMP_EN 

DSI 

complex I/O 

DSI 

PLL 

controller 

TVINT 

Status 

PLL 

control 

GPIO2 

DSI PLL 

HS divider 

camdss-036 



DSI1_PLL_FCLK 

DSI2_PLL_FCLK 

DSI PLL 

control 


subsystem 

dsi_dxi 

DSI_PLL_REFCLK 

DSS 2_ALWON _FCLK (BYPASS) 

PCLKFREE 

DSS 1_ALWON _FCLK (BYPASS) 

Device 

DSI PLL 

HS 

divider 

CLKIN4DDR 

PRCM 

DSI complex I/O 

DSS_L3_ICLK 

DSS2_ALW ON_ 

FCLK 

SYS_CLK 

DSI_FCLK 

dsi_dyi 

DSI protocol 

engine 

DSS_L4_ICLK 

DSS_L3_ICLK 

TxByteClkHS 

DSS1_ALW ON_ 

FCLK 

Sync 

DISPC_ 

FCLK 

DPLL 4_ALWON_ 

FCLKOUTM4X2 



7.3.1 Clocking, Reset, and Power-Management Scheme 

7.3.1.1 Clocks 

The power, reset, and clock management (PRCM) module provides six clock signals to the display 

subsystem: The L3 interface clock (DSS_L3_ICLK) and the L4 interface clock (DSS_L4_ICLK), with 

frequencies equal to the L3 interconnect clock and the L4 interconnect clock, respectively; two 

configurable functional clocks (DSS1_ALWON_FCLK and DSS2_ALWON_FCLK); and one other 

functional clock (DSS_TV_FCLK). 

The DSI PLL provides two functional clock signals to the display subsystem: DSI1_PLL_FCLK and 

DSI2_PLL_FCLK. 

Figure 7-63 details the clock tree for the display subsystem. 

Figure 7-63. Display Subsystem Clock Tree 

Divider 

LCD 

CMOS pads 

RFBI 

PCLK FCLK 

Divider 

PCD Display 

DSS_L3_ICLK 

L3_ICLK 

controller 

DSS _L4_ICLK 

DSS_L4_ICLK 

x1 

L4_ICLK 

sys_altclk 

DSS_TV_FCLK 

Video encoder 

x1 x2 x4 

Clock generator 

DPLL4_ALWON_ 

FCLKOUTM3X2 



Video 

DACs 

camdss-158 

1601



NOTE: A synchronization signal is sent by the display controller (DISPC) to the DSI protocol 

engine. This signal, named DISPC_UPDATE_SYNC, is used to inform the DSI protocol 

engine that it must be unsynchronized with the display controller. 

Table 7-19 describes the different clocks with their possible frequency values. 

Table 7-19. Display Subsystem Clocks 

Clock Signal Attribute Module Frequency Comment 

DSS_L3_ICLK L3 interface clock DSS (See Chapter 3, Power, L3 interface clock from PRCM 

Reset, and Clock 

Management) 

DSS_L4_ICLK L4 interface clock DSS (See Chapter 3, Power, L4 interface clock from PRCM 

Reset, and Clock 

Management) 

DSS1_ALWON_FCLK Functional clock DISPC, DSI protocol Up to 173 MHz at nominal From PRCM: DPLL4 (source: 

engine voltage (OPP100), and up DPLL4_ALWON_FCLK) 

to 100 MHz at low voltage 

(OPP50) 

DSS2_ALWON_FCLK Functional clock DSI PLL 12/13/16.8/19.2/26/38.4 From PRCM: SYS_CLK 

MHz 

DSI1_PLL_FCLK Functional clock DISPC Up to 173 MHz at nominal From DSI PLL and HS divider 

voltage (OPP100), and up 


(OPP50) 

DSI2_PLL_FCLK Functional clock DSI protocol engine Up to 173 MHz at nominal From DSI PLL and HS divider 

voltage (OPP100), and up 


(OPP50) 

DSS_TV_FCLK Functional clock DSS, video mode 54 MHz or From PRCM: DPLL4 (source: 

DAC DPLL4_ALWON_FCLK) or 

sys_alt_clk (up to 59 External input clock (See Chapter 3, 

MHz) Power, Reset, and Clock 

Management) 

To enable or disable each functional clock, set the following bit (1: Enable, 0: Disable): 

• PRCM.CM_FCLKEN_DSS[0] EN_DSS1 bit to enable DSS1_ALWON_FCLK 

• PRCM.CM_FCLKEN_DSS[1] EN_DSS2 bit to enable DSS2_ALWON_FCLK 

• PRCM.CM_FCLKEN_DSS[2] EN_TV bit to enable DSS_TV_FCLK 

To enable or disable the DSS_L3_ICLK and DSS_L4_ICLK interface clocks, write (1: Enable, 0: Disable) 

to the PRCM.CM_ICLKEN_DSS[0] EN_DSS bit. 

NOTE: Note that it is not possible to gate/stop L3 clock and keep L4 clock running. 

• L3 and L4 interface clock 

The DSS_L3_ICLK clock is only used by the display controller interface to fetch the pixel data. The 

DSS_L4_ICLK is used to access the L4 interconnect for configuring all the display subsystem 

registers. 

NOTE: A clock generated internally from the L3 interface clock allows the submodules to be 

configured and is the functional clock for the RFBI. All the display subsystem registers are 

configured through the display subsystem register. 

• Display controller functional clocks 

The display controller can use either the DSS1_ALWON_FCLK or the DSI1_PLL_FCLK functional 

clock. 





To select the DSS1_ALWON_FCLK functional clock (the default clock selected after reset), write 0 in 

the DSS.DSS_CONTROL[0] DISPC_CLK_SWITCH bit; to select the DSI1_PLL_FCLK functional clock, 

write 1 in the DSS.DSS_CONTROL[0] DISPC_CLK_SWITCH bit. 

NOTE: The DSS1_ALWON_FCLK and DSI1_PLL_FCLK functional clocks must be active (the 

PRCM.CM_FCLKEN_DSS[0] EN_DSS1 and DSI PLL programmed correctly) to switch from 

one functional clock to another. The new functional clock is effective when the next vertical 

blanking interval occurs. This is true only if the DSS.DISPC_CONTROL[5] GOLCD bit is set 

to 1. 

Depending on the DPLL4 input clock frequency, the DSS1_ALWON_FCLK can be adjusted by setting the 

PRCM.CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 bit field. 

• DSI PLL functional clock (DSI_PLL_REFCLK) 

The DSI PLL controller module can use either the DSS2_ALWON_FCLK (from PRCM) or the 

PCLKFREE (from DISPC) functional clock. To select the DSS2_ALWON_FCLK functional clock 

(default clock selected after reset), write 0 in the DSS.DSI_PLL_CONFIGURATION2[11] 

DSI_PLL_CLKSEL bit; to select the PCLKFREE functional clock, write 1 in the 

DSS.DSI_PLL_CONFIGURATION2[11] DSI_PLL_CLKSEL bit. 

• DSI protocol engine functional clocks (DSI_FCLK) 

The DSI protocol engine can use either the DSS1_ALWON_FCLK (from PRCM) or the 

DSI2_PLL_FCLK (from DSI PLL) functional clock. To select the DSS1_ALWON_FCLK functional clock 

(default clock selected after reset), write 0 in the DSS.DSS_CONTROL[1] DSI_CLK_SWITCH bit; to 

select the DSI2_PLL_FCLK functional clock, write 1 in the DSS.DSS_CONTROL[1] 

DSI_CLK_SWITCH bit. 

NOTE: It is possible to switch between these two clocks, even when both of them are not active. 

• There are five clock domains in the DSI module: 

– Byte clock domain: 

TxByteClkHS is generated from the bit clock and converted into a byte clock. The maximum 

frequency is 112.5 MHz at nominal voltage (OPP100), and 100 MHz at low voltage (OPP50). It is 

generated by the DSI complex I/O. 

– Functional clock domain 

The DSI_FCLK is the functional clock for the DSI protocol engine module. The maximum frequency 

is 173 MHz (nominal voltage) and 100 MHz (low voltage). It must always be equal to or higher than 

the byte (TxByteClkHS), L4 interconnect (DSS_L4_ICLK), and video port (VP_CLK) clocks. The 

software must configure the clocks correctly. 

– L4 interface clock domain 

The DSS_L4_ICLK is used in the L4 interconnect port domain. The maximum frequency is 100 

MHz at nominal voltage. 

– The video port domain 

The pixel clock (PCLK) on the video port is used by the video port domain to capture the pixels 

from the display controller. The maximum frequency of VP_CLK used as the functional clock for the 

video port domain is 173 MHz at nominal voltage and 96 MHz at low voltage. 

– Serial Configuration Port (SCP) and Power Control (PWR) interfaces 

The DSS_L4_ICLK is the functional clock. 

NOTE: 

• There is no clock domain for RxClkEsc because it is used as an enable and not as a 

clock by the DSI protocol engine module 

• The clock domains are asynchronous (except for L4 interconnect port and SCP/PWR 

because both of them use DSS_L4_ICLK). The clocks used for the L4 interconnect port 

and SCP/PWR interface must be balanced. 

• If video mode is used, the display controller functional clock must be generated using a 

clock from the DSI PLL. 



1603



• Video encoder functional clock 

The DSS_TV_FCLK is divided into three balanced clocks, depending on the clock mode selected (see 

Table 7-20). 

Table 7-20. Possible Digital Clock Division for the Video Encoder 

Clock Output Clock Mode 

Clock Mode 0 Clock Mode 1 

Video encoder clock 4x DSS_TV_FCLK DSS_TV_FCLK or 0 (gated) 

Video encoder clock 2x DSS_TV_FCLK/2 DSS_TV_FCLK 

Video encoder clock 1x DSS_TV_FCLK/4 DSS_TV_FCLK/2 

The clock mode is defined by the DSS_CONTROL[2] VENC_CLOCK_MODE register bit: 

• In the case of clock mode 1, the DSS_CONTROL[3] VENC_CLOCK_4X_ENABLE bit is used to control 

clock gating. 

• In the case of clock mode 0, the VENC_CLOCK_4X_ENABLE bit must be set to 0x1 by software. 

NOTE: After reset, clock mode 0 is selected by default, and the DSS_TV_CLK clock is disabled. 

The DSS_TV_CLK / 4 in mode 0, or the DSS_TV_CLK / 2 in mode 1, is used in the DISPC 

module to send data to the video encoder. 

NOTE: Clock mode 1 can be used for power-saving purposes, or if a 27-MHz external clock is 

provided to the video encoder. 

DSS_TV_FCLK can be adjusted depending on the DPLL4 input clock frequency by setting the 

PRCM.CM_CLKSEL_DSS[12:8] CLKSEL_TV bit field. If the DPLL4 is selected, the DSS_TV_FCLK is 

provided by the DPLL4_ALWON_FCLKOUTM3X2 clock. 

NOTE: If the DSS_TV_FCLK is not provided by DPLL4 but rather by the sys_alt_clk pin, an 

external clock generator must be connected to this pin. In this case, a 54-MHz clock is 

needed for PAL or NTSC 601, a 49.09-MHz clock is needed for NTSC square pixel, and a 

59-MHz clock is needed for PAL square pixel. 

• Video DAC stage clocks 

The video DAC stage uses one distinct clock: The DSS_TV_FCLK. The video data are latched on the 

positive edge of the DSS_TV_FCLK clock. 

7.3.1.2 Resets 

7.3.1.2.1 Hardware Reset 

The display subsystem receives its reset signal DSS_RST (the reset signal of the display subsystem 

[DSS] power domain) from the PRCM module. 

7.3.1.2.2 Software Reset 

The display subsystem can receive a software reset propagated through all of the submodules and used 

to initialize the display subsystem. To apply the reset, write to the DSS.DSS_SYSCONFIG[1] 

SOFTRESET bit (1: Reset; 0: Normal). The DSS.DSS_SYSSTATUS[0] RESETDONE bit indicates that the 

software reset is complete when its value is 1. 





NOTE: The display controller, the DSI protocol engine, and the RFBI modules also have their own 

software reset functionality. To access this reset, access the DSS.DISPC_SYSCONFIG[1] 

SOFTRESET bit for the display controller, the DSS.DSI_SYSCONFIG[1] SOFTRESET bit for 

the DSI protocol engine, and the DSS.RFBI_SYSCONFIG[1] SOFTRESET bit for the RFBI 

module. 

7.3.1.3 Power Domain 

To properly reset these modules, 0x2 is the only valid value to write to these registers. 

CAUTION 

All the interface and functional clocks, even for the TV output, must be provided 

to the display subsystem to update the RESETDONE status bit correctly. 

The display subsystem modules are on the display subsystem (DSS) power domain and on the VDD2 

voltage domain, except for the video DAC stage, which are on the analog vdda_dac voltage domain. 

7.3.1.4 Power Management 

7.3.1.4.1 Clock Activity Mode 

The display controller clocks can be configured in one of the following clock activity modes: 

• DSS.DISPC_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x0 (reset value): The interface and 

functional clocks can be switched off. 

• DSS.DISPC_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x1: The functional clocks can be can 

be switched off and the interface clocks are maintained during the wake-up period. 

• DSS.DISPC_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x2: The interface clocks can be can 

be switched off and the functional clocks are maintained during the wake-up period. 

• DSS.DISPC_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x3: The interface and functional 

clocks are maintained during the wake-up period. 

The DSI protocol engine clocks can be configured in one of the following clock activity modes: 

• DSS.DSI_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x0 (reset value): The interface and 

functional clocks can be switched off. 

• DSS.DSI_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x1: The functional clocks can be 

switched off and the interface clocks are maintained during the wake-up period. 

• DSS.DSI_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x2: The interface clocks can be switched 

off and the functional clocks are maintained during the wake-up period. 

• DSS.DISPC_SYSCONFIG[9:8] CLOCKACTIVITY bit field set to 0x3: The interface and functional 

clocks are maintained during the wake-up period. 

The DSS power domain clock activity status is logged in the PRCM.CM_CLKSTST_DSS[0] 

CLKACTIVITY_DSS status bit. When set to 0, there is no domain clock activity. When set to 1, the DSS 

power domain clock is active. 

NOTE: The display subsystem interface clock can be dependent on the DSS power domain state. 

This is configured with PRCM.CM_AUTOIDLE_DSS[0] AUTO_DSS bit: 

• When the AUTO_DSS bit is set to 0 (reset value): The display subsystem interface clock 

is not related to the DSS power domain state transition. 

• When the AUTO_DSS bit is set to 1: The display subsystem interface clock is 

automatically enabled or disabled along with the DSS power domain state transition. 



1605



7.3.1.4.2 Autoidle Mode 

The RFBI, display controller, DSI protocol engine, and L4 interfaces can internally gate their clocks to 

decrease power consumption if no transaction is present on the related bus. The following bits must be set 

to enable this functionality: 

• DSS.DSS_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display subsystem 

• DSS.RFBI_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the RFBI 

• DSS.DISPC_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display 

controller 

• DSS.DSI_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the DSI protocol 

engine 

• DSS.DISPC_CONFIG[9] FUNCGATED bit (1: Functional clocks gated enabled; 0: Functional clocks 

gated disabled) for the display controller 

7.3.1.4.3 Idle Mode 

NOTE: All the bits listed above (except for the FUNCGATED bit) are set to 1 by default. It is highly 

recommended to set all the bits to 1 to save power. 

The display controller, DSI protocol engine, and RFBI can be configured into one of the following 

acknowledgment modes: 

• Force-idle mode: The module immediately enters the idle state on receiving a low-power mode request 

from the PRCM module. In this mode, the software must ensure that there are no asserted output 

interrupts before requesting this mode to go into the idle state. Set the DSS.DISPC_SYSCONFIG[4:3] 

SIDLEMODE bit field to 0x0 (reset value) for display controller, set the DSS.DSI_SYSCONFIG[4:3] 

SIDLEMODE bit field to 0x0 (reset value) for DSI protocol engine, and, finally, the 

DSS.RFBI_SYSCONFIG[4:3] SIDLEMODE bit field to 0x0 (reset value) for RFBI. 

• No-idle mode: The module never enters the idle state. Set the DSS.DISPC_SYSCONFIG[4:3] 

SIDLEMODE bit field to 0x1 for display controller, set the DSS.DSI_SYSCONFIG[4:3] SIDLEMODE bit 

field to 0x1 for DSI protocol engine, and, finally, the DSS.RFBI_SYSCONFIG[4:3] SIDLEMODE bit field 

to 0x1 for RFBI. 

• Smart-idle mode: 

– Display controller: After receiving a low-power-mode request from the PRCM module, the display 

controller module enters the idle state when all the following conditions are satisfied: 

• All asserted output interrupts are acknowledged (no interrupt pending). 

• The display controller does not use anymore the L4 interface clock (DSS_L4_ICLK). 

– DSI protocol engine: After receiving a low-power-mode request from the PRCM module, the DSI 

protocol engine enters the idle state when all the following conditions are satisfied: 

• All asserted output interrupts are acknowledged (no interrupt pending). 

• The DSI protocol engine does not use the L4 interface clock (DSS_L4_ICLK) anymore. 

• The SCP and PWR transactions are complete. 

• No data remains in the TX FIFO (data waiting in the FIFO to be sent to the peripheral). 

To configure the display subsystem in smart-idle mode, set the DSS.DISPC_SYSCONFIG[4:3] 

SIDLEMODE bit field to 0x2 for display controller, set the DSS.DSI_SYSCONFIG[4:3] SIDLEMODE bit 

field to 0x2 for DSI protocol engine, and, finally, the DSS.RFBI_SYSCONFIG[4:3] SIDLEMODE bit field 

to 0x2 for RFBI. 

Once the idle handshake protocol is over: 

• The DSS L4 interface clock (DSS_L4_ICLK) can be shutdown at any time. 

• Any transaction on the L4 configuration port is ignored. 

7.3.1.4.4 Wake-Up Mode 

The Display Controller (DISPC) supports the wake-up protocol. The mode is selected by programming the 

appropriate value in the DSS.DISPC_SYSCONFIG[2] ENWAKEUP bit. The wake-up signal is asserted 

when the DISPC is in idle mode and when anyone of the following events occur: 





• Graphics pipe is enabled and data fetch is not completed for graphics window, and the number of data 

bytes in FIFO is less than the low threshold programmed value. 

• Video1 pipe is enabled and data fetch is not completed for video1 window, and the number of data 


• Video2 pipe is enabled and data fetch is not completed for video2 window, and the number of data 


• The current pixel is the last pixel displayed on the LCD panel if it is not the last frame. 

• The current pixel is the last pixel displayed on the digital panel if it is not the last frame. 

If software users set the DSS.DISPC_CONFIG[17] FIFOFILLING bit, when one of the active pipe 

reaches the low threshold and should refill the FIFO for the current frame, the other pipes also refill 

their own FIFOs, even if the low threshold has not been reached. This is used to improve the 

probability of increasing the time when there is no access to the L3 interconnect (MStandby asserted, 

affects power savings). 

Once the wake-up signal is asserted, the WAKEUP interrupt request is generated. The wake-up signal 

is deasserted when the idle request is no longer activated. 

7.3.1.4.5 Standby Mode 

As part of the system-wide power-management scheme, the display controller can enter standby mode. 

To configure the display controller, write the DSS.DISPC_SYSCONFIG[13:12] MIDLEMODE bit field (00: 

Forced standby; 01: No standby; 10: Smart standby) in one of the following standby modes: 

• Forced standby mode (default mode): The module enters standby mode when the module is disabled. 

• No standby mode: The module never enters standby mode. 

• Smart standby mode: The module enters standby state when the DISPC module is disabled or when 

all the three following events occur: 

– Graphics pipe is disabled or graphics pipe is enabled but data fetch completed for graphics window, 

or graphics pipe is enabled and data fetch is not completed and number of data bytes in FIFO is 

greater than the high threshold programmed value. 

– Video1 pipe is disabled or video1 pipe is enabled but data fetch completed for video1 window, or 

video1 pipe is enabled and data fetch is not completed and number of data bytes in FIFO is greater 

than the high threshold programmed value. 

– Video2 pipe is disabled or video2 pipe is enabled but data fetch completed for video2 window, or 

video2 pipe is enabled and data fetch is not completed and number of data bytes in FIFO is greater 

than the high threshold programmed value. 

When in standby mode, the display controller does not generate transactions on the L3 master port. 

Standby is active when the PRCM module confirms this mode. 

The display subsystem standby mode activity can be monitored with the PRCM.CM_IDLEST_DSS[0] 

ST_DSS status register. When this register is read to 0, the display subsystem is accessible and the 

interface clock running; when it is read to 1, the display subsystem is in standby mode. 

7.3.1.4.5.1 Conditions to Exit Standby Mode 

The following conditions allow the subsystem to exit standby mode: 

• Forced standby mode: Standby mode is exited when the display controller is enabled. 

• Smart standby mode: Standby mode is exited when any one of the following events occurs: 

– Graphics pipe is enabled and data fetch is not completed for graphics window, and number of data 


– Video1 pipe is enabled and data fetch is not completed for video1 window, and number of data 


– Video2 pipe is enabled and data fetch is not completed for video2 window, and number of data 




1607



7.3.1.4.5.2 Standby Transition Dependency 

The sleep transition of the DSS power domain can be dependent or not with respect to MPU domain. This 

is configured by PRCM.CM_SLEEPDEP_DSS[1] EN_MPU bit: 

• When the EN_MPU bit is set to 0 (reset value): The DSS power domain sleep dependency with the 

MPU power domain is disabled. The DSS power domain will not enter idle unless the MPU power has 

previously entered idle. 

• When the EN_MPU bit is set to 1: The DSS power domain sleep dependency with the MPU power 

domain is enabled. The DSS power domain will enter idle regardless of the power domain state of the 

MPU. 

The sleep transition of the DSS power domain may, or may not depend on the IVA2.2 domain, depending 

on the configuration of the PRCM.CM_SLEEPDEP_DSS[2] EN_IVA2 bit: 

• When the EN_IVA2 bit is set to 0 (reset value): The DSS power domain sleep dependency on the 

IVA2.2 power domain is disabled. 

• When the EN_IVA2 bit is set to 1: The DSS power domain sleep dependency on the IVA2.2 power 

domain is enabled. 

7.3.1.4.5.3 Standby Procedure Description 

When the display subsystem initiates a standby procedure, it also initiates an standby/wait handshake 

protocol with the PRCM module that lets the PRCM cut the display subsystem clocks. Depending on the 

PRCM setting, two modes are available: 

• Manual mode 

– DSS1_ALWON_FCLK is shut down when the PRCM.CM_FCLKEN_DSS[0] EN_DSS1 bit is set to 0 

and the display subsystem is in standby mode. 

– DSS2_ALWON_FCLK is shut down when the PRCM.CM_FCLKEN_DSS[1] EN_DSS2 bit is set to 0 

and the display subsystem is in standby mode. 

– DSS_L3_ICLK and DSS_L4_ICLK are controlled together. They are shut down when the 

PRCM.CM_ICLKEN_DSS[0] EN_DSS bit is set to 0 and the display subsystem is in standby mode. 

CAUTION 

Do not stop DSS1_ALWON_FCLK, or DSS2_ALWON_FCLK clock (if used) if 

the display subsystem is not disabled. 

CAUTION 

DSS_TV_FCLK does not depend on the display subsystem standby state. 

Ensure correct clock management for DSS_TV_FCLK. 

The clocks are reactivated when the related bits are set to 1 and the display subsystem exits from 

standby. For more information, see Chapter 3, Power, Reset, and Clock Management. 

• Hardware- or software-supervised mode 

The DSS-power state-transition between active and inactive states can be either hardware or software 

supervised. This is programmed with the PRCM.CM_CLKSTCTRL_DSS[1:0] CLKTRCTRL_DSS bit 

field: 

– When the CLKTRCTRL_DSS bit field is set to 0x0 (reset value), the automatic transition is disabled 

– When the CLKTRCTRL_DSS bit field is set to 0x1, the software-supervised sleep transition is 

started on the DSS power domain. 

– When the CLKTRCTRL_DSS bit field is set to 0x2, the software-supervised wake-up transition is 

started on the DSS power domain. 

– When the CLKTRCTRL_DSS bit field is set to 0x3, the automatic transition is enabled. Any 

transition on the DSS power domain is supervised by the hardware. 





7.3.1.4.5.4 Display Subsystem Standby Mode, Power-Saving Use Cases 

• Setup 

– Set the display subsystem in smart standby mode. 

– Manually enable DSS_L3_ICLK and DSS_L4_ICLK. 

– Manually enable DSS1_ALWON_FCLK or DSS2_ALWON_FCLK. 

– Manually enable DSS_TV_FCLK if the video encoder is used. 

– Set the PRCM.CM_CLKSTCTRL_DSS[1:0] CLKTRCTRL_DSS bit field to 0x3 (autocontrol mode 

supervised by hardware). 

• Shut down the display subsystem. 

– Disable the display subsystem. 

– Manually disable DSS1_ALWON_FCLK, DSS2_ALWON_FCLK, DSS_TV_FCLK, DSS_L3_ICLK, 

and DSS_L4_ICLK. 

For more details on low-power programming settings, see Section 7.6.2. 



1609

DSI protocol engine 

RFBI 

Display controller 


DSI_DMA_REQ0 

DSI_DMA_REQ1 

DSI_DMA_REQ2 

DSI_DMA_REQ3 

RFBI_DMA_REQ 




7.3.2 Hardware Requests 

7.3.2.1 DMA Requests 

The display controller, the DSI protocol engine, and the RFBI generate some DMA requests to the sDMA. 

Figure 7-64 details the DMA tree. 

Figure 7-64. Display Subsystem DMA Tree 

Table 7-21. DSS DMA Requests Description 

DSS_DMA0 

DSS_DMA1 

DSS_DMA2 

DSS_DMA3 


DMA Request Name DSS Module Mapping Description 

DSS_LINE_TRIGGER DISPC S_DMA_5 See Section 7.3.2.1.1 

DSI_DMA_REQ0 DSI protocol engine S_DMA_71 See Section 7.3.2.1.2 




RFBI_DMA_REQ RFBI S_DMA_74 See Section 7.3.2.1.3 

NOTE: The DMA requests from the RFBI module (RFBI_DMA_REQ) and the DSI protocol engine 

(DSI_DMA_REQ3) are merged on line DSS_DMA3. The software must only use DSS_DMA3 

on one module at a time (RFBI or DSI protocol engine). 

7.3.2.1.1 Display Controller DMA Request (Line Trigger) 

One DMA synchronization line (DSS_LINE_TRIGGER) is connected to the sDMA by the sDMA controller 

(S_DMA_5) input line. This DMA request is not a classical one but a synchronization signal from the 

display subsystem to the sDMA informing the sDMA that a programmable number of lines are output to 

the LCD, and that the system memory can be updated. This request is related to an interrupt event 

described in Section 7.3.2.2, Interrupt Requests. This allows the sDMA channel to be synchronized with 

the display subsystem internal DMA controller. In other words, it allows to synchronize a memory to 

memory frame buffer update based on the scan line of the frame buffer in system memory (SDRAM or 

SRAM) by the display controller. The DSS_LINE_TRIGGER DMA request is generated at a programmable 

line number defined in DSS.DISPC_LINE_NUMBER[10:0] LINENUMBER bit field. 



dss-159


ULPSACTIVENOT_ALL1_IRQ_EN 

ULPSACTIVENOT_ALL1_IRQ 

ERRSYNCESC1_IRQ_EN 

ERRSYNCESC1_IRQ 

DSI virtual channel 3 

ECC_NO_CORRECTION_IRQ_EN 

ECC_NO_CORRECTION_IRQ 

CS_IRQ_EN 

CS_IRQ 

DSI virtual channel 0 




CS_IRQ_EN 

CS_IRQ 

....... 

....... 

....... 

31 

0 

6 

0 

6 

0 



7.3.2.1.2 DSI Protocol Engine DMA Request 

The DSI DMA requests are used to allow automatic transfer by the sDMA or MPU (with less efficiency and 

through-put capability) from the DSI RX FIFO to the system memory and from the system memory to the 

DSI TX FIFO. Two independent DMA requests for RX FIFO and TX FIFO for the same VC are supported. 

7.3.2.1.3 RFBI DMA Request 

The RFBI_DMA_REQ is used to receive data into the RFBI FIFO. The DMA request is always generated 

when there is enough room in the FIFO to accept the full burst. 

7.3.2.2 Interrupt Requests 

The DSI protocol engine, the DSI complex I/O (DSI_IRQ), and the display controller (DISPC_IRQ) 

generate one interrupt request each. The DSI_IRQ and DISPC_IRQ lines are merged together in a single 

interrupt line. 

One interrupt line (DSS_IRQ) is connected to two interrupt controllers: 

• MPU interrupt controller (M_IRQ_25 input line) 

• IVA interrupt handler (IVA2_IRQ[13] input line) 

Figure 7-65 shows the interrupt tree for the DSI protocol engine and DSI complex I/O in detail. 

Figure 7-65. DSI Interrupt Tree 

DSI_COMPLEXIO_IRQSTATUS 

DSI_VC3_IRQSTATUS 

DSI_VC0_IRQSTATUS 

TA_TO_IRQ_EN 

TA_TO_IRQ 

....... 

HS_TX_TO_IRQ_EN 

HS_TX_TO_IRQ 

COMPLEXIO_ERR_IRQ 

PLL_RECAL_IRQ_EN 

PLL_RECAL_IRQ 

....... 

WAKEUP_IRQ_EN 

WAKEUP_IRQ 

VIRTUAL_CHANNEL3_IRQ 




DSI_IRQSTATUS 

DSI_IRQ 

dss-160 

1611



WAKEUP_EN 

WAKEUP 

FRAMEDONE_EN 

FRAMEDONE 


....... 

....... 

DISPC_IRQSTATUS 



Figure 7-66 details the interrupt tree for the DISPC and the display subsystem. 

7.3.2.2.1 DISPC Interrupt Request 

Figure 7-66. DISPC and DSS Interrupts Tree 

DSI_IRQSTATUS 

DISPC_IRQ 

DSI_IRQ 

DSS_IRQSTATUS 

DSS_IRQ 

The interrupt line indicates when one or more events are detected by the hardware. Each event is 

independently maskable by setting the DSS.DISPC_IRQENABLE register. 

To check when a particular interrupt event occurs and to reset a particular event, the 

DSS.DISPC_IRQSTATUS register must be accessed. This register regroups all the status of the module 

internal events that generate an interrupt (read 0: No interrupt occurred; read 1: Interrupt occurred; write 1: 

Status bit reset). See Section 7.7, Display Subsystem Register Manual, for more information on checking 

and clearing interrupt events. 

Table 7-22 lists the display subsystem interrupt events. 

Interrupt Name Description 

Table 7-22. Display Subsystem Interrupts 

FRAMEDONE Active frame is complete and LCD output is disabled. 

VSYNC VSYNC interrupt occurred at the end of the frame. 

EVSYNC_EVEN (1) EVSYNC_EVEN interrupt occurred at the end of the frame. (EVSYNC is received 

and the field polarity is even.) 

EVSYNC_ODD (1) EVSYNC_ODD interrupt occurred at the end of the frame. (EVSYNC is received 

and the field polarity is odd.) 

ACBIASCOUNTSTATUS The ac-bias transition counter decremented to 0. 

PROGRAMMEDLINENUMBER The LCD reached the user-programmed line number. 

GFXFIFOUNDERFLOW The input graphics FIFO goes underflow. 

GFXENDWINDOW The screen reached the end of the graphics window. All data for the graphics 

window are fetched from memory and displayed on the screen. 

PALETTEGAMMALOADING The palette/gamma table is loaded. 

OCPERROR L3 interconnect sent SResp = ERR. 

VID1FIFOUNDERFLOW The input video1 FIFO goes underflow. 

(1) EVYNC interrupts (EVSYNC_EVEN and EVSYNC_ODD) are external interrupts received by the display controller and generated 

by the video encoder (VENC) module. 



dss-161



Table 7-22. Display Subsystem Interrupts (continued) 


VID1ENDWINDOW The screen reached the end of video1 window. All data for the video window are 

fetched from the memory and displayed on the screen. 

VID2FIFOUNDERFLOW The input video2 FIFO goes underflow. 

VID2ENDWINDOW The screen reached the end of video2 window. All data for the video window are 

fetched from the memory and displayed on the screen. 

SYNCLOST Interrupt occurs when VSYNC width/front or back porches are not wide enough to 

load the pipelines with data (LCD output). 

SYNCLOSTDIGITAL Interrupt occurs when the display controller is not ready to output data when a 

digital request occurs. This interrupt informs that the timings of the NTSC/PAL 

video encoder are not set correctly. 

WAKEUP Occurs when the wakeup signal is asserted 

NOTE: To clear a synchronization lost interrupt, follow this sequence: 

1. Clear the DSS.DISPC_CONTROL[0] LCDENABLE (LCD: SYNCLOST interrupt) or 

DSS.DISPC_CONTROL[1] DIGITALENABLE (TV: SYNCLOSTDIGITAL interrupt) bits. 

Check the interrupts. 

LCD: Verify that a FRAMEDONE interrupt occurs. 

TV : Verify that EVSYNC_EVEN or EVSYNC_ODD interrupts occur. 

2. Set the DSS.DSS_SYSCONFIG[1] SOFTRESET bit to reset the display subsystem. 

3. Set the display subsystem registers again. 

NOTE: The SYNCLOSTDIGITAL interrupts, which occur before the first VSYNC pulse signal (from 

the video encoder), must not be considered. 

7.3.2.2.2 DSI Interrupt Request 

After the first VSYNC pulse signal, the SYNCLOSTDIGITAL interrupt status bit must be 

cleared by writing 1 in the DSS.DISPC_IRQSTATUS[15] SYNCLOSTDIGITAL bit; then the 

SYNCLOSTDIGITAL interrupt can be enabled by setting the DSS.DISPC_IRQENABLE[15] 

SYNCLOSTDIGITAL bit. 

The DSI protocol engine requires a single interrupt line, DSI_IRQ. The DSS.DSI_IRQSTATUS register 

indicates the general interrupt events. See Table 7-23. Each VC and complex I/O has a dedicated 

interrupt register: DSS.DSI_VCn_IRQSTATUS and DSS.DSI_COMPLEXIO_IRQSTATUS respectively. 

See Table 7-24 and Table 7-25. 

Table 7-23 indicates the DSI global interrupt events. 


Table 7-23. DSI Global Interrupts 

RESYNCHRONIZATION_IRQ Resynchronization in video mode 

TA_TO_IRQ Turn-around timer expired 

LDO_POWER_GOOD_IRQ Signal LDOPWRGOOD from the DSI_PHY changes its state for the supply 

VDDALDODSIPLL from up to down or down to up. 

SYNC_LOST_IRQ Synchronization with video mode port is lost (video mode only) 

ACK_TRIGGER_IRQ Acknowledge trigger is received 

TE_TRIGGER_IRQ Tearing effect trigger is received 

WAKEUP_IRQ Occurs when the SWakeUp signal is asserted 

HS_TX_TO_IRQ High speed TX Time-out Interrupt 

LP_RX_TO_IRQ Low speed RX Time-out Interrupt 






Table 7-23. DSI Global Interrupts (continued) 

COMPLEXIO_ERR_IRQ Error signaling from complex I/O: The interrupt is triggered when any error is 

received from the complex I/O (events are defined in 

DSI_COMPLEXIO_IRQSTATUS). 

PLL_RECAL_IRQ PLL recal event (assertion of DSIRecal signal from the DSI PLL Control module) 

PLL_UNLOCK_IRQ PLL unlock event (deassertion of DSILock signal from the DSI PLL Control 

module) 

PLL_LOCK_IRQ PLL lock event (assertion of DSILock signal from the DSI PLL Control module) 

VIRTUAL_CHANNEL3_IRQ Virtual channel #3 

Error signaling from DSI Virtual Channel3: The interrupt is triggered when an error 

is received from DSI Virtual Channel3 (events are defined in 

DSI_VC3_IRQENABLE). 













Table 7-24 indicates the DSI complex I/O interrupt events. 


Table 7-24. DSI Complex I/O Interrupts 

ULPSActiveNot_ALL0_IRQ All signals ULPSActiveNOT are 0 

ULPSActiveNot_ALL1_IRQ All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit 

being high are high 

STATEULPS3_IRQ Lane #3 in ultralow-power state 



ERRCONTROL3_IRQ Control error for lane #3 



ERRESC3_IRQ Escape entry error for lane #3(edge trigger interrupt) 

ERRESC2_IRQ Escape entry error for lane #2 (edge trigger interrupt) 

ERRESC1_IRQ Escape entry error for lane #1 (edge trigger interrupt) 

ERRCONTENTIONLP1_1_IRQ Contention LP1 error for lane #1 






ERRSYNCESC3_IRQ Low power Data transmission synchronization error for lane #3 



NOTE: The error contention signals for DX and DY signals of each lane are ORed together. 

Table 7-25 indicates the DSI VCs interrupt events 






Table 7-25. DSI Virtual Channel Interrupts 

ECC_CORRECTION_IRQ Indicates if a 1-bit error correction occurred using the ECC 

PACKET_SENT_IRQ Indicates that a packet has been sent. It is used when BTA manual mode is used 

CS_IRQ Virtual channel - Check-Sum of the payload mismatch detection 

FIFO_RX_OVF_IRQ RX FIFO overflow. The FIFO used on the L4 interconnect slave port for buffering 

the data received on the DSI link has overflowed 

FIFO_TX_OVF_IRQ TX FIFO overflow. The FIFO used on the L4 interconnect slave port for buffering 

the data received on the L4 interconnect slave port has overflowed 

BTA_IRQ Bus turnaround is received from the peripheral (the VC ID used for the last BTA 

request transfer to the peripheral is used to determine which VC is used to flag 

the interrupt) 

ECC_NO_CORRECTION_IRQ ECC error (short and long packets). No correction of the header because of more 

than 1-bit error 

FIFO_TX_UDF_IRQ TX FIFO underflow. The FIFO used on the slave port for buffering the data 

received on the L4 interconnect port has under-flowed in the middle of a packet 

transfer 



1615

L3 

interconnect 

L4 

interconnect 


controller 

Registers 

Configuration 

LCD data 

L4 interface 

Registers 

DSI protocol 

engine 

Configuration, 

data 


Display Subsystem Functional Description www.ti.com 

7.4 Display Subsystem Functional Description 

This section describes the functions of the LCD and TV display supports by describing the following 

modules: display controller, DSI protocol engine, DSI PLL controller, DSI complex I/O, RFBI and video 

encoder. 

The functions of the display controller are common to both LCD and TV data paths; the RFBI are 

LCD-specific; and the video encoder functions are specific to the TV set. 

7.4.1 Block Diagram 

Figure 7-67 is a schematic of the display subsystem. 

7.4.2 Display Controller Functionalities 

Figure 7-67. Display Subsystem Full Schematic 


LCD data 

Configuration, data 

Field_ld 

Digital data 

24 

Configuration 

Data 

Control 

24 

TV encoder 

Video 

encoder 

Registers 

Remote 

frame buffer 

interface 

Registers 

10 

10 

DAC1 

DAC2 


DSI PLL 

controller 

LCD output 

Composite or 

Luma video 

output 

Chroma video 

output 

Status 

PLL control 

LCD output 

DSI PLL 

The display controller can read and display the encoded pixel data stored in memory (see Figure 7-68). 



dss-037

L3 

interconnect 

L4 

interconnect 

OCP master port arbitrator 

OCP 

slave port 

L3 clock 

domain 

DMA engine 

GFX 

FIFO 

@G 

Video1 

FIFO 

@G 

Video2 

FIFO 

@G 

DMA 

registers 


registers 

L4 clock 

domain 

/24 

½/4/8-Bpp 

24 

24 

16 


clock domain 

Video2 pixel(V2) 

Video1 pixel(V1) 

Graphics pixel(G) 

0 

1 

Color space 

conversion 

/ 

Extend 

/ 

24 

Color space 

conversion 

16 

/ 

Extend 

/ 

24 

12/16-Bpp 

Control 

24 

Palette/gamma 

256 x 24 bits 

Extend 

Graphics path 

Video1 path 

1 

0 

1 

0 

/ 

Video2 path 

/ 

24 

Up/downsampling 

Up/downsampling 


1 

0 

1 

0 

24 

YUV2RGB Re-sampling 

@G: Address generator 


www.ti.com Display Subsystem Functional Description 

Figure 7-68. Display Controller Architecture Overview 

1 

0 

/ 

(V2) 

(V1) 

(G) 

/ 

24 

(V2) 

(V1) 

(G) 

Overlay 

manager 

Color key 

Background color 

0 

1 

2 

3 

Background color 

0 

1 

2 

3 

Color key 

Overlay 

manager 

0 

1 

Palette 

or 

gamma 

Color 

phase 

rotation 

matrix 

TFT color 

depth 

Display controller boundary 

12 

Spatial/ 

temp 

dither 

STN 

dither 

STN-TFT path 

12/16/18-Bpp 

Digital path 

FIFO 

24 

Functional clock 

1 

0 

TDM 

STN/TFT 

output 

Timings 

generator 

LCD pixel data[23:0] 

1 

0 

Line trigger 

Digital pixel data[23:0] 

Input 

control signals 

Output 

control signals 

Several processes can be configured to manage the graphics pipeline (palette, gamma table correction) 

and video pipeline (color space conversion, upsampling, downsampling, overlay, and transparency 

features). 

The internal timing generator logic generates the LCD input signals. The external timing generator 

generates the appropriated signals to drive the digital output. The data from the two overlay managers are 

sent on the two concurrent 24-bit buses outside the display controller module. The memory accessed by 

the display controller is either the SDRAM memory or the SRAM memory. 



dss-038 

1617

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P31 

P30 

P29 

P28 

P27 

P26 

P25 

P24 

P23 

P22 

P21 

P20 

P19 

P18 

P17 

P16 

P15 

P14 

P13 

P12 

P11 

P10 

P9 

P8 

P7 

P6 

P5 

P4 

P3 

P2 

P1 

P0 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P24 

P25 

P26 

P27 

P28 

P29 

P30 

P31 

P16 

P17 

P18 

P19 

P20 

P21 

P22 

P23 

P8 

P9 

P10 

P11 

P12 

P13 

P14 

P15 

P0 

dss-T039 

P1 

P2 

P3 

P4 

P5 

P6 

P7 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P7 

P6 

P5 

P4 

P3 

P2 

P1 

P0 

P15 

P14 

P13 

P12 

P11 

P10 

P9 

P8 

P23 

P22 

P21 

P20 

P19 

P18 

P17 

P16 

dss-T040 

P31 

P30 

P29 

P28 

P27 

P26 

P25 

P24 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P0 

P1 

P2 

P3 

P4 

P5 

P6 

P7 

P8 

P9 

P10 

P11 

P12 



7.4.2.1 Display Modes 

7.4.2.1.1 LCD Output 

The display subsystem supports two types of display technologies (both monochrome and color modes): 

• Passive matrix displays 

• Active matrix displays 

The passive matrix display mode supports 3375 possible colors, allowing 16, 256, or 3375 colors to be 

displayed in each frame, depending on the color depth. The monochrome LCD has 15 grayscale levels 

available. 

In active matrix display mode, the configuration of colors depends on the color depth: 

• 24 BPP supports 16,777,216 colors. 

• 18 BPP supports 262,144 colors. 

• 16 BPP supports 65,536 colors. 

• 12 BPP supports 4096 colors. 

7.4.2.1.2 Digital Output 

The digital output is always a 24-bit RGB value based on an external pixel request. 

7.4.2.2 Graphics Pipeline 

The graphics pipeline is connected to the graphics FIFO controller for the input port and to the two overlay 

managers (LCD and digital). It consists of one 256-entry palette and some programmable replication logic. 

The replication logic is used to convert the RGB pixels, excluding the RGB24 format, into RGB24 format 

based on user programming (replication of the most-significant bits [MSBs] for the RGB24 LSBs or use of 

0s). The first unit connected to the input port of the graphics pipeline is the replication logic used for RGB 

pixels, then the second unit is the palette for concerned pixels. 

7.4.2.2.1 Graphics Memory Format 

The supported formats for the graphics layer are CLUT bitmaps (1-, 2-, 4-, and 8-BPP) and true color 

bitmaps in RGB formats (12-, 16-, and 24-BPP [packet and nonpacket RGB24]) and in ARGB or RGBA 

formats (ARGB 16-, and 32-BPP, and RGBA 32-BPP) as follows: 

• BITMAP 1-BPP data memory organization (CLUT) (little endian) 

• BITMAP 1-BPP data memory organization (CLUT) (little endian + nibble mode) 

• BITMAP 1-BPP data memory organization (CLUT) (big endian) 

• BITMAP 1-BPP data memory organization (CLUT) (big endian + nibble mode) 

P13 

P14 

P15 

P16 

P17 

P18 



P19 

P20 


P21 

P22 

P23 

P24 

P25 

P26 

P27 

P28 

P29 

P30 

dss-T060 

P31 

dss-T061

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P12 P13 P14 P15 P8 P9 P10 

P11 

P4 P5 P6 P7 P0 

P0 

P1 P2 P3 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P3 P2 P1 P0 

P7 P6 P5 P4 

P11 P10 P9 P8 

dss-T041 

dss-T042 

P15 P14 P13 P12 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Pixel 7 Pixel 6 Pixel 5 Pixel 4 Pixel 3 Pixel 2 

Pixel 1 

Pixel 0 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Pixel 6 Pixel 7 




31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 




dss-T043 

dss-T044 


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Pixel 0 



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


Pixel 0 

Pixel 7 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

dss-T045 

Pixel 0 Pixel 1 Pixel 2 Pixel 3 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused R1 G1 B1 Unused R0 G0 B0 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


dss-T046 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R1 G1 B1 












• RGB 12-BPP data memory organization (little endian) 

• RGB 12-BPP data memory organization (big endian) 




R0 

G0 


B0 

dss-T048 

dss-T062 

dss-T063 

dss-T064 

dss-T065 

dss-T066 

dss-T067 

1619



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R0 G0 B0 R1 G1 

• ARGB 16-BPP data memory organization (little endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

A1 R1 G1 B1 A0 R0 G0 B0 

• ARGB 16-BPP data memory organization (big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

dss-T049 

A0 R0 G0 B0 A1 

R1 G1 

B1 

• RGB 24-BPP data memory organization (little or big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused R G 

B 

• ARGB 32-BPP data memory organization (little or big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

A R G 

• RGBA 32-BPP data memory organization (little or big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R G B 

• RGB 24-BPP packet data memory organization (little or big endian) 

B 

A 

dss-T050 

dss-T051 

dss-T052 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

B1 R0 G0 B0 

G2 B2 R1 G1 

R3 G3 B3 R2 

7.4.2.2.2 Color Look-Up Table/Gamma Table 

The graphics path supports the palette/gamma table. Figure 7-69 shows the internal architecture of the 

color look-up/gamma table. 

The palette is split into three memories of 256-bit x 8-bit entries. For bitmap (CLUT) indexes, the same 

value (1-, 2-, 4-, or 8-BPP) indexes the three memories. For gamma curve correction, each R, G, and B 

component indexes the corresponding memory to combine the three gamma curve values into a 24-bit 

value. The table can be reloaded every frame, once or never (at the beginning of the frame before 

fetching the pixels for the graphics and/or video windows). 



+0x0 

+0x4 

+0x8 

dss-T053 

B1 

dss-T070 

dss-T069

24 

/ 

1, 2, 4, and 8 BPP 

Palette 

or 

gamma 

Display controller palette/gamma boundary 

RGB 

Index 

/ 8 

/ 8 

/ 8 

0 

1 



7.4.2.2.2.1 Color Look-Up Table 

Figure 7-69. Palette/Gamma Correction Architecture 

0 

1 

Palette/gamma logic 

0 

1 

R CLUT 

(256 x 8 bits) 

G CLUT 

(256 x 8 bits) 

B CLUT 

(256 x 8 bits) 

The palette mode uses the encoded pixel values from the input graphics FIFO as pointers to index the 

24-bit-wide palette: 1-BPP pixels address 2 palette entries, 2-BPP pixels address 4 palette entries, 4-BPP 

pixels address 16 palette entries, and 8-BPP pixels address 256 palette entries. 

When a palette entry is selected by the encoded pixel value, the content of the entry is sent to the 

color/grayscale space/time base passive matrix dithering circuit, or to the color time base active matrix 

dithering circuit. 

In color mode, the value within the palette is made up of three 8-bit fields, one for each color component 

(red, green, and blue). For color operation, an individual frame is limited to a selection of 256 colors (the 

number of palette entries). The format of one of the palette values in the memory is as follows: 

• 24-BPP Data Memory Organization (Little Endian or Nibble) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused R G B 

In monochrome mode, only one 8-bit value is present. 

• 24-BPP Data Memory Organization (Little Endian or Nibble) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused Unused Unused Gray 

After passing through the palette, 256 gray scales and 16,777,216 colors are numbers obtained. A 

redundancy introduced in the dithering logic step reduces these numbers when displaying. For passive 

matrix panels, the colors are limited to 15 gray scales and 3375 colors. 

• Passive matrix technology 

The palette is bypassed in 12, 16, and 24 BPP. The palette is not used. 




/ 8 

/ 8 

/ 8 

/ 24 

dss-054 

1621



The palette is bypassed in 12, 16, and 24 BPP, allowing up to 2 24 = 16,777,216 colors to be displayed. 

7.4.2.2.2.2 Gamma Table 

In the gamma curve mode, the selected encoded pixel values based on the color keys from the video or 

graphics paths are sent to the gamma curve table. The mode is available only if the color look-up palette 

is not used for graphics. The output of the gamma curve processing is always sent to the LCD output. It is 

not available on digital output. 

Each component of encoded pixel value is used as a pointer to index 1 out of 256 24-bit gamma curve 

entries in the table. Each 8-bit component is replaced with the 8-bit table value corresponding to an R, G, 

or B component. The format of one of the gamma curve values in the memory is as follows: 

• 24-BPP Data Memory Organization (Little or Big Endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused Gamma-R Gamma-G Gamma-B 

7.4.2.2.2.2.1 Replication Logic 

The replication logic increases the color depth of the graphics and video encoded pixels (from true color 

RGB 12-, and 16-BPP to 24-BPP). The encoded value is shifted to the 24-bit alignment. The MSB bits are 

copied to the LSB missing ones. Then the graphics are merged with the video data based on the 

transparency color keys. When the replication logic is not selected, the encoded pixel values are shifted to 

the MSB boundary of the 24-bit format. The missing bit values are filled up with 0s. 

This is an example for RGB16 extension: 

• Original 16-BPP data: 

• If replication logic is ON: 

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 

dss-T055 

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R4 R3 R2 R1 R0 R4 R3 R2 G5 G4 G3 G2 G1 G0 G5 G4 B4 B3 B2 B1 B0 B4 B3 B2 

• If replication logic is OFF: 

7.4.2.3 Video Pipeline 

dss-T056 

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R4 R3 R2 R1 R0 0 0 0 G5 G4 G3 G2 G1 G0 0 0 B4 B3 B2 B1 B0 0 0 0 

The video pipeline is connected to the video FIFO controller for the input port and to the two overlay 

managers (LCD and digital). It consists of the Re-Sampling unit, the Color Space Conversion Unit, and 

some programmable replication logic. The replication logic is used to convert the RGB pixels, excluding 

the RGB24 format, into RGB24 format based on user programming (replication of the MSBs for the 

RGB24 LSBs or use of 0s). The first unit connected to the input port of the video pipeline is the 

Re-Sampling Unit, then the replication logic used for RGB pixels, then the Color Space Conversion Unit 

for YUV4:2:2 pixels. 

7.4.2.3.1 Video Memory Formats 

The display subsystem supports the following formats for the video layer: YUV2, UYVY, RGB12, RGB16, 

RGB24 (non-packed and packed formats), ARGB16 (video channel 2 only), ARGB32 (video channel 2 

only), and RGBA32 (video channel 2 only). 



dss-T057

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


dss-T046 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R1 G1 B1 







R0 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R0 G0 B0 R1 G1 

• ARGB 16-BPP data memory organization (little endian + video 2 channel only) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

A1 R1 G1 B1 A0 R0 G0 B0 

• ARGB 16-BPP data memory organization (big endian + video 2 channel only) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

G0 

B0 

dss-T048 

dss-T049 

A0 R0 G0 B0 A1 

R1 G1 

B1 

• RGB 24-BPP data memory organization (little or big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Unused R G 

B 

• RGB 24-BPP packet data memory organization (little or big endian) 

dss-T050 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

B1 R0 G0 B0 

G2 B2 R1 G1 

R3 G3 B3 R2 

• ARGB 32-BPP data memory organization (little or big endian + video 2 channel only) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

A R G 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

R G B 

B 

A 

dss-T051 

• RGBA 32-BPP data memory organization (little or big endian + video 2 channel only) 

• UYVY 4:2:2 data memory organization (little endian) 

dss-T052 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Y1 Cr0 Y0 Cb0 

• UYVY 4:2:2 data memory organization (big endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

dss-T058 

+0x0 

+0x4 

+0x8 

dss-T053 

Cb0 Y0 Cr0 Y1 

• YUV2 4:2:2 data memory organization (little endian) 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Cr0 Y1 Cb0 Y0 

• YUV2 4:2:2 data memory organization (big endian) 



dss-T059 

B1 

dss-T067 


dss-T069 


1623

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Line n 

Line n 

Y0 Cb0 Y1 Cr0 

Image data line (0- and 180- degree rotation) 

Last Pixel 

Image data line 

(90- and 270degree 

rotation) 

Line n 

½ ½ 1 

Line n+1 



7.4.2.3.2 Color Space Conversion 

The color space conversion module converts the video-encoded pixel values from YCbCr 4:2:2 format into 

RGB24. Figure 7-70 and Figure 7-71 detail the YCbCr 4:2:2 conversion to YCbCr 4:4:4 depending on the 

rotation parameters. 

Figure 7-70. YCbCr 4:2:2 to YCbCr 4:4:4 (0- or 180-Degree Rotation) 

Line n+2 

Line n+3 

YUV4:2:2 

YUV4:4:4 

Luminance sample (Y) 

Chrominance sample (Cb) 

Chrominance sample (Cr) 

Figure 7-71. YCbCr 4:2:2 to YCbCr 4:4:4 (90- or 270-Degree Rotation) 

Luminance sample (Y) 

Chrominance sample (Cb) 

Chrominance sample (Cr) 

The interpolation of the missing chrominance component is given by the equation in Figure 7-72. 

Figure 7-72. Interpolation of the Missing Chrominance Component 

Cb n ( YCbCr 444) 

 

Cbn 

1( 

YCbCr 422) 

Cb n 1 

( YCbCr 422) 

(n odd) 

2 

Crn 

( YCbCr 444) 

 

Cr n 1 

( YCbCr 422) 

Cr n 1 

( YCbCr 422) 

(n odd) 

2 

First, to convert the YCbCr 4:2:2 encoded pixel values into YCbCr 4:4:4 format, the missing chrominance 

samples (Cb and Cr) are interpolated using the average values of the two closest values on the same line 

(1/2, 1/2) or are repeated from the second pixel in the same 32-bit container. 

• In case of rotation 0-degree, for the last pixel, the chrominance samples are duplicated using the 

values from the previous pixel; otherwise, the chrominance samples are averaged using the two 

adjacent values. 

• In case of 180-degree rotation, for the first pixel the chrominance samples missing are duplicated from 

the adjacent pixel; otherwise, the chrominance samples are averaged using the two adjacent values. 

• In case of rotation 90- and 270-degree, the missing chrominance components are duplicated from the 

adjacent pixel in the same 32-bit container. 



dss-E062 

dss-061 

dss-060 

dss-T072

R 

G 

B 

= 

1 

256 

* 

RY 

GY 

BY 



In case of 5-tap configuration for the vertical filtering, the missing chrominance samples are always 

duplicated using the second chrominance samples in the same 32-bit value. 

Then the pixels are converted from YCbCr color space into the RGB color space, because the output 

format of the color space conversion is RGB24 (8-bit value per component: Red, green, and blue). The 

following matrices show the 11-bit coefficients registers used to convert from YCbCr 4:4:4 into RGB24. 

Users set the coefficients according to the standard used to encode the pixel data in YCbCr color space. 

In case of resampling, the YUV4:2:2 format is converted into YUV4:4:4. The YUV4:2:2-to-YUV4:4:4 

processing is bypassed in the color space conversion unit. 

If the active range for the luminance samples (Y) is [16:235] and [16:240] for the chrominance samples 

(Cb and Cr), the values of R, G, and B output components are clipped to the range [0:255]. The equation 

shown in Figure 7-73 gives the 11-bit coefficients of the YCbCr to RGB color space conversion. 

Figure 7-73. YCbCr to RGB Registers (VIDFULLRANGE = 0) 

RCr 

GCr 

BCr 

RCb 

GCb 

BCb 

* 

Y 

dss-E063 

If the active range for the luminance samples (Y) and chrominance samples (Cb and Cr) is [0:255], the 

values of R, G, and B output components are clipped to the range [0:255]. The equation shown in 

Figure 7-74 gives the 11-bit coefficients of the YCbCr-to-RGB color space conversion. 

Figure 7-74. YCbCr to RGB Registers (VIDFULLRANGE = 1) 

Cr – 128 

Cb – 128 

Figure 7-75 describes the computation for the calculation of the R component. The same computation 

applies for the G and B components: 



dss-E064 

1625

RY 

11-bit (signed) 

Y 

8-bit (unsigned) 

i −2 

–16 or 0 

RCb 


Adder 


Cb 


Shifted value (right by 8) 


Clipping to [0:255] 


R component 


RCr 


2 

( ) = ∑ ( Φ) 

( + ) 7 

i 

For the horizontal up/downsampling, the equation is R component with five taps): 

Rout n ( Ci x Rin n i ) 

dss-E066 



7.4.2.3.3 Hardware Cursor 

Figure 7-75. Color Space Conversion Macro-Architecture 

Cr 


–128 –128 

The video layer can be used to display the hardware cursor. The encoded pixel data for the cursor image 

are in RGB12, RGB16 or RGB24 formats and the color space conversion block is bypassed. The 

transparency color key can be used when a non rectangle shape is used. 

The alpha blending can be used to show a partial transparent cursor. When the alpha blender is enabled, 

the graphics layer is on top of the video layers. The cursor uses the graphics layer. The pixel alpha 

blending or the transparency color key can be used. 

7.4.2.3.4 Up-/Down-Sampling 

The video layer has a dedicated resizing block to upsample and downsample the video-encoded pixels. 

The supported input formats from memory are RGB24, RGB16, and YUV4:2:2 

(RGB12 and all the alpha formats like ARGB and RGBA are not supported) 

Users must set the right size and position of the original video before resizing for the 

upsampled/downsampled video to be inside the display screen boundaries. 

The filtering applies on each component independently R, G, and B). 

For the vertical up/downsampling, the equation is R component with three taps): 



dss-065 

(7)

1 

( ) = ∑ ( Φ) 

( ) >> 7 

i 

n ( Ci Rin n i ) 

Rout x 

i = −1 

dss-E067 

2 

( ) = ∑ ( Φ) 

( ) 7 

 

For the vertical up/downsampling, the equation is R component with five taps): 

i 


i= 

−2 

Ci( Φ) 

dss-E069 : FIR filter coefficients 

Video picture 

Memory 

dss-E068 



Rout: R component output 

Rin: R component input (9) 

The pixel (n + 1) is older than pixel (n). The line (n + 1) is older than line (n). 

NOTE: The coefficients Ci() depend on the phase between input and output pixels. 

NOTE: If the 5-tap resizer is used for RGB16 and YUV4:2:2 picture formats, the width of the input 

picture must be a multiple of 2 pixels and more than 5 pixels: 

DISPC_VIDn_ATTRIBUTES[21] VIDVERTICALTAPS == 1 

DISPC_VIDn_PICTURE_SIZE[10:0] VIDORGSIZEX 4 and even 

Figure 7-76 shows an example of video upsampling. 

Filter Description 

Figure 7-76. Video Upsampling 

LCD panel 

Programmable 

background default 

color value 

Video window 

The up/downsampling filter is a poly-phase filter with five taps and eight phases for the horizontal filter and 

a programmable number of taps (three or five) and eight phases for vertical filter. The upsampling ratio is 

up to x8. The downsampling ratio using 3-tap configuration is/2. The downsampling ratio using 5-tap 

configuration is/4. The vertical filter is first applied to the encoded input pixel data; and then the horizontal 

filter is applied on the resulting pixel values to generate the output pixel values. Figure 7-77 shows the 

computation for the R component in the case of three coefficients (vertical filtering). The same 

computation applies to the G and B components. 



dss-070 

(8) 

1627

Coef(n – 1) 


R (n – 1) 


Coef(n) 


R (n) 


Adder 






R component for pixel n 


DISPC DISPC_SIZE_LCD 

_ LCD _ SIZE. PPL 

h _ ratio 

DISPC _VID _ SIZE. VidSizeX 

DISPC _VID _ PICTURE _ SIZE. VidOrgSizeY 

v _ ratio 

DISPC _VID _ SIZE. VidSizeY 

v _ ration 

Ratio 

2 h _ ratio 



Figure 7-77. Resampling Macro-Architecture (3-Coefficient Processing) 

v _ ration v _ ration 2 

Ratio max( , ) 

2 h _ ratio 2 ( h _ ratio 1) 

If 

If 

Coef(n + 1) 


1 v _ ratio 2 

12 v _ ratio 4 

DISPC _VID _ PICTURE _ SIZE. VidOrgSizeX 

Ratio 

DISPC _VID _ SIZE. VidSizeX 

dss_swpu108-E136 

dss_swpu108-E135 

R (n + 1) 


To determine if the minimum functional clock matches the down sampling ratio and the desired Pixel 

clock, the following formula must be used in conjunction with Table 7-26 and Table 7-27. 

Ratio V when performing a vertical down-sampling only 

NOTE: For frequency ratio calculation on the TV output, it is correct to replace DISPC_SIZE_LCD 

with DISPC_SIZE_DIG. 

When the down-sampling ratio is below 0.5, it is not possible to use a video in full screen. 

Ratio H when performing a horizontal down-sampling only 

Ratio H+V when performing a horizontal and vertical down-sampling 

Ratio = max (horizontal Ratio, vertical Ratio) as previously defined. 



dss-071



Table 7-26. Functional Clock Frequency Requirement in RGB16 YUV4:2:2—Active Matrix Display 

Minimum Functional Clock 

Horizontal Resampling 

(MHz) Off Up 1:1 – 1:2 1:2 – 1:3 1:3 – 1:4 

Vertical Off AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK 

Resamplin 

g 

Up AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK 

3-tap 1:1 to 1:2 2xPCLK 2xPCLK 4xPCLK 6xPCLK 8xPCLK 

5-tap 1:1 to 1:4 RatioxPCLK RatioxPCLK RatioxPCLK RatioxPCLK RatioxPCLK 

With A = 1 in case all the data and synchronization signals are asserted and deasserted on the rising 

edge of the PCLK; otherwise, A = 2. 

Table 7-27. Functional Clock Frequency Requirement in RGB24—Active Matrix Display 

Minimum Functional Clock 

Horizontal Resampling 

(MHz) Off Up 1:1 – 1:2 1:2 – 1:3 1:3 – 1:4 

Vertical Off AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK 

Resamplin 

g 

Up AxPCLK AxPCLK 2xPCLK 3xPCLK 4xPCLK 

3-tap 1:1 to 1:2 2xPCLK 2xPCLK 4xPCLK 6xPCLK 8xPCLK 

5-tap 1:1 to 1:4 RatioxPCLK RatioxPCLK 2xRatioxPCLK 2xRatioxPCLK 2xRatioxPCLK 

With A = 1 in case all the data and synchronization signals are asserted and deasserted on the rising 

edge of the PCLK; otherwise, A = 2. 

Use case example: 

An input picture of 1024*768 is scaled to an output picture of size of 800*600 and displayed onto a LCD of 

resolution1280*768 at a PCLK of 74.25 MHz with a DSS functional clock of 133 MHz. 

In this example, a H+V down-sampling is done on the input picture. Firstly the Ratio V and H are 

determined and the resulting maximum value is taken to calculate the functional clock frequency required. 

Ratio V: h_ratio = 1.6 and v_ratio = 1.28 then Ratio = 0.4 

Ratio H: Ratio = 1.28 

Ratio H+V: Ratio = max (1.28, 0.4) = 1.28 

In this use case, the horizontal and vertical down sampling range are 1:1–1:2. The 3-tap or 5-tap 

configuration can be taken into consideration. Therefore, from Table 7-26 and Table 7-27, If in 

RGB16-YUV4:2:2: 

• 3-taps → DSS functional clock = 4 * PCLK = 297 MHz 

• 5-taps → DSS functional clock = Ratio * PCLK = 95.36 MHz 

If in RGB24, 

• 3-taps → DSS functional clock = 4 * PCLK = 297 MHz 

• 5-taps → DSS functional clock = 2 * Ratio * PCLK = 190.72 MHz 

In this use case, the pixel format supported is RGB16-YUV4:2:2 in a 5-tap configuration. 

7.4.2.4 Overlay Support 

CAUTION 

Enabling overlay optimization (setting the DSS.DISPC_CONTROL [12] 

OVERLAYOPTIMIZATION bit) if no overlay region effectively exists (the 

DSS.DISPC_VIDn_ATTRIBUTES [0] VIDENABLE bit is cleared, with n = 1, 2) 

leads to unpredictable behavior. The overlay optimization feature must be 

enabled only when an overlay area exists. Before enabling the overlay 

optimization, the DSS.DISPC_GFX_WINDOW_SKIP[31:0] GFXWINDOWSKIP 

bit field must be first set according to the video1 and graphics windows overlap. 



1629

Video1 

Video2 



The overlay mechanism consists of displaying more than one layer (graphics and video layers) using rules 

based on priority and transparency color keys. 

When the pixel format is ARGB or RGBA, the color key match logic uses only the RGB value defined by 

ARGB or RGBA. The alpha blending factor is ignored. 

The overlay managers are based on the same rules for priority and transparency color keys (see 

Figure 7-80). 

Each data pipeline is assigned a single overlay related to a single display controller output. 

The overlay manager is connected to all three outputs of the pipelines (graphics, video1 and video2). The 

output of the LCD overlay manger is connected to the Spatial/Temporal Dithering, and Passive Matrix 

units and back to the palette unit in the case of Gamma correction. 

7.4.2.4.1 Priority Rule 

The overlay manager can be configured in two distinct modes: 

• Alpha mode (only source color key with the graphics layer) 

• Normal mode (no alpha support) 

The following rules apply in normal mode: 

The video1 layer is always on top of the graphics layer. The video2 layer is always on top of the video1 

and graphics. The display controller reads the data for each buffer from the system memory and, 

depending on the transparency color key values, displays either the pixels in the video layer, the pixels in 

the graphics layer, or the solid background color. 

Each layer can have any size up to full-display screen. If there are no graphics or video-encoded pixels at 

a specific position, the programmable, solid background color appears (see Figure 7-82). 

Figure 7-78. Overlay Manager in Normal Mode 

Layer composition by hardware 



Video1 

Video2 


(0,0) 

Gfx window height 

y 

(x,y) 

Display width 

Gfx window width 


Graphics 

Video1 

Video2 

Video1 window width 

Video2 

window 

width 

x 



The following rules apply in alpha mode: 

Figure 7-79. Display Attributes in Normal Mode 

Video1 window 

Additional display attributes: 

height 

•type (STN/TFT, mono/color) 

•depth 

•background color 

•timings 

Display height 

Additional video/graphics attributes: 

•format 

•base address 

•row skip 

•pixel skip 

•transparency color key 

•rotation 

Video2 

window 

height 

view 

graphics 

video2 

video1 background layers 

The video2 layer is always on top of the video1 layer. The graphics layer is always on top of the video1 

and video2. The display controller reads the data for each buffer from the system memory and, depending 

on the transparency color key values, displays either the pixels in the video layer, the pixels in the 

graphics layer, or the solid background color. 

Each layer can have any size up to full-display screen. If there are no graphics or video-encoded pixels at 

a specific position, the programmable, solid background color appears (see Figure 7-82). 




1631

Gfx window height 

(0 ,0 ) 

y 

GFX 

Memory 

Palette 

Video1 

Video2 

(x ,y ) 

Display width 

Gfx window width 

Video1 


Graphics 

Display controller boundary 

Layer composition by hardware 

Rules: graphics always on top of video2, 

video2 always on top of the video1, 

video1 always on top of the background 

color (when no transparency color key 

enabled and match) 

Video2 

Video1 window width 

Video2 

window 

width 

Register 

programmable background color 

x 



Figure 7-80. Overlay Manager in Alpha Mode 

Video1 layer 

Screen 

Video1 

Video2 

Graphics layer 

(always on top of 

the video) 

Figure 7-81. Display Attributes in Alpha Mode 

Additional display attributes: 

• type (STN/TFT, mono/color) 

• depth 

• background color 

• timings 

Additional video/graphics attributes 

• format 

• base address 

• row increment 

• pixel increment 

• transparency color key 

• rotation 

Figure 7-82 shows the alpha blending processing in detail. 

Video1 window height 

Display height 

Video2 

window 

height 

GFX 

graphics 

video2 

video1 

view 

Programmable 

background color 

key (default) 

Video2 layer 

dss-163 

background layers 



dss-164

GFX RGB 

GFX 

absent 

or match 

Color 

key 

GFXGlobalα 

register 

x 

x 

GFXα 

0 

V2 RGB 

1-α 

DISPC_GFX_ATTRIBUTES[28] 

PREMULTIPLYALPHA 

+ 



Figure 7-82. Alpha Blending Macro Architecture with Pre-multiplied Alpha Support 

V2Globalα 

register 

x 

V2α 

x 

x 

0 

1-α 

+ 

V2 

absent 

DISPC_VID2_ATTRIBUTES[28] 


NOTE: "1-alpha" operator corresponds to the basic 1's complement operation. 

V1 RGB 

x 

Background 

color register 

V1 

absent 

Alpha blender 

The pre-multiplied alpha option is accessible through DSS.DISPC_GFX_ATTRIBUTES[28] 

PREMULTIPLYALPHA and DSS.DISPC_VIDn_ATTRIBUTES[28] PREMULTIPLYALPHA registers bits. 

The following settings are available: 



dss-165 

1633



• PREMULTIPLYALPHA bit = '0' : Source is not pre-multiplied with alpha. Full blending is done in the 

DISPC. 

• PREMULTIPLYALPHA bit = '1' : Source is pre-multiplied with alpha. Partial blending is done. 

NOTE: The pre-multiplied alpha option is only valid when bit fields 

DSS.DISPC_GFX_ATTRIBUTES[4:1] GFXFORMAT and 

DSS.DISPC_VIDn_ATTRIBUTES[4:1] VIDFORMAT, respectively, are set to ARGB or RGBA 

formats. Otherwise, the PREMULTIPLYALPHA bit fields are ignored by the hardware. 

The alpha blending value is defined by the pixel value (ARGB or RGBA formats). A global alpha blending 

value can be defined and used in combination with the pixel alpha blending value. If the pixel format 

contains no alpha blending value, the pixel alpha value is considered to be 0xFF. 

In case of ARGB-444, the alpha blending is defined using a 4-bit value. It is converted into an 8-bit value 

by duplicating the 4-bit value. Table 7-28 details the alpha blending 4-bit values and the corresponding 

blending percentage. 

Table 7-28. Alpha Blending 4-Bit Values 

Alpha Blending 4-Bit Value (ARGB-444) Alpha Blending 8-Bit Value % Blending 

(Converted Value) 

0x0 0x00 100% (transparent) 

0x1 0x11 93.33% 

0x2 0x22 86.6% 

... ... ... 

0xE 0xEE 6.6% 

0xF 0xFF 0% (opaque) 

7.4.2.4.2 Transparency Color Keys 

7.4.2.4.2.1 Normal Mode 

This section describes the features available in normal mode. 

The two transparency color keys are the video source transparency color key and the graphics destination 

transparency color key. The encoded pixel color value is compared to the transparency color key. For 

CLUT bitmaps, the palette index is compared to the transparency color key and not to the palette value 

pointed out by the palette index. 

NOTE: The video source transparency color key and graphics destination transparency color key 

cannot be active at the same time. 

• Video source transparency color key value: 

The video source transparency color key value defines the encoded pixel data considered as the 

transparent pixel. The encoded pixel values with the source color key value are pixels not visible on 

the screen, and the underlayer encoded pixel values or solid background color are visible. 

The video source transparency color key can be used only if the color space conversion and the 

up/down-scaling modules are disabled. The format of the data is RGB 16. (This feature handles the 

hardware cursor displayed by one of the video layers.) 

To enable the video source transparency color key, set to 0x1 the DSS.DISPC_CONFIG[11] 

TCKLCDSELECTION bit for LCD output or the DSS.DISPC_CONFIG[13] TCKDIGSELECTION bit for 

digital output. Program the DSS.DISPC_CONFIG[10] TCKLCDENABLE bit (LCD output) or the 

DSS.DISPC_CONFIG[12] TCKDIGENABLE bit (digital output) to enable or disable the transparency 

color key. 

An example is shown in Figure 7-83: The video source transparency is applied on video1 (VID1) and 

video2 (VID2) layers. The pixels with the transparency color key are not displayed; instead, underlying 

layers are shown. 





Figure 7-83. Video Source Transparency Example 

GFX VID1 VID2 

Transparency color key 

• Graphics destination transparency color key value: 

The graphics destination transparency color key value defines the encoded pixels in the video layers to 

be displayed. The encoded pixel values with the destination color key value are pixels not visible on 

the screen and the pixels different from the transparency color key are displayed over the video layers. 

The destination transparency color key is applicable only in the graphics region when graphics and 

video overlap; otherwise, the destination transparency color key is ignored. 

To enable the graphics destination transparency color key, set to 0x0 the DSS.DISPC_CONFIG[11] 

TCKLCDSELECTION bit for LCD output or the DSS.DISPC_CONFIG[13] TCKDIGSELECTION bit for 

digital output. Program the DSS.DISPC_CONFIG[10] TCKLCDENABLE bit (LCD output) or the 

DSS.DISPC_CONFIG[12] TCKDIGENABLE bit (digital output) to enable or disable the transparency 

color key. 

An example is shown in Figure 7-84: The destination transparency is applied on graphics (GFX) layer 

and the pixels without the transparency color key are displayed over the overlying layers. 




1635



7.4.2.4.2.2 Alpha Mode 

Figure 7-84. Graphics Destination Transparency Example 

GFX VID1 VID2 

This section describes the features available in alpha mode. 

Transparency color key 

Only the graphics source transparency color key is available The encoded graphics pixel color value is 

compared to the transparency color key. The encoded pixel values with the source transparency key are 

not visible and the under-layer encoded pixel values or solid background color are visible. To enable the 

graphics source transparency color key, set to 0x0 the DSS.DISPC_CONFIG[11] TCKLCDSELECTION bit 

for LCD output or the DSS.DISPC_CONFIG[13] TCKDIGSELECTION bit for digital output. Program the 

DSS.DISPC_CONFIG[10] TCKLCDENABLE bit (LCD output) or the DSS.DISPC_CONFIG[12] 

TCKDIGENABLE bit (digital output) to enable or disable the transparency color key. In the case of CLUT 

bit maps, the palette index is compared to the transparency color key and not the palette value pointed out 

by the palette index. 

7.4.2.4.3 Overlay Optimization (Only Available in Normal Mode) 

The display controller can be configured to take advantage of the fact that the graphics pixels under video 

window 1 are not visible when the transparency color key is not used. The optimization can be selected to 

reduce the bandwidth used to fetch the pixels for graphics. The color key must be disabled. The graphics 

pixels under the video window 1 are not fetched from system memory. At least the video window 1 and 

the graphics window must be enabled. The following graphic formats are supported: RGB (RGB16 and 

RGB24 packed and unpacked), YUV4:2:2, and BITMAP 8. The formats BITMAP 1, 2, and 4 are not 

supported. The video format can be RGB (RGB16, RGB24 packed and unpacked, and YUV4:2:2 formats). 

The DMA engine does not fetch the unnecessary graphics pixels to avoid extra bandwidth use. Only 

visible pixels from graphics and video buffers in system memory are fetched and displayed by the display 

controller. 

7.4.2.5 Active/Passive Matrix Display Data Path 

For active matrix display data path, the following blocks are serial and each of them can be bypassed: 

• Color phase rotation 

• Spatial/temporal dithering 

• Multiple cycle data format 

For passive matrix display data path, the following blocks are serial and each of them can be bypassed: 

• Color phase rotation 




RR 

10-bit signed 

coefficient 

Rout 

 

 

Gout 

 

 

 

Bout 

R 

8-bit 

unsigned 

1 

256 

RR 

 

* 

 

 

 

GR 

 

 

 

BR 

RG 

10-bit signed 

coefficient 



• Spatial/temporal dithering 


7.4.2.5.1 Color Phase Rotation 

The Color Phase Rotation (CPR) can be used to correct the LCD output colorimetry in case of non pure 

white backlight. 

The color phase rotation can be selected for passive matrix and active matrix panel. The logic is 

integrated after the LCD overlay manager or the palette while using the gamma correction and before the 

spatial/temporal dithering. The color phase rotation can be selected to correct the nonpure white backlight 

of the LCD module by using a programmable matrix to convert the 24-bit RGB pixel value into a new 

24-bit RGB pixel value. The matrix is programmed through a set of nine 10-bit signed coefficients. The 

output of the calculation is clipped to [0:255]. The color phase rotation is processed by the equation shown 

in Figure 7-85. 

Figure 7-85. Color Phase Rotation Matrix 

RG 

GG 

BG 

Figure 7-86 shows the color phase rotation macro-architecture. 

7.4.2.5.1.1 Spatial/Temporal Dithering 

Adder 


G 

8-bit 

unsigned 





R component 


RB 

Rin 

 

 

 

GB 

 

 

* 

 

Gin 

 

 

BB 

 

 

Bin 

 

dss-E076 

Figure 7-86. Color Phase Rotation Macro Architecture 

RB 

10-bit signed 

coefficient 

B 

8-bit 

unsigned 

The spatial/temporal dithering logic can be selected for passive matrix and active matrix panel. The 

dithering logic is integrated after the color phase rotation and before the TDM and passive matrix units. 

The spatial/temporal dithering logic can be selected to enhance the quality of the passive matrix and 

active matrix outputs. The dithering logic can process the pixels over a single frame, two frames, or four 

frames. In the case of a single frame, only spatial processing is applied. In the case of multiple frames, 

spatial and temporal processing is applied to the pixels. 

• Passive Matrix Technology: The passive matrix display dithering logic path is used. The 

spatial/temporal dithering logic can be selected. When selected, the pixels are preprocessed by the 

spatial/temporal dithering logic before the passive matrix display dithering logic. The output format of 

the spatial/temporal dithering logic is RGB 12-bit (not configurable). 




1637



• Active Matrix Technology: The encoded pixel values are used by spatial/temporal dithering logic to 

display the data in a lower color depth on the LCD panel. The spatial/temporal dithering algorithm is 

based on the (x,y) pixel position, the value of removed bits and the frame number. The picture quality 

is improved when enabling the spatial/temporal dithering logic. When spatial/temporal dithering is not 

enabled, the three MSBs of the pixel color components are output on the interface data bus if the 

interface data bus is smaller than the pixel format size. If the interface data bus is wider than the pixel 

format size, by programming the pixel components replication active/inactive, the MSB is replicated to 

the LSB of the interface data bus or the LSB is filled with 0s. 

7.4.2.5.2 Passive Matrix Display Dithering Logic 


After the graphics data are merged with the video data from the video layers depending on the 

transparency status, the result is sent to the color/grayscale space-/time-based dither generator. The 

monochrome data and each RGB color component are encoded on 4 bits, which are the 4 MSBs of 

the pixel-encoded component 8-bit value defined by the merge of the graphics data and the video data. 

These 4-bit values are used to select on the 16 intensity levels. The gray/color intensity is controlled by 

turning individual pixels on and off at varying period rates, making the average time the pixel is off 

longer than the average time the pixel is on, thus producing more intense grays/colors. The dithering 

generator also uses the intensity of adjacent pixels in the calculation to give the screen image a 

smooth appearance. The proprietary dither algorithm is optimized to provide a range of intensity values 

that matches the visual perception of color/gray graduations. 


The passive matrix dithering logic is always bypassed in active displays. 

NOTE: If the interface data bus is smaller than the pixel format size, dithering logic can be enabled. 

If the interface data bus is wider than the pixel format size, the dithering logic cannot be 

enabled and replication feature can be used. 

7.4.2.5.3 Passive Matrix Display Output FIFO 


The display controller contains a 2-entry by 8-bit-wide output FIFO used to store pixel data before it is 

driven out to the LCD pins. Each time a modulated pixel value is output from the dither generator, it is 

placed into a serial shifter. The shifter can be configured to be 4 or 8 bits wide. Single-panel 

monochrome screens use either four or eight data lines; single-panel color screens use eight data 

pins. 


The output FIFO is bypassed in active matrix mode. 

7.4.2.5.4 Multiple Cycle Output Format 

The pixels after the active matrix display processing are formatted on one or multiple cycles (from one to 

three cycles). The interface width can be 8-, 9-, 12-, or 16-bit. On three cycles, two pixels can concatenate 

and send to the panel. When the TDM is disabled, the display controller outputs the pixels using the 

conventional formats: Passive matrix display/active matrix display monochrome/color. 

The following example shows an output configuration based on the interface width (8-bit) and the pixel 

format output (24-bit) (also see Table 7-29): 

• The DSS.DISPC_CONTROL[24:23] TDMCYCLEFORMAT bit field is set to 0x2 (three cycles for one 

pixel). 

• The DSS.DISPC_DATA_CYCLEk (k=0) register is set to 0x00000008 (8 bits from pixel 1 for the first 

cycle). 

• The DSS.DISPC_DATA_CYCLEk (k=1) register is set to 0x00000008 (8 bits from pixel 1 for the 

second cycle). 

• The DSS.DISPC_DATA_CYCLEk (k=2) register is set to 0x00000008 (8 bits from pixel 1 for the third 

cycle). 





Table 7-29. 8-Bit Interface Configuration/24-Bit Mode 

24-Bit Mode 

1st Cycle 2nd Cycle 3rd Cycle 

Data[7] R0[7] G0[7] B0[7] 

Data[6] R0[6] G0[6] B0[6] 

Data[5] R0[5] G0[5] B0[5] 

Data[4] R0[4] G0[4] B0[4] 

Data[3] R0[3] G0[3] B0[3] 

Data[2] R0[2] G0[2] B0[2] 

Data[1] R0[1] G0[1] B0[1] 

Data[0] R0[0] G0[0] B0[0] 

7.4.2.6 Video Line Buffer 

The line buffer size is 1024 x 24-bit. There are six line buffers (1024 x 24-bit) that can be merged into 

three lines (2048 x 24-bit). Table 7-30 lists the maximum width depending on the TAP configuration and 

the pixel format. 

Table 7-30. Maximum Width Allowed 

Vertical Tap Pixel Format Maximum Width (Pixels) 

3 RGB16 2048 

RGB24 

YUV4:2:2 

5 RGB16 1024 

7.4.2.7 Synchronized Buffer Update 

RGB24 

YUV4:2:2 

A synchronization mismatch between the frame buffer and the display refreshes, named tearing effect, 

can lead to images that appear to be stretched on the screen. To avoid this, a synchronization mechanism 

is needed between the display controller and the process that updates the buffer. An interrupt is generated 

when the display reaches a predefined line number. This PROGRAMMEDLINENUMBER interrupt is a 

level signal and stays active during the programmed line of the display. 

7.4.2.8 Rotation 

In case of SDRAM buffer, the display controller accesses the encoded pixels in burst, always considering 

the consecutive data in memory. The rotation engine (VRFB) in the SDRAM scheduler (SDRC) is in 

charge of translating the addresses from virtual to physical SDRAM addresses (see Chapter 10, Memory 

Subsystem). 

Rotation using the SMS-VRFB rotation engine is supported for BITMAP8, RGB12 (16-bit container), 

ARGB16, RGB16, RGB24 (using 32-bit container), ARGB32, RGBA32, and YUV4:2:2 (YUV2 and YUYV). 

The BITMAP1, BITMAP2, BITMAP4, and RGB24 (using 24-bit container) formats are not supported. 

NOTE: For good performance in the L3 interconnect and for SDRAM efficiency, it is highly 

recommended to use the VRFB rotation engine when possible and not the display 

subsystem DMA engine to rotate the frame buffer. 

A VID DMA optimization is available to optimize the memory traffic (DDR memory) when 90- and 

270-degree rotation is required. This optimization consists of reconstructing the RGB16 and YUV line 

pixels using the cache capability of the DISPC scaler line buffers. 

The pixel formats that can take advantage of the reduction in memory traffic are: 

• YUV4:2:2 



1639



• RGB16 (no reduction is possible for RGB24 packed and unpacked formats) 

The benefits of the video DMA optimization, when the feature is enabled, are: 

• The L3 interconnect traffic is reduced by a factor of 2x (only for YUV4:2:2 pixel format) 

• The DDR memory traffic is reduced by a factor of 2x (for YUV4:2:2 and RGB16 pixel formats) 

For more information about the configuration settings for video DMA optimization, see Section 7.5.3.4.5, 

Video DMA Optimization. 

NOTE: The DMA optimization feature must be used only for YUV and RGB16 formats when 90- or 

270-degree rotation is required. In all other configurations, the 

DISPC_VIDn_ATTRIBUTES[20] VIDDMAOPTIMIZATION bit must be kept at reset value 

(0x0). 

7.4.2.9 Multiple Buffer Support 

Users update the base address of the buffer when the update of the working buffer has finished and is 

ready to be displayed. The register that contains the base address of the buffer is a shadow register that 

is read by the hardware at the next Vertical Front Porch (VFP). 

7.4.3 DSI Protocol Engine Functionalities 

NOTE: Copyright ©2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member 

Confidential. 

The DSI protocol engine integrates DSI interface to the display through the DSI DSI_PHY module, L4 

interconnect interface and video interface from the display controller. The DSI DSI_PHY or complex I/O 

module is detailed in Section 7.4.5. The DSI transmitter (protocol engine + PHY) port can be connected to 

multiple displays using a single DSI host port. The DSI protocol engine controls the DSI PLL control 

module detailed in Section 7.4.4. The DSI transmitter port can be used in video mode or/and command 

mode. 

7.4.3.1 DSI Protocol Architecture 

The DSI protocol engine receives data from the video port and/or the L4 interconnect slave port, 

encapsulates them with the VC ID, generates the ECC and check-sum, and splits the data into byte 

stream to the DSI_PHY to be sent using the low-speed (LS) or high-speed (HS) protocol. The DSI protocol 

engine receives data and acknowledge from the display using the same DSI link in case of bidirectional 

display. Multiple data streams can be interleaved to support multiple panels connected to the same host 

DSI port. Figure 7-87 details the DSI protocol engine architecture. 



Video interface 

(data [23:0], HS, VS, CLK, 

PCLK, DE) 

Interface 

protocol 

STALL 

FIFO 

Data 

handler 

Data 

handler 


Low– level protocol 

Registers - control logic 

OCP 

slave 



Figure 7-87. DSI Protocol Engine 

SINTERRUPT 

Lane splitter 

DMA_Req[3:0] 

CTRL 

PPI 

Serializer 

Serializer 

Clock 

DSI_PHY 


Lane 1 

Lane 2 

DDR clock 

NOTE: The order of the PHY pairs (clock and data lanes) is informative. Each PHY pair can be 

Clock or Data. The DSI complex I/O receives the configuration for pin order and the 

differential +/- in a pair from the settings in DSS.DSI_COMPLEXIO_CFG1 register. 

DSI_PHY 

The DSI serial interface is a bidirectional differential serial interface with data/clock for the physical layer 

(configured in unidirectional link in case the display module is only unidirectional). The maximum DSI data 

transfer capacity is 900 Mbps per channel. The speed of the link can be software configured only when 

the DSI_PHY is in stop state or in ULPS. 

Figure 7-88 shows the DSI transmitter/receiver high-level data flow. 



dss-166 

1641

DSI 

protocol 

engine 

DSI_PHY 

Transmitter Receiver 

Application 

Video mode data stream of 16,18, 

Application 

Pixel Control or 24 bits 

Command mode stream 

Pixel Control 

Pixel Control 

Pixel to byte 

Data formats 

Pixel 

Control 

Byte to pixel 

packing formats 

unpacking formats 

Data Control Data Control 

8 bits 8 bits 

Data Control Data 


Data Control 

8 bits 

Lane management 

layer 

N * 8 bits 



7.4.3.2 Clock Requirements 

Figure 7-88. DSI Transmitter/Receiver Data Flow 

Packet-based protocol 

Arbitrary data support 

Lane distribution/lane merging 


Lane management 

layer 

Data Control 

Generation/detection of packet start 

and stop signaling 

Data Control 

PHY layer 

Serializer/deserializer 

Clock generation/recovery (DDR) 

Electrical layer 

PHY layer 

High-speed unidirectional clock 

Lane 0 – High-speed data (optionally bidirectional in LP mode) 

Lane 1 – High-speed unidirectional data 

Lane N – High-speed unidirectional data 

Data Control 

8 bits 

N * 8 bits 

Control 

The serial clock generated by the DSI host and sent to the display can be a continuous clock. The clock 

lane supports clock transmission even there is no data to send for displays that require continuous clock. 

It is software programmed through the DSS.DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON bit: This bit 

can be programmed only when the interface is disabled (that is, DSS.DSI_CTRL[0] IF_EN bit set to 0). 

The peripheral can use two different kinds of clocks. The first one is the DDR clock provided on the clock 

lane. The second clock is some transitions on the data lane 1 even if there is no valid data to send using 

low power mode. 

The LP clock (TxClkEsc) frequency provided to the DSI complex I/O is in the range of 67% to 150% of the 

peripheral Low-Power (LP) clock frequency. It is generated internally by the DSI protocol engine module 

using the DSI functional clock. The DSI functional clock is divided by 1, 2, 3, up to 8191 using the value 

programmed in the DSS.DSI_CLK_CTRL[12:0] LP_CLK_DIVISOR bit field. The LP clock generated from 

DSI functional clock must be in the range of 20 MHz down to 32 KHz. The duty cycle must be 50/50 

(tolerance of 45/55 for maximum value). LP clock frequency visible on the pads (DP xor DN) is half the 

frequency of TxClkEsc. 

The DSS.DSI_CLK_CTRL[20 ] LP_CLK_ENABLE bit is used to enable or disable the clock. When 

disabled, the value of DSS.DSI_CLK_CTRL[12:0] LP_CLK_DIVISOR bit field is ignored and does not 

have to be programmed by software users. 



dss-167

CLK REQUEST 

CLK READY 

DATA REQUEST 

DATA READY 

CLK LANE 

CLK STATE 

LP 

DATA LANE 

DATA STATE 

ENTER 

HS 

ZERO 

LP 

T LPX TCLK-PREPARE T CLK-ZERO 

DDR_CLK_PRE 



7.4.3.2.1 Timing Parameters for an LP to HS Transaction 

Figure 7-89 shows the timing requirement when switching the data and clock lane state from LP to HS. 

Table 7-31 lists the LP to HS timing parameters. 

Figure 7-89. LP to HS Timing 

CLK 

ON 

T CLK-PRE T LPX THS-PREPARE 

Table 7-31. LP to HS Timing Parameters 

ENTER 

HS 

ENTER_HS_MODE_LATENCY 

ZERO 

T HS-ZERO 

HS 

PACKET 

Registers/Associated Bit 

Timing Description Register Settings Timing Seen on the Line 

Fields 

Length of any CEIL (2 * 

DSI_PHY_REGISTER1[20:16] CEIL (25 ns / 

TLPX low-power state REG_TLPXBY2/4) * 4 * 

REG_TLPXBY2 DDR_Clock_Period) 

period DDR_Clock_Period 

T CLK-PREPARE 

T CLK-ZERO 

The value set in this bit field is 

half of the T LPX 

Time to drive the CLK 

lane to LP-00 state, to DSI_PHY_REGISTER2[7:0] CEIL (65 ns / 

prepare for HS clock 

transmission 

REG_TCLKPREPARE DDR_Clock_Period) 

Time to drive the CLK 

lane to HS-0 state, DSI_PHY_REGISTER1[7:0] CEIL (265 ns / 

before starting the 

clock 

REG_TCLKZERO DDR_Clock_Period) 

dss-325 

REG_TCLKPREPARE * 

DDR_Clock_Period + (~– 

25 ns – +5 ns) 

{CEIL [(REG_TCLKZERO 

+ 3)/4] * 4 + CEIL 

(REG_TCLKPREPARE/4) 

* 4 – 

REG_TCLKPREPARE + 

2} * DDR_Clock_Period + 

(~ 0 ns – +5 ns) 



1643



Table 7-31. LP to HS Timing Parameters (continued) 



Fields 

TCLK-PRE Time that the HS 

clock must be driven 

before any associated 

data lane begins the 

transition from LP to 

HS mode 

N/A N/A 

DDR_CLK_PRE - TLPX - 

TCLK-PREPARE - TCLK-ZERO T HS-PREPARE 

T HS-ZERO + T HS-PREPARE 

Time to drive the data 

lane to LP-00 state, to DSI_PHY_REGISTER0[31:24] CEIL (70 ns / 

prepare for HS packet 

transmission 

REG_THSPREPARE DDR_Clock_Period) + 2 

REG_THSPREPARE * 

DDR_Clock_Period + 

(–26.5 ns – +4 ns) 

THS-ZERO: Time to drive 

{CEIL [(N + 3)/4] * 4 + 

the data lane to HS-0 

DSI_PHY_REGISTER0[23:16] CEIL (175 ns / CEIL (M/4) * 4 + 3} * 

state before the 

REG_THSPRPR_THSZERO DDR_Clock_Period) + 2 DDR_Clock_Period + (~ – 

synchronous 

29 ns – 0 ns). 

sequence 

DDR_CLK_PRE 

Time between the 

CLK lane request 

assertion and the 

data request assertion 

DSI_CLK_TIMING[15:8] 

DDR_CLK_PRE 

CEIL [(TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE) / 

TxByteClkHS] (1)(2) 

to switch the data 

lanes to HS 

ENTER_HS_MODE_ Time to enter data 

LATENCY (3) lane into HS mode 

DSI_VM_TIMING7[31:16] CEIL [(TLPX + THS-PREPARE + 

ENTER_HS_MODE_LATENC THS-ZERO) / TxByteClkHS] 

(1) 

Y 

Where 

N = 

REG_THSPREPARE_TH 

SZERO – 

REG_THSPREPARE 

M = REG_THSPREPARE 

(1) The timings seen on the line should be used to determine the register value. 

(2) See the MIPI D-PHY specification for the TCLK-PRE value. 

(3) ENTER_HS_MODE_LATENCY timing applies only to video mode. It does not need to be programmed in command mode. 

In the example in Table 7-32, the DDR clock = 400 MHz; TxByteClkHS = 100 MHz. 

Table 7-32. LP to HS Timing Parameters Example for 400-MHz DDR Clock 

Default Register Settings 

Timing Registers/Associated Bit Fields Timing Seen on the Line 

(Programmed at Reset) 

DSI_PHY_REGISTER1[20:16] 

T LPX 10 50 ns 

REG_TLPXBY2 


T CLK-PREPARE 26 40–70 ns 

REG_TCLKPREPARE 


T CLK-ZERO 106 280–285 ns 

REG_TCLKZERO 

T CLK-PRE (1) 

N/A N/A 80 ns 


T HS-PREPARE 30 48.5–79 ns 

REG_THSPREPARE 


T HS-ZERO 72 178.5–207.5 ns 

REG_THSPRPR_THSZERO 


DDR_CLK_PRE 45–49 (2) 450–490 ns 

DDR_CLK_PRE 

ENTER_HS_MODE_ DSI_VM_TIMING7[31:16] 

24 * TxByteClkHS or 112 * 

DDR_CLOCK 

LATENCY ENTER_HS_MODE_LATENCY 34 * TxByteClkHS or 136 * 

DDR_CLOCK (2) 

(1) See the MIPI D-PHY specification for the TCLK-PRE value. 

(2) The register setting is calculated based on the values in the Timing Seen on the Line column. 

277–336.5 ns 



CLK REQUEST 

CLK READY 

DATA REQUEST 

DATA READY 

CLK SIGNAL 

CLK LANE 

DATA LANE 

DATA STATE 

HS 

PACKET 

EoT 

T HS-EOT 

if enable 

TRAIL 

EXIT 

HS 

T HS-TRAIL 

CLK 

ON 

T HS-EXIT 

EXIT_HS_MODE_LATENCY 

DDR_CLK_POST 

T CLK-POST 



7.4.3.2.2 Timing Parameters for an HS to LP Transaction 

Figure 7-90 shows the timing requirement when switching the state of the data and clock lanes from HS to 

LP. Table 7-33 lists the HS to LP timing parameters. 

Figure 7-90. HS to LP Timing 

TRAIL 

EXIT 

HS 

LP 

T CLK-TRAIL 



LP 

T HS-EXIT 

ENTER 

HS 

dss-326 

1645



Table 7-33. HS to LP Timing Parameters 



Fields 

If EoT is enabled, a 

delay is added to 

EXIT_HS_MODE_LAT 

T HS-EOT ENCY to send the EoT N/A N/A 

T HS-TRAIL 

T HS-EXIT 

packet. The EoT period 

depends on the 

number of data lanes. 

Thus: 

DIVROUNDUP (4, 

NB_DATA_LANES) 

One data lane = Four 

DDR clocks 

Two data lanes = Two 

DDR clocks 

Time to drive flipped 

{CEIL [(REG_THSTRAIL 

differential state after 

DSI_PHY_REGISTER0[15:8] CEIL (60 ns / + 3)/4] * 4 – 2.75} * 

last payload data bit of 

REG_THSTRAIL DDR_Clock_Period) + 5 DDR_Clock_Period + (~ 0 

an HS transmission 

ns– 5 ns) 

burst 

[CEIL (REG_THSEXIT/4) 

Time to drive data lane 

DSI_PHY_REGISTER0[7:0] CEIL (145 ns / * 4] * 

to LP-11 state, after HS 

REG_THSEXIT DDR_Clock_Period) DDR_Clock_Period – (~ 3 

burst 

ns– 45 ns) 

Time that the 

transmitter must 

continue sending HS 

T CLK-POST clock after the last N/A N/A 

T CLK-TRAIL 

associated data lane 

has transitioned to LP 

mode 

DDR_CLK_POST – 

(1) THS-EOT – THS-TRAIL 

Time to drive HS 

{CEIL [(REG_TCLKTRAIL 

differential state after 

DSI_PHY_REGISTER1[15:8] CEIL (60 ns / + 3)/4] * 4 – 1.5} * 

last payload clock bit of 

REG_TCLKTRAIL DDR_Clock_Period) + 2 DDR_Clock_Period + (~ 0 

a HS transmission 

ns–5 ns) 

burst 

DDR_CLK_POST 

Time between the data 

lane request 

deassertion and the 

CLK request 

deassertion to switch 

the data lanes into LP DSI_CLK_TIMING[7:0] 

(1) 

CEIL [(THS-TRAIL + THS-EOT + TCLK-POST) / 

mode. The DDR_CLK_POST 

DDR_CLK_POST 

value must follow the 

rule: DDR_CLK_POST 

≥ T HS-TRAIL + T HS-EOT + 

T CLK-POST 

TxByteClkHS] (2)(3) 

CEIL [(THS-TRAIL + THS-EXIT + 

EXIT_HS_MODE_ DSI_VM_TIMING7[15:0] 

(1) 

Time to exit HS mode THS-EOT ) / TxByteClkHS] 

LATENCY (4) EXIT_HS_MODE_LATENCY (2) 

(1) If T HS-EOT is enabled 

(2) The timings seen on the line should be used to determine the register value. 

(3) See the MIPI D-PHY specification for the TCLK-POST value. 

(4) EXIT_HS_MODE_LATENCY timing applies only to video mode. It does not need to be programmed in command mode. 

In the example in Table 7-34, the DDR clock = 400 MHz; TxByteClkHS = 100 MHz; two data lanes. 

Table 7-34. HS to LP Timing Parameters Example for 400-MHz DDR Clock and Two Data Lanes 

Timing Seen on the 

Registers/Associated Bit Default Register Settings Timing Seen on the Line 

Timing Line 

Fields (Programmed at Reset) (THS-EOT Enabled) 

(THS-EOT Disabled) 

T HS-EOT N/A N/A 5 ns N/A 





Table 7-34. HS to LP Timing Parameters Example for 400-MHz DDR Clock and Two Data Lanes 

(continued) 

Timing Seen on the 

Registers/Associated Bit Default Register Settings Timing Seen on the Line 

Timing Line 

Fields (Programmed at Reset) (THS-EOT Enabled) 

(THS-EOT Disabled) 


T HS-TRAIL 29 73.125–78.125 ns 73.125–78.125 ns 

REG_THSTRAIL 


T HS-EXIT 58 105–147 ns 105–147 ns 

REG_THSEXIT 

T CLK-POST (1) N/A N/A 585 ns 580 ns 


T CLK-TRAIL 26 76.25–81.25 ns 76.25–81.25 ns 

REG_TCLKTRAIL 

DDR_CLK_POST 


DDR_CLK_POST 


DDR_CLOCK – 


DDR_CLOCK 

658.125–663.125 ns 653.125–658.125 ns 

(2) 

EXIT_HS_MODE_ DSI_VM_TIMING7[15:0] 


DDR_CLOCK – 

LATENCY EXIT_HS_MODE_LATENCY 24 * TxByteClkHS or 96 * 

DDR_CLOCK (2) 

183.125–230.125 ns 178.125–225.125 ns 

(1) See the MIPI D-PHY specification. 

(2) The register setting is calculated based on the values in the Timing Seen on the Line (THS-EOT Enabled) column. 

7.4.3.2.3 Extra LP Transitions 

Some DSI receivers require extra clock cycles in LP mode to process the data. The DSI protocol engine 

can be programmed to send automatically one NULL long packet. It applies only when no more data are 

ready to be sent from the internal FIFO to the peripheral on the last low speed transfer. The same value is 

used for all the VCs sending packets in low speed mode. 

The size of the payload is defined by the DSS.DSI_CLK_CTRL[17:16] LP_CLK_NULL_PACKET_SIZE bit 

field. The header value depends on the VC ID and the size of the payload as detailed in Table 7-35 and 

Table 7-36. 

Table 7-35. Extra NULL Packet Header 

Virtual Payload size Header Header (2nd Byte): WC Header (3rd Byte): WC Header (ECC) 

Channel ID (DSI_CLK_CTRL[17:16] (1st Byte) LSB MSB 

LP_CLK_NULL_PACKE 

T_SIZE) 

0 0x0 0x9 

0x0 1 0x9 0x1 0x13 

2 0x2 0x2F 

3 0x3 0x35 

0 0x0 0x1F 

0x1 1 0x49 0x1 0x05 

2 0x2 0x39 

3 0x3 0x0 0x23 

0 0x0 0x10 

0x2 1 0x89 0x1 0x0A 

2 0x2 0x36 

3 0x3 0x2C 

0 0x0 0x06 

0x3 1 0xC9 0x1 0x1C 

2 0x2 0x20 

3 0x3 0x3A 





Table 7-36. Extra NULL Packet Payload 

Payload size Payload (1st Payload (2nd Payload (3rd byte) Payload (CRC) Payload (CRC) 

(DSI_CLK_CTRL[17:16] byte) byte) LSB MSB 

LP_CLK_NULL_PACKET_ 

SIZE) 

NOTE: 

7.4.3.3 DSI Transfer Modes 

0 NA NA NA 0xFF 0xFF 

1 0 NA NA 0x87 0x0F 

2 0 0 NA 0xB8 0xF0 

3 0 0 0 0x33 0x39 

• In Table 7-35 and Table 7-36, both ECC and checksum are enabled. 

• NA means not available. 

There are two transfer modes supported by the DSI module: 

• Video mode (VM): Pixels are received from the video port, there are some real time constraints (pixels 

must be sent at the pixel frequency required by the display module) for sending the data to the display; 

• Command mode (CM): Pixels can be received from the video port or from the L4 interconnect, there 

are no real time constraints except that TE must be avoided by starting the transfer at the right time 

during scan of the display and should be fast enough. 

7.4.3.3.1 Video Mode 

The video mode refers to the MIPI DPI 1.0 standard. The sync events and pixels must be sent according 

to the display mode timings. Data are received from the video port. The display controller is in charge of 

fetching the data from the system memory and providing the data to the DSI protocol engine using the 

video port. The short packets used for the sync event are using precalculated 32-bit values. The long 

packets are constructed using the header defined in DSS.DSI_VCn_LONG_PACKET_HEADER registers. 

7.4.3.3.2 Command Mode 

The command mode refers to the MIPI DCS standard. The commands, parameters and pixels are sent to 

the display module with limited real time constraints (as defined in Section 7.4.3.3.1). The pixels can be 

provided on the video port by the display controller or on the L4 interconnect port. 

NOTE: In DSI command mode, the display controller must be configured in stall mode by setting 

the DSS.DISPC_CONTROL[11] STALLMODE bit to 1. 

The DSS.DSI_VCn_LONG_PACKET_HEADER registers are used for the header of long packets, the 

DSS.DSI_VCn_SHORT_PACKET_HEADER registers are used for the short packets. 

The error correction code (ECC) can be provided while writing the ECC value directly into the 

DSS.DSI_VCn_LONG_PACKET_HEADER and DSS.DSI_VCn_SHORT_PACKET_HEADER registers. 

The DSS.DSI_VCn_CTRL[8] ECC_TX_EN bit indicates if the ECC value should be calculated or if the 

value written in the register should be used instead for command and video modes. In case of 

synchronization short packets for video mode, since the hardware generates the short packets without 

using DSS.DSI_VCn_SHORT_PACKET_HEADER registers. If the DSS.DSI_VCn_CTRL[8] ECC_TX_EN 

bit is set to 1, the ECC is calculated; otherwise, the value zero is used. The feature is used to generate 

incorrect ECC for debug purpose and to ease the check for the link and peripheral error detection and 

correction. 

For the payload, the DSS.DSI_VCn_LONG_PACKET_PAYLOAD registers are used. Each 32-bit 

PAYLOAD data is written into the DSS.DSI_VCn_LONG_PACKET_PAYLOAD register from the MPU 

subsystem or system DMA. It is buffered to be able to send packets with higher rate than the L4 

interconnect frequency can provide. The word count defined in the 

DSS.DSI_VCn_LONG_PACKET_HEADER registers is used to determine the number of bytes to be sent 





using the DSS.DSI_VCn_LONG_PACKET_PAYLOAD registers. The write into the 

DSS.DSI_VCn_LONG_PACKET_HEADER registers is required before accessing the 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD register. The hardware must be able to extract the length of 

the payload and be able to discard extra data sent using the DSS.DSI_VCn_LONG_PACKET_PAYLOAD 

register. The hardware takes into account the write into the DSS.DSI_VCn_LONG_PACKET_HEADER 

register only if the VC is enabled otherwise the write is ignored by hardware. 

In the case of pixels received on the video port, only the DSS.DSI_VCn_LONG_PACKET_HEADER 

register is used. The video port pixels are used for the payload. When the pixel data is coming from the 

display controller video port, the DSI protocol can add a DCS command byte between the packet header 

and pixel data by setting the DSS.DSI_CTRL[24] DCS_CMD_ENABLE bit to 0x1. The value will be either 

0x2c (write_memory_start) by setting the DSS.DSI_CTRL[25] DCS_CMD_CODE bit to 0x1, or 0x3c 

(write_memory_continue) by setting the DSS.DSI_CTRL[25] DCS_CMD_CODE bit to 0x0. 

When transmitting RGB 16-BPP data, the DSS.DSI_CTRL[26] RGB565_ORDER bit must be set to 0x1 to 

maintain the pixel byte order as in video mode . 

A 2-line ping-pong buffer is implemented to allow the DSI protocol engine to store incoming pixels from the 

display controller through the video port while sending the DSI formatted frame to the DSI_PHY. The 

ping-pong buffer is supported in command mode, provided the size of the packet defined in the header 

register is less than the size of each line buffer (768 *32 bits). If the size of the packet is greater than the 

size of the line buffer, the ping-pong mechanism cannot be used (both lines are used as a single line). 

The ping-pong buffer status can be checked by the DSI_VCn_CTRL[14] PP_BUSY bit. 

• When PP_BUSY equals 1, the ping-pong buffer is active and the line buffers are not ready to receive 

data; therefore, the user cannot update a new header. 

• When PP_BUSY equals 0, at least one line buffer is empty; therefore, the user can update a new 

header. PP-BUSY is then set to 0x1. If both line buffers are empty, the user can write two headers, 

one following the other. PP_BUSY remains at 0x0 after the first header is written, and is set to 0x1 

after second header is written. 

An IRQ is available to allow software to update header on events. The IRQ is enabled by setting the 

DSI_VCn_IRQENABLE[8] PP_BUSY_CHANGE_IRQ bit to 0x1, and its status is accessible on the 

DSI_VCn_IRQSTATUS[8] PP_BUSY_CHANGE_IRQ bit. 

7.4.3.3.3 Video + Command Modes 

The two modes can be interlaced to send two DSI streams to two types of panels: Video or command 

types. The number of concurrent video stream is limited to a single one. The number of concurrent 

command mode streams is limited to 4 when there is no video stream and 3 otherwise. In case there is 

one DSI stream using video mode, the command mode pixels must be provided only on the L4 

interconnect. 

7.4.3.3.4 Burst Modes 

• Frequency-burst mode The frequency-burst mode is used to reduce the high-speed (HS) period by 

increasing the clock frequency on the DSI link. It allows in some case, the power consumption 

reduction of the link. The non-HS period used typically to drive the main panel can be used to send 

data to the secondary panel or to allow feedback (acknowledge) from the primary and secondary 

panels. The DSI protocol engine needs to buffer a full line before sending the HS packets for the line. 

A double buffering mechanism is required to be able to send a line while the following one is being 

received on the video port. 

• Transparent-burst mode The transparent-burst mode is used by increasing the pixel clock frequency 

generated by the display controller with in addition an increase of the horizontal blanking period. 

7.4.3.3.5 Interleaving Mode 

Video mode can output command mode packets, which are provided to DSI through the L4 interconnect, 

during the blanking periods of the video stream sequence on the PPI link. These command mode packets 

can be programmed as high-speed packets or low-power packets. 

During a video stream sequence on the PPI link, four types of gap exist: 



1649



• BLLP gap: Blanking period during VSA, VBP, and VFP lines 

• HSA gap: Blanking period during VACT lines; always between HS and HE short packet 

• HBP gap: Blanking period during VACT lines; always between HS/HE short packet and data pixel long 

packet 

• HFP gap: Blanking period during VACT lines; always between data pixel long packet and the end of 

the current VACT line 

To perform interleaving in a particular gap, video mode must be set to go into low-power state during the 

blanking gap. Each type of gap has separate configurable register bits that determine whether a blanking 

long packet will be sent or the link will go into low-power state during the gap on the PPI link. If low-power 

state is set during a gap, the DSI module performs interleaving during that period. 

Two set of registers are available for: 

• High-speed interleaving (when high-speed command mode packets must be sent during a video 

stream on the PPI link) 

• Low-power interleaving (when low-power command mode packets must be sent during a video stream 

on the PPI link) 

7.4.3.3.5.1 HS Command Mode Interleaving Programming Model 

Figure 7-91 shows the various HS mode scenarios in interleaving mode during a blanking gap. For each 

type of blanking gap, a dedicated bit field determines the number of TxByteClkHS clock cycles used for 

interleaving in HS command mode packets. 

• The BL_HS_INTERLEAVING[31:16] DSI_VM_TIMING6 bit field defines the number of TxByteClkHS 

clock cycles used to interleave HS command mode packets during a BLLP gap. 

• The HBP_HS_INTERLEAVING[7:0] DSI_VM_TIMING4 bit field defines the number of TxByteClkHS 

clock cycles used to interleave HS command mode packets during an HBP gap. 

• The HFP_HS_INTERLEAVING[15:8] DSI_VM_TIMING4 bit field defines the number of TxByteClkHS 

clock cycles used to interleave HS command mode packets during an HFP gap. 

• The HSA_HS_INTERLEAVING[23:16] DSI_VM_TIMING4 bit field defines the number of TxByteClkHS 

clock cycles used to interleave HS command mode packets during an HSA gap. 

These programmable values must be programmed to satisfy the timings for the clock and data lane to 

enter and exit HS mode latency. According to the scenario, different equations must be considered when 

calculating the register values. 



Video 

HS 

packet 

Video 

HS 

packet 

LP state 

LP state 

Command mode 

HS packet 

HS_INTERLEAVING 

enter 

HS 

enter 

HS 

Command mode 

HS packet 


Command mode 

HS packet 




Figure 7-91. HS Command Mode Interleaving 

BLANKING_PERIOD 

exit HS 

mode 

exit HS 

mode 

Command mode 

HS packet 


LP state 

exit HS 

mode 

LP state 

enter 

HS 

LP state 

enter 

HS 

exit HS 

mode 

Video 

HS …(1) 

packet 

…(2) 

Video 

HS …(3) 

packet 

LP state…(4) 

dss-327 

NOTE: For calculations and equations, the following abbreviations are used: EXIT_CLK_HS_MODE 

represents the exit HS mode latency for the clock lane. There is no dedicated register for this 

value but the programmer must know this value for further calculations. 

EXIT_CLK_HS_MODE = T CLK-TRAIL + TH S-EXIT 

For the following equations, BLANKING_PERIOD represents the BLLP, HSA, HBP, or HFP blanking 

periods. The HS_INTERLEAVING period represents the maximal period HS command mode packets. Its 

value is set in the BL_HS_INTERLEAVING, HSA_HS_INTERLEAVING, HBP_HS_INTERLEAVING, or 

HFP_HS_INTERLEAVING registers, depending on the blanking type. 

In each scenario, two calculations are present, depending on the value of ddr_clk_always_on. 

• ddr_clk_always_on = 1: Clock lane is always active. 

• ddr_clk_always_on = 0: Clock lane is activated only when there are HS packets to be sent on the PPI 

link. 

• Scenario 1: The gap for interleaving starts and ends with a regular video stream HS packet. 

– ddr_clk_always_on = 1 

HS_INTERLEAVING = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + max{ 

ENTER_HS_MODE_LATENCY, 2} + 1) 


HS_INTER1 = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + max{ 




1651



HS_INTER2 = BLANKING_PERIOD – (DDR_CLK_POST + EXIT_CLK_HS_MODE + 

DDR_CLK_PRE+ ENTER_HS_MODE_LATENCY + 1) 

HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2} 

• Scenario 2: The gap for interleaving starts with a regular video stream HS packet and ends in LP state. 


HS_INTERLEAVING = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + 3) 


HS_INTER1 = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + 3) 

HS_INTER1 = BLANKING_PERIOD – (DDR_CLK_POST + EXIT_CLK_HS_MODE + 3) 


• Scenario 3: The gap for interleaving starts with the LP state and ends with a regular video stream HS 

packet. 


HS_INTERLEAVING = BLANKING_PERIOD – (ENTER_HS_MODE_LATENCY + 

EXIT_HS_MODE_LATENCY + max{ ENTER_HS_MODE_LATENCY, 2} + 1) 


HS_INTER1 = BLANKING_PERIOD – (DDR_CLK_PRE + ENTER_HS_MODE_LATENCY + 

EXIT_HS_MODE_LATENCY + max{ ENTER_HS_MODE_LATENCY, 2} + 1) 

HS_INTER2 = BLANKING_PERIOD – (DDR_CLK_PRE + ENTER_HS_MODE_LATENCY + 

DDR_CLK_POST + EXIT_CLK_HS_MODE + DDR_CLK_PRE+ ENTER_HS_MODE_LATENCY + 

1) 

HS_INTERLEAVING = min{ HS_INTER1, HS_INTER2}) 


packet. 


HS_INTERLEAVING = BLANKING_PERIOD – (ENTER_HS_MODE_LATENCY + 

EXIT_HS_MODE_LATENCY + 3) 


HS_INTER1 = BLANKING_PERIOD – (DDR_CLK_PRE+ ENTER_HS_MODE_LATENCY + 

EXIT_HS_MODE_LATENCY + 3) 

HS_INTER2 = BLANKING_PERIOD – (DDR_CLK_PRE+ ENTER_HS_MODE_LATENCY + 

DDR_CLK_POST + EXIT_CLK_HS_MODE + 1) 


7.4.3.3.5.2 LP Command Mode Interleaving Programming Model 

Figure 7-92 shows the various LP mode scenarios in interleaving mode during a blanking gap. For each 

type of blanking gap, a dedicated bit field determines the number of TxByteClkHS clock cycles used for 

interleaving in LP command mode packets. 

• BL_LP_INTERLEAVING bit field DSI_VM_TIMING6[15:0] defines the number of TxByteClkHS clock 

cycles used to interleave the HS command mode packets during a BLLP gap. 

• HBP_LP_INTERLEAVING bit field DSI_VM_TIMING5[7:0] defines the number of TxByteClkHS clock 

cycles used to interleave the HS command mode packets during an HBP gap. 

• HFP_LP_INTERLEAVING bit field DSI_VM_TIMING5[15:8] defines the number of TxByteClkHS clock 

cycles used to interleave HS command mode packets during an HFP gap. 

• HSA_LP_INTERLEAVING bit field DSI_VM_TIMING5[23:16] defines the number of TxByteClkHS clock 

cycles used to interleave HS command mode packets during an HSA gap. 

These programmable values must be programmed to satisfy the timings for clock and data lane enter and 

exit LP mode latency. Clock lane timings do not affect LP command mode interleaving, because the clock 

lane can be controlled separately, compared with the data lane high-speed and low-power mutually 

exclusive control. Clock lanes can be in high-speed mode while the data lanes are in high-speed data 

transfer mode, low-power data transfer mode, or in low-power state. 

According to this scenario, different equations must be considered for calculating register values. 



Video 

HS 

packet 

Video 

HS 

packet 

LP state 

LP state 

exit HS 

mode 

exit HS 

mode 

BLANKING_PERIOD 

Period for interleaving 

LP command mode 

packets 

LP_INTERLEAVING 

Period for interleaving LP 

command mode packets 


Period for interleaving LP 

command mode packets 




Figure 7-92. LP Command Mode Interleaving 

LP state 

LP state 

Period for interleaving LP command mode packets 


enter 

HS 

LP state 

enter 

HS 

Video 

HS 

packet 

Video 

HS 

packet 

LP state 

For the following equations, BLANKING_PERIOD represents the BLLP, HSA, HBP, or HFP blanking 

periods. The LP_INTERLEAVING period represents the maximal period in LP command mode packets. Its 

value is set in the BL_LP_INTERLEAVING, HSA_LP_INTERLEAVING, HBP_LP_INTERLEAVING, or 

HFP_LP_INTERLEAVING registers, depending on the blanking type. 

ALLOWED_HSBYTE_CLOCKS_FOR_LP represents the number of TxByteClkHS clock cycles during 

which LP interleaving can appear. 

To calculate the LP_INTERLEAVING value: 

(1) 

(2) 

(3) 

(4) 

dss-328 

1. Calculate how many TxByteClkHS clock cycles can be reserved for LP interleaving during the 

appropriate blanking video mode gap. 

2. Calculate the LP_INTERLEAVING value according to the results of Step 1. 

Step 1: 

• Scenario 1: The gap for interleaving starts and ends with a regular video stream HS packet. 

ALLOWED_HSBYTE_CLOCKS_FOR_LP = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + 

max{ ENTER_HS_MODE_LATENCY, 2} + 1) 

• Scenario 2: The gap for interleaving starts with a regular video stream HS packet and ends in LP state. 

ALLOWED_HSBYTE_CLOCKS_FOR_LP = BLANKING_PERIOD – (EXIT_HS_MODE_LATENCY + 1) 


packet. 



1653

The resulting value must be programmed in the appropriate video mode register for LP interleaving. 

LP_INTERLEAVING < 

Tlp_available 8* Thsbyte_clk Ttxclkesc 

16 

5* Tdsif_clk 26 

 

 

 

 

 



ALLOWED_HSBYTE_CLOCKS_FOR_LP = BLANKING_PERIOD – (max{ 



packet. 

ALLOWED_HSBYTE_CLOCKS_FOR_LP = BLANKING_PERIOD – 1 

After finishing Step 1, the time period available for LP interleaving is known: 

T lp_available = ALLOWED_HSBYTE_CLOCKS_FOR_LP *T TxByteClkHS 

Step 2: 

TxByteClkHS: Period of HS byte clock of DSI_PHY module 

Tdsif_clk: Period of DSI functional clock 

Ttxclkesc: Period of LP transmit escape clock 


 

 

 

 

 

dss-E124 

The DSI protocol engine implements an handshake protocol on its L4 interconnect port with the PRCM. 

The DSI protocol engine provides a clock gating signal CIO_CLK_ICG to gate the L3 interface clock 

(L3_ICLK) provided by the PRCM to the DSI complex I/O. It allows reduction of the power consumption of 

the DSI complex I/O while the DSI link is not in used. To gate the L3_ICLK clock at DSI complex I/O level, 

set the DSS.DSI_CLK_CTRL[14] CIO_CLK_ICG bit to 1. 

7.4.3.5 Serial Configuration Port (SCP) Interface 

The SCP interface is used to transfer register values from the DSI protocol engine to the DSI PLL Control 

module and to the DSI complex I/O. It spends several cycles to serialize the data to be sent. Software 

users must consider the delay in processing the transfer of the data from/to the slave port to/from the 

module. 

7.4.3.5.1 Shadowing Register 

The two first SCP registers for the DSI complex I/O address map must be implemented as shadow 

registers. The shadowing mechanism is enabled/disabled using the DSS.DSI_COMPLEXIO_CFG1[31] 

SHADOWING bit: 

• When setting the DSS.DSI_COMPLEXIO_CFG1[31] SHADOWING bit to 1, the transfer of the values 

from the two first L4 interconnect port registers into the two first registers of the DSI complex I/O 

(DSS.DSI_PHY_REGISTER0 and DSS.DSI_PHY_REGISTER1) is done only when the 

DISPC_UPDATE_SYNC signal from the display controller is active and the 

DSS.DSI_COMPLEXIO_CFG1[30] GOBIT is set to 1. If there is no pending update for the two 

registers, when the DISPC_UPDATE_SYNC signal is asserted, the DSS.DSI_COMPLEXIO_CFG1[30] 

GObit is reset by hardware and there is no SCP transfer. 

– If there is only one register to update, only the corresponding new value is transferred. The second 

register in the DSI complex I/O is not updated. When the transfer is completed, the 

DSS.DSI_COMPLEXIO_CFG1[30] GOBIT is reset by hardware. 

– If the two registers need to be updated, the order of the transfer is first the register with lower 

address and then the second one. When the transfers are completed, the 

DSS.DSI_COMPLEXIO_CFG1[30] GOBIT is reset by hardware. 

When there is an on-going transfer (read or write) to any SCP register, the transfer must complete 

before starting the update of shadowing registers. 

• When unsetting the DSS.DSI_COMPLEXIO_CFG1[31] SHADOWING bit to 0, if the transfer into the 





two first DSI complex I/O registers has already started, it should be finished. 

NOTE: When reading the shadow registers, the local value stored in the DSI protocol engine is 

returned if the update is pending; otherwise, the values stored in the DSI complex I/O are 

returned. 

7.4.3.5.2 Busy Signal 

The signal SCPBusy indicates that there is still some activity using the SCPClk provided by the PRCM. 

The SCPClk clock is the DSS_L3_ICLK clock. 

7.4.3.6 Power Control 

The DSI protocol engine can control and send power commands for both DSI complex I/O and DSI PLL 

controller modules. 

7.4.3.6.1 Complex I/O Power Control Commands 

7.4.3.6.1.1 Complex I/O Power Control Commands 

The DSI complex I/O can be set into three modes: 

• OFF: In this power state, the complete DSI_PHY circuit is powered down. The internal LDO is OFF. 

• ON: In this power state, the complete DSI_PHY circuit is powered on and functional. 

• ULPS: In this power state, the ULPS exit detection circuit power switch is ON for the lanes which are in 

receive ULPS mode. For the lanes which are in transmit ULPS mode, the circuitry for weak pull-down 

is ON. The ultralow-power state should only be used when all the three lanes are in ULPS (transmit or 

receive). 



1655

OFF 

RESET 

DSI_COMPLEXIO_CFG1[28:27] PWR_CMD = 0x1 




7.4.3.6.1.2 Complex I/O Power FSM 

Figure 7-93 describes the power control FSM to control the power state of the complex I/O. 

Figure 7-93. Complex I/O Power FSM 

ON 

DSI_COMPLEXIO_CFG1[28:27] PWR_CMD = 0X0 



ULPS 

The PwrCmdOff, PwrCmdUlp and PwrCmdOn commands control the state transition of the DSI complex 

I/O. Software users must set the DSS.DSI_COMPLEXIO_CFG1[28:27] PWR_CMD bit field to ask for a 

state change. The allowed transitions are: OFF - ON and ON - ULP and ULP - OFF. The 

DSS.DSI_COMPLEXIO_CFG1[26:25] PWR_STATUS bit field gives a status on the current state of the 

DSI complex I/O. 

CAUTION 

• In automatic mode, software must ensure that the DSI complex I/O in the 

ON mode (that is, ON command already sent) before sending requests to 

the complex I/O. 

• In a command request to change to a state which is the current one 

(acknowledge has been received), the command is ignored (nothing is sent 

to the DSI complex I/O). 

• To change state to ULP state, users must ensure that all the three 

ULPSActiveNot signals are low. The ULPSActiveNot_ALL0_IRQ interrupt 

can be used by software users to determine the state of the ULPSActiveNot 

signals. The change from ULP to ON state is required before starting the 

ULP status exit sequence (see Section 7.4.3.7.1 for details). 

7.4.3.6.2 DSI PLL Power Control Commands 

The DSI PLL controller module can be set into four modes: 

• OFF: The DSI PLL and HSDIVIDER are OFF. 

• ON ALL: Both DSI PLL and HSDIVIDER are ON. The HS_CLK clock is provided to the DSI complex 

I/O and the second clock output is provided to the HSDIVIDER. 

• ON HSCLK: The DSI PLL is ON. The HSDIVIDER is OFF. The HS_CLK clock is provided to the DSI 

complex I/O but the second clock output is not provided to the HSDIVIDER. 

• ON DIV: Both DSI PLL and HSDIVIDER are ON. The HS_CLK clock is not provided to the DSI 

complex I/O but the second clock output is provided to the HSDIVIDER. 



dss-169

1 = DSI_CLK_CTRL[31:30] PLL_PWR_CMD = 0x0 (STATE_OFF) 

2 = DSI_CLK_CTRL[31:30] PLL_PWR_CMD = 0x1 (STATE_ON_HSCLK) 

3 = DSI_CLK_CTRL[31:30] PLL_PWR_CMD = 0x2 (STATE_ON_ALL) 

4 = DSI_CLK_CTRL[31:30] PLL_PWR_CMD = 0x3 (STATE_ON_DIV) 

RESET 

OFF 

4 

1 

1 

3 



7.4.3.6.2.1 DSI-PLL Power FSM 

Figure 7-94 shows the DSI PLL power FSM. 

Figure 7-94. DSI PLL Power FSM 

ON DIV 

4 

ON ALL 

3 

2 

2 

1 

4 

3 

2 

ON HSCLK 

The commands PLLPwrCmdOff, PLLPwrCmdOnAll, PLLPwrCmdOnDIV and PLLPwrCmdOnHSClk 

controls the state transition of the DSI PLL control module. Software users must set the 

DSS.DSI_CLK_CTRL[31:30] PLL_PWR_CMD bit field to ask for a state change. The 

DSS.DSI_CLK_CTRL[29:28] PLL_PWR_STATUS bit field gives a status on the current state of the DSI 

PLL controller. 

NOTE: In a command requests to change to a state which is the current one (acknowledge has 

been received), the command is ignored (nothing is sent to the DSI PLL Control module). 

All the DSI PLL power is controlled by the DSI protocol engine except the LDO power of the PLL and 

HSDIVIDER that can be controlled by the DSI PLL controller module. Indeed, the HSDIVIDER and PLL 

SYSRESET signals can be forced by the DSI PLL controller module by setting 

DSS.DSI_PLL_CONTROL[4] DSI_HSDIV_SYSRESET and DSS.DSI_PLL_CONTROL[3] 

DSI_PLL_SYSRESET bits, respectively. By setting these bits to 1, the SYSRESET signal is forced active 

(module is forced to reset state). When these bits are set to 0 (reset value), the SYSRESET signals are 

controlled by the DSI PLL power FSM. 

7.4.3.6.2.1.1 DSI-PLL HS Clock Signals 

The DSIStopClk signal is provided to the DSI PLL control module. It indicates when the DSI Protocol 

engine does not need to use the high-speed transfer mode (HS mode) and PLL HS output (HS_CLK 

clock) can be stopped. The following conditions must also be met when DISPC_UPDATE_SYNC may be 

generated by the display controller, as that may also result in the PLL HS output being stopped. 



dss-170 

1657

RESET 

DSIStopClk 

De-Assertion 



When the interface is disabled (that is, DSS.DSI_CTRL[0] IF_EN bit set to 0), the signal DSIStopClk is 

asserted. 

The assertion of the DSIStopClk depends on the following conditions: 

• Clock lane TxRequestHS is deasserted (the DDR clock on the clock lane is not required anymore). 

The get TxRequestHS deassertion, all of the following conditions are required: 

– The DSS.DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON bit must be reset to 0 and no HS data 

transfer should be ongoing or already scheduled. 

– No VC active in video mode. No VC using the video mode is enabled; if the VC is enabled, the 

mode is command mode only (that is, DSS.DSI_VCn_CTRL[0] VC_EN bit set to 1 and 

DSS.DSI_VCn_CTRL[4] MODE bit set to 0). 

– No command mode requiring high-speed transfer (one or more VCs using command mode can be 

active) 

– Or DSS.DSI_CTRL[0] IF_EN bit reset to 0 (if all previous conditions are not required) 

The deassertion of the DSIStopClk depends on one of the following conditions (the DSI interface is 

enabled by setting the DSS.DSI_CTRL[0] IF_EN bit to 1): 

• Clock lane TxRequestHS must be asserted (the DDR clock on the clock lane is required anymore). 

• One video mode VC active 

• At least one VC in command mode requiring high-speed transfer 

• The DSS.DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON bit is set to 1 by software users (the 

DSS.DSI_CTRL[0] IF_EN bit must be reset to 0 to update the DDR_CLK_ALWAYS_ON bit value) 

Automatic assertion/deassertion is enabled by using the DSS.DSI_CLK_CTRL[18] 

HS_AUTO_STOP_ENABLE bit. 

Manual mode can be used by setting/resetting the DSS.DSI_CLK_CTRL[19] HS_MANUAL_STOP_CTRL 

bit to assert/deassert the DSIStopClk signal. 

7.4.3.6.2.1.2 DSI-PLL HS Clock FSM 

Figure 7-95 shows the DSI PLL HS clock FSM. 

Figure 7-95. DSI PLL HS Clock FSM 

(All the conditions for assertion are valid and 

DSI_CLK_CTRL[18] HS_AUTO_STOP_ENABLE = 0x1) 

Or 

(DSI_CLK_CTRL[19] HS_MANUAL_STOP_CTRL = 0x1 and 


One of the conditions for de-assertion is valid and 


Or 

(DSI_CLK_CTRL[19] HS_MANUAL_STOP_CTRL = 0x0 and 


DSIStopClk 

Assertion 

When DSIStopClk is used there is a latency through other modules (DSI PLL controller and DSI_PHY) 



dss-171



before TxByteClkHS is stopped. This latency must be accounted for to prevent any issue when 

DSIStopClk is deasserted soon after being asserted. This is done using a hardware timer programmed 

using the DSS.DSI_STOPCLK_TIMING[7:0] DSI_STOPCLK_LATENCY bit field. This timer is 

programmed in number of periods of the DSI Protocol functional clock (DSI_FCLK). At reset value, the 

timer is programmed with 0x80 (128) value. 

7.4.3.7 Timers 

CAUTION 

The programmed value in the DSS.DSI_STOPCLK_TIMING[7:0] 

DSI_STOPCLK_LATENCY bit field must be greater than ((3 x L3_ICLK period) 

+ (5 x CLKIN4DDR period))/(DSI_FCLK period). 

NOTE: Among the timers described in this section, only the HS TX, LP RX and turnRequests timers 

generates interrupts immediately when the timer value is null. For ForceTxStopMode timer, it 

ends counting instantly and ForceTxStopMode is not asserted. 

7.4.3.7.1 Twakeup Timer 

The T WakeUp timer is not implemented in the DSI protocol engine. The software must use a general-purpose 

(GP) timer to handle this. This timer is used for existing ULP status mode for the active lanes (clock and/or 

data lanes). The sequence to exit ULP state is: 

1. Change the state of TxULPSExit for each lane to ACTIVE. 

2. Wait for the interrupt indicating that all lanes with TxULPSExit active have acknowledged by asserting 

ULPSActiveNot. This is done by reading the DSS.DSI_COMPLEXIO_IRQSTATUS 

ULPSACTIVENOT_ALLi_IRQ bit fields (i = 0, 1). 

3. Start the application wake-up timer (GP timer). 

4. Wait for the time-out. 

5. Change the TxUlpsClk signals to INACTIVE state for the clock lane and/or TxRequestEsc INACTIVE 

state for the data lane(s). 

NOTE: The minimum time for the wake-up period is 1 ms. 

To enter ULPS mode for clock lane, TxUlpsClk state must be changed to active state. To enter ULPS 

mode for data lane, TxRequestEsc state must be changed to active state (TxUlpsEsc as well if it is not 

already in active state). 

7.4.3.7.2 ForceTxStopMode FSM 

The signal ForceTxStopMode is used at initialization time (DSI complex I/O). Figure 7-96 describes the 

ForceTxStopMode FSM to assert/deassert ForceTxStopMode signal. 



1659

RESET 

De-assertion 



Figure 7-96. ForceTxStopMode FSM 

DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO = 0x1 

DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO = 0x0 

Or 

Time out 

Timer started 

The DSI protocol engine asserts ForceTxStopMode by setting the DSS.DSI_TIMING1[15] 

FORCE_TX_STOP_MODE_IO bit to 1. Asserting the FORCE_TX_STOP_MODE_IO bit allows to initialize 

the lanes. The lanes are in the Stop State when ForceTxStopMode signal is high. 

No data can be sent before the ForceTxStopMode signal is deasserted. The deassertion time is defined 

by the STOP_STATE_COUNTER_IO, Stop_State_x4_IO, Stop_State_x16_IO field DSI_TIMING1[15:0]. 

The FORCE_TX_STOP_MODE_IO bit is reset by hardware when the time is reached. 

This bit can be reset by software. 

The calculation of the number of DSI_FCLK cycles assertion period is defined by: 

Total period in DSI_FCLK cycles = DSI_TIMING1[12:0] STOP_STATE_COUNTER_IO x 

((DSI_TIMING1[14] STOP_STATE_X16_IO x 15) + 1) x ((DSI_TIMING1[13] STOP_STATE_X4_IO x 3) 

+ 1) 

7.4.3.7.3 TurnRequest FSM 

The signal TurnRequest is used to request turnaround. It is only valid for the data lane #1 since the other 

data lanes cannot be used in the reverse direction to receive data from the DSI receiver. Figure 7-97 

describes the TurnRequest FSM to assert/deassert TurnRequest signal. 



dss-172

RESET 

IDLE 

DSI_TIMING1[31] TA_TO = 0x1 

DSI_TIMING1[31] TA_TO = 0x0 

by software 



Figure 7-97. TurnRequest FSM 

Timer loaded 

PPI TurnRequest signal 

asserted by DSI protocol 

engine 

BTA accepted by peripheral 

DSI_TIMING1[31] TA_TO = 0x0 by software 

DSI_TIMING1[31] TA_TO = 0x0 by hardware 

Timer started 

Time-out 

TA_TO 

interrupt 

generation and 

ForceTxStopMode 

sequence 

The DSI protocol engine asserts TurnRequest signal during one TxClkEsc cycle when the turn-around is 

enabled through the DSS.DSI_VCn_CTRL[6] BTA_EN bit (for more information, see Section 7.4.3.8, Bus 

Turnaround). The DSS.DSI_TIMING1[31] TA_TO bit is set/reset by software to respectively enable/disable 

the timer for turnaround procedure failure. It can be reset by software or automatically by hardware when 

the time out occurs. 

The timer is loaded with the value in number of DSI_FCLK cycles: 

DSI_TIMING1[28:16] TA_TO_COUNTER x ((DSI_TIMING1[30] TA_TO_X16 x 15) + 1) x 

((DSI_TIMING1[29] TA_TO_X8 x 7) + 1). 

When the TA_TO_IRQ interrupt is generated (turn-around timer expired, and procedure failed), the 

hardware automatically asserts ForceTXStopMode in order for the DSI_PHY to drive LP-11 stop state. 

The ForceTXStopMode timer is used to define the minimum duration of LP-11 state. The Stop State can 

be longer if there is no activity. 

The hardware resets the ForceTXStopMode bit, followed by an internal logic reset except all register 

values and TX FIFO content, then resets the DSS.DSI_CTRL[0] IF_EN bit. The software should take 

action to recover by resetting the peripheral, for example, if it is not responding. It should wait for 

DSS.DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO and DSS.DSI_CTRL[0] IF_EN bits to be reset to 0 

before starting the recovery sequence. 

7.4.3.7.4 Peripheral Reset Timer 

The peripheral reset timer is not implemented in the DSI protocol engine module. Such as the Twakeup 

timer, a general-purpose timer (GPTimer)should be used in case of reset of the peripheral to determine 

when the peripheral is ready again for operation. 

7.4.3.7.5 HS TX Timer 

The HS TX timer is used to detect when the host has been in TX mode for too long. When time-out 

occurs, the EOT is forced. The timer is reloaded when a start of high speed transmission occurs. It is 

enabled/disabled by software through the DSS.DSI_TIMING2[31] HS_TX_TO bit. The interrupt 

HS_TX_TO_IRQ is generated when the timer expires. The DSS.DSI_IRQSTATUS[14] HS_TX_TO_IRQ 

bit is set to 1 when the HS TX time-out occurs. 



dss-173 

1661

RESET 

IDLE 

DSI_TIMING2[31] HS_TX_TO = 0x1 

DSI_TIMING2[31] HS_TX_TO = 0x0 

by software 



The maximum time to be supported is 20 ms. It can be used to determine that at least once a frame in 

video mode, the HS mode is stopped to enter ULPS. Since the refresh rate can be up to 50 frames per 

second in video mode, the maximum time in HS is 20 ms. 

The timer is loaded with the value in number of TxByteClkHS: 

DSI TIMING2[28:16] HS_TX_TO_COUNTER x ((DSI TIMING2[30] HS_TX_TO_X16 x 15) +1) x ((DSI 

TIMING2[29] HS_TX_TO_X8 x 7) +1) 

Figure 7-98. High-Speed TX Timer FSM 

Timer loaded 

DSI link is High Speed mode 

SOT generated 

DSI ends in high speed mode 

EOT generated 

DSI_TIMING2[31] HS_TX_TO = 0x0 by software 

DSI_TIMING2[31] HS_TX_TO = 0x0 by hardware 

Timer started 

Time-out 

HS_TX_TO 

interrupt 


EOTsent 

When the time-out occurs, the hardware should sent EOT request in order for the DSI complex I/O to 

drive LP-11 stop state. This is followed by the generation of the interrupt. The hardware will perform an 

internal logic reset including the TX FIFO content, but excluding the register values and then resets the 

DSS.DSI_CTRL[0] IF_EN bit. 

The software should wait for the DSS.DSI_CTRL[0] IF_EN bit to be reset to 0 before taking any recovery 

action by resetting for example the peripheral if it is not responding. 

7.4.3.7.6 LP RX Timer 

When the host is in Low power Receive mode after a bus turn-around, the LP RX timer is loaded. When 

the timer expires, the host requests the DSI complex I/O to drive LP-11. The interrupt LP_RX_TO_IRQ is 

generated when the timer expires. The DSS.DSI_IRQSTATUS[15] LP_RX_TO_IRQ bit is set to 1 when 

the LP RX time-out occurs. 

The DSS.DSI_TIMING2[15] LP_RX_TO bit is set/reset by the software to respectively enable/disable the 

timer. 

The timer is loaded with the value in number of DSI_FCLK cycles: 

DSI_TIMING2[12:0] LP_RX_TO_COUNTER x ((DSI_TIMING2[14] LP_RX_TO_X16 x 15) + 1) x 

((DSI_TIMING2[13] LP_RX_TO_X4 x 3) + 1) 



dss-174

RESET 

IDLE 

DSI_TIMING2[15] LP_RX_TO = 0x1 

DSI_TIMING[15] LP_RX_TO = 0x0 

by software 



Figure 7-99. Low-Power RX Timer FSM 

Timer loaded 

LP RX timer has completed. 

Direction has changed (RX >TX). 

DSI_TIMING2[15] LP_RX_TO = 0x0 by software 

DSI_TIMING2[15] LP_RX_TO = 0x0 by hardware 

Timer started 

Time-out 

LP_RX_TO 

interrupt 


ForceTxStopMode 

sequence 

When the interrupt is generated, the hardware should automatically reset the DSS.DSI_TIMING2[15] 

LP_RX_TO bit and then assert ForceTXStopMode in order for the DSI complex I/O to drive LP-11 stop 

state. The ForceTXStopMode timer is used to define the minimum duration of LP-11 state. The Stop State 

can be longer if there is no activity. 

The hardware resets the ForceTXStopMode bit, followed by an internal logic reset except all register 

values and TX FIFO content, then resets the DSS.DSI_CTRL[0] IF_EN bit. The software should take 

action to recover by resetting the peripheral, for example, if it is not responding. It should wait for the 

DSS.DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO and DSS.DSI_CTRL[0] IF_EN bits to be reset 

before starting the recovery sequence. The TX FIFO is not flushed (the FIFO is flushed only when 

DSS.DSI_VCn_CTRL[0] VC_EN is set to 1). 

7.4.3.8 Bus Turnaround 

The bus turn-around (BTA) is not automatically sent by default after each packet sent to the display(s). It 

is programmable independently for each VC ID. The VC can be enabled when DSS.DSI_VCn_CTRL[6] 

BTA_EN bit is set to 1 by software. The software should ensure that, when the BTA is sent to the 

peripheral, there is enough time allocated for the response and the BTA from the peripheral to host. For 

more information about possible DSI PHY timing adjustments during the turn-around procedure, see 

Section 7.5.6.4.3, Turn-Around Request in Transmit Mode, and Section 7.5.6.4.4,Turn-Around Request in 

Receive Mode. When setting the DSS.DSI_VCn_CTRL[6] BTA_EN bit to 1, one BTA is sent manually to 

the peripheral. This manual mode can be used for packets in command or video mode. 

Acknowledgment from the peripheral for successful BTA is indicated by asserting the BTA_IRQ interrupt, if 

it is enabled in the DSS.DSI_VCn_IRQENABLE[5] BTA_IRQ_EN bit. To monitor the BTA interrupt, the 

user should read the DSS.DSI_VCn_IRQSTATUS[5] BTA_IRQ status bit. 

CAUTION 

The BTA should not be sent when the RX FIFO is not empty. Users should take 

care of emptying the RX FIFO before sending BTA to the peripheral. It is to 

ensure that when receiving new data from peripheral, all the allocated spaces 

for all the VCs are empty. 



dss-175 

1663



In automatic mode, the BTA is sent automatically at the end of short or long packets when respectively the 

DSS.DSI_VCn_CTRL[2] BTA_SHORT_EN or the DSS.DSI_VCn_CTRL[3] BTA_LONG_EN bits are set to 

1. 

NOTE: If the DSS.DSI_VCn_CTRL[2] BTA_SHORT_EN bit is enabled, users can still set the 

DSS.DSI_VCn_CTRL[6] BTA_EN bit. Only one BTA is sent to the peripheral and the 

DSS.DSI_VCn_CTRL[6] BTA_EN bit is reset by hardware. 

If the DSS.DSI_VCn_CTRL[3] BTA_LONG_EN bit is enabled, users can still set the 

DSS.DSI_VCn_CTRL[6] BTA_EN bit. Only one BTA is sent to the peripheral and the 

DSS.DSI_VCn_CTRL[6] BTA_EN bit is reset by hardware. 

If the DSS.DSI_VCn_CTRL[2] BTA_SHORT_EN and DSS.DSI_VCn_CTRL[3] 

BTA_LONG_EN bits are both enabled, users can still set the DSS.DSI_VCn_CTRL[6] 

BTA_EN bit to send a BTA. Only one BTA is sent and the DSS.DSI_VCn_CTRL[6] BTA_EN 

bit is reset by hardware. 

As explained previously, two modes can be used for each VC ID: 

• Automatic: After each packet, a bus turn-around is sent. To determine the size of the long packet, the 

protocol engine on the host side should read the word count defined in the header (in 

DSS.DSI_VCn_LONG_PACKET_HEADER register) and use it to determine the last data to be sent on 

the DSI link. For short packets, the size is always 4 bytes. Then the bus turn-around is sent to the 

peripheral. The word count is also used to determine how many bytes should be transferred from the 

32-bit writes access to the payload register (DSS.DSI_VCn_LONG_PACKET_PAYLOAD register). 

• Manual: In case of data transfer using the L4 interconnect port, while all data have been provided to 

the DSI protocol engine, users can select bus turn-around for the last packet provided to the L4 

interconnect port only by setting the bus turn-around enable bit (DSS.DSI_VCn_CTRL[6] BTA_EN) or 

for last packets and following ones by setting the automatic mode; in case of data transfer using the 

video port, the bus turnaround enable bit (DSS.DSI_VCn_CTRL[6] BTA_EN) can be selected at any 

time during the transfer of the packet. In case of video mode packets (data and synchronization 

events) users cannot determine when the BTA is sent relatively the video mode packets, so it is highly 

recommended to use manual BTA mode only for packets generated in command mode but it is 

possible to use BTA when for a VC in video mode. In case of data provided on the video port, an 

interrupt for end of packet transfer (PACKET_SENT_IRQ) is provided to indicate users when the 

packet has been completely sent by the DSI complex I/O. The PACKET_SENT_IRQ can be monitored 

in DSI_VCn_IRQSTATUS[2] PACKET_SENT_IRQ status bit. Users can request BTA even if the space 

allocated in the TX FIFO for the corresponding VC is empty. It can be sent later on even if there was 

no packet sent before BTA request. The DSS.DSI_VCn_CTRL[6] BTA_EN bit should be reset by 

hardware if the BTA request has been sent even if the automatic mode for this specific type of packets 

is enabled. 

The bus turnaround is supported for video mode packets and for command mode packets. It is not 

possible to send BTA during the blanking periods of the video mode when HS blanking packets should be 

sent, that is, when one of the following bits is set to 1: 

• DSS.DSI_CTRL[20] BLANKING_MODE 

• DSS.DSI_CTRL[21] HFP_BLANKING_MODE 

• DSS.DSI_CTRL[22] HBP_BLANKING_MODE 

• DSS.DSI_CTRL[23] HSA_BLANKING_MODE 

Therefore, in video mode, the BTA request is delayed until there is a blanking period without HS blanking 

packets. 

TA Timer 

When TurnRequest signal is asserted (always only for data lane #1), the TA_TO timer is started. If the 

direction signal is no changed according to the turn-around request, the TA_TO interrupt is generated. 

When the Direction signal is in output mode, any data on the input data bus should be ignored since the 

DSI is in transmission mode (data and triggers should be ignored). See Section 7.4.3.7.3 for more details 

on the TA_TO timer. 





7.4.3.9 PHY Triggers 

The DSI protocol engine uses three triggers, which are supported only for data lane 1: 

• Reset from host to display 

• Tearing effect (TE) from display to host 

• Acknowledge from display to host 

7.4.3.9.1 Reset 

CAUTION 

Each trigger is associated with a dedicated user-configurable receive or 

transmit pattern, loaded in DSI_PHY_REGISTER3 or DSI_PHY_REGISTER4 

bit fields. The default (reset) values of the bit fields are aligned with the MIPI 

D-PHY specification v0.92. If the user needs to change any of these values, the 

following must be considered: 

• If any of the bit fields are written with a nondefault value, the other bit fields 

in the same register must also be configured with different values. This is to 

ensure that two different trigger bit fields are not programmed with the same 

pattern. 

• If two or more bit fields are written with equal values, this may lead to 

unpredictable behavior of the DSI PHY module. 

The DSI protocol engine can use one of the triggers of the DSI_PHY to send a reset to the display. The 

reset trigger pattern is configurable through the DSI_PHY_REGISTER3[31:24] REG_TXTRIGGERESC3 

bit field. To send the reset pattern to the peripheral, the DSS.DSI_CTRL[5] TRIGGER_RESET bit must be 

set to 1. When the software requires the trigger reset pattern to be sent, the DSI protocol engine resets its 

own logic but not the registers. The software can select between two reset modes: 

• Immediate reset: All pending requests in TX FIFO not already taken into account for transfer 

scheduling, the RX FIFO requests, and the data from video port are ignored. Only the current transfer 

on DSI link and already scheduled ones are transmitted. All the other transfers are discarded. 

• Synchronized reset: The mode is only valid if there is VC using the video mode and if it is active. The 

principle is to wait for the current video frame to be transferred on the link. Any data on VP after the 

current frame are ignored. 

To select the reset mode, software users must program the DSS.DSI_CTRL[14] 

TRIGGER_RESET_MODE. 

7.4.3.9.2 Tearing Effect 

CAUTION 

For both reset modes, the hardware should flush the FIFOs, synchronization 

buffers, and line buffers before resetting the DSS.DSI_CTRL[0] IF_EN bit. 

The TE on the display is avoided by having synchronization information from the display. It is used only in 

command mode. In case of video mode, it is not functional. Users are responsible for selecting the 

command mode for the VC using the TE feature. 

The software must set and send the appropriate sequence to receive the TE trigger pattern from the 

peripheral. The value of the expected TE trigger pattern can be configured through the 

DSI_PHY_REGISTER4[23:16] REG_RXTRIGGERESC2 bit field. When the TE trigger pattern is received, 

the DSI protocol engine generates the TE_TRIGGER_IRQ interrupt with TE event if the interrupt is 

enabled. To enable the interrupt, set to 1 the DSS.DSI_IRQENABLE[16] TE_TRIGGER_IRQ_EN bit. The 

DSS.DSI_IRQSTATUS[16] TE_TRIGGER_IRQ status bit indicates if the interrupt event has been 

generated. 



1665



One or multiple VCs can be synchronized using the same TE trigger. The DSS.DSI_VCn_TE[30] TE_EN 

bit should be set to indicate that the hardware should use the following TE trigger to start the transfer of 

the data from the related VC. This bit is reset when all the data have been sent to the peripheral. The 

DSS.DSI_VCn_TE[31] TE_START bit should be used when the automatic mode enabled by setting the 

DSS.DSI_VCn_TE[30] TE_EN bit is not used. It allows users to start the transfer manually based on 

application events or based on the TE trigger interrupt (TE_TRIGGER_IRQ). 

The number of bytes to be transferred is defined by using the DSS.DSI_VCn_TE[15:0] TE_SIZE bit field. 

The TE_SIZE bit field is decremented for each payload byte (it does not include Check-sum) sent on the 

DSI link. The register content should not be modified by software during a transfer. The 

DSS.DSI_VCn_TE[15:0] TE_SIZE bit field should be set first to indicate that the following accesses to 

DSS.DSI_VCn_LONG_PACKET_HEADER register should be used for TE transfer. 

The data can be provided from two sources (selection by setting the DSS.DSI_VCn_CTRL[1] SOURCE 

bit): 

• L4 interconnect port using DMA request: The DMA request DSI_DMA_REQi (i=0 to 3) to should be 

asserted only when TE trigger is received or when the DSS.DSI_VCn_TE[31] TE_START bit is set by 

user and should not be asserted anymore when all the bytes defined in DSS.DSI_VCn_TE[15:0] 

TE_SIZE bit field have been sent on the DSI link. The VC is associated with a DMA request (from 

DSI_DMA_REQ0 to DSI_DMA_REQ3) by programming the number in the 

DSS.DSI_VCn_CTRL[23:21] DMA_TX_REQ_NB bit field. The 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD register is used to provide the number of bytes defined by 

the DSS.DSI_VCn_TE[15:0] TE_SIZE bit field (the check-sum value is not provided in the 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD register). The size of the header is not taken into account 

in the number of bytes to transfer. The DSS.DSI_VCn_SHORT_PACKET_HEADER register is not 

used. 

• Video port: The DMA request is not asserted. The data are captured in the line buffer using the STALL 

mechanism. In case there is no line buffer instantiated (that is, DSS.DSI_CTRL[13:12] LINE_BUFFER 

bit field set to 0), it is not possible to use the video port to provide data. The line buffer should be filled 

up according to the word count defined in the DSS.DSI_VCn_LONG_PACKET_HEADER register 

header. The value should be written before the TE trigger event is received or before the 

DSS.DSI_VCn_TE[31] TE_START bit is set to 1 by software. In case the total number of bytes defined 

by the DSS.DSI_VCn_TE[15:0] TE_SIZE bit field is not a multiple of the word count defined in the 

DSS.DSI_VCn_LONG_PACKET_HEADER register, all the packets have the same size defined by the 

WC of the header except the last transfer. The size of the last transfer is defined by the remaining 

bytes to send. Since the DSS.DSI_VCn_TE[15:0] TE_SIZE bit field is modified after each packet 

transfer, the size of the last packet is equal to the value of DSS.DSI_VCn_TE[15:0] TE_SIZE bit field 

just before the last transfer (the header and the payload check-sum sizes are not included in 

DSS.DSI_VCn_TE[15:0] TE_SIZE bit field). 

When the transfer is completed, the value of the DSS.DSI_VCn_TE[15:0] TE_SIZE bit field is equal to 0. 

The software must ensure that the pending data in the TX FIFO for the corresponding VC using TE are 

related to TE transfer. Any data in the TX FIFO that should be sent before reception of TE trigger should 

be sent before TE. This is done by not enabling TE trigger until all data for the corresponding VC have 

been sent to the peripheral. The software can check that the space allocated for the VC in the TX FIFO is 

empty by reading the DSS.DSI_VCn_CTRL[5] TX_FIFO_NOT_EMPTY status bit. 

7.4.3.9.3 Acknowledge 

The corresponding Acknowledge interrupt (ACK_TRIGGER_IRQ ) is generated upon reception of the 

acknowledge trigger. The value of the expected acknowledge trigger pattern can be configured through 

the DSI_PHY_REGISTER4[15:8] REG_RXTRIGGERESC1 bit field. To enable the acknowledge interrupt, 

set the DSS.DSI_IRQENABLE[17] ACK_TRIGGER_IRQ_EN bit to 1. When the interrupt is generated, the 

DSS.DSI_IRQSTATUS[17] ACK_TRIGGER_IRQ status bit is set to 1. 



0 0 

8 

0 0 P [5:0 ] 

Parity Generator 

ECC 

WC [15 :8 ] or DB 1 



7.4.3.10 ECC Generation 

The DSI protocol uses a four-byte packet header. Since ECC generation requires a fixed word length of 

64-bits, the packet headers should be padded with additional bits to form a full eight-byte value for ECC 

generation and checking. The packet header less the ECC byte should occupy bits D[23:0] and the pad 

bits should occupy bits D[63:24]. All padding bits should be zero for the purpose of generating the ECC 

byte. ECC can be generated using a parallel approach as illustrated in Figure 7-100. 

Figure 7-100. 64-Bit ECC Generation on TX Side 

WC [7 : 0 ] or DB 0 

8 8 8 

D63 D24D23 D0 

16-bit checksum 

CRC LS byte CRC MS byte 

16-bit packet footer (PF) 

VC 

dss-177 

DT [5 :0 ] 

The ECC generation/check can be enabled and disabled by software. It is defined by a common bit for all 

the VCs: 

• The DSS.DSI_CTRL[2] ECC_RX_EN bit enables/disables the ECC generation in the receive direction. 

• The DSS.DSI_VCn_CTRL[8] ECC_TX_EN bit enables/disables the ECC generation in the transmit 

direction 

7.4.3.11 Checksum Generation for Long Packet Payloads 

Long packets are comprised of a packet header protected by an ECC byte and a payload of 0 to 2 16 - 1 

bytes. To detect the errors during the transmission of long packets, a checksum is calculated over the 

payload portion of the data packet. Note that, for the special case of a zero-length payload, the 2-byte 

checksum is set to 0xFFFF. The checksum can only indicate the presence of one or more errors in the 

payload. Unlike ECC, the checksum does not enable error correction. For this reason, checksum 

calculation is not useful for some unidirectional DSI implementations since the peripheral has no way for 

reporting errors to the host processor. Checksum generation and transmission is mandatory for host 

processors sending long packets to peripherals. It is optional for peripherals transmitting long packets to 

the host processor. However, the format of long packets is fixed; the peripherals that do not support 

checksum generation should transmit two bytes having value 0x0000 in place of the checksum bytes 

when sending long packets to the host processor. The host processor should disable checksum checking 

for received long packets from peripherals that do not support checksum generation. 

The checksum should be realized as a 16-bit CRC with a generator polynomial of x^16+x^12+x^5+x^0. 

The LS byte is sent first, followed by the MS byte. Note that within the byte, the LS bit is sent first. 

Figure 7-101. Checksum Transmission 

The CRC implementation is presented in Figure 7-102. The CRC shift register is initialized to 0xFFFF 



dss-176 

1667

MSB 

C15 C14 C13 C12 C11 

x^0 x^5 



before packet data enters. Packet data not including the packet header then enters as a bitwise data 

stream from the left, LS bit first. Each bit is fed through the CRC shift register before it is passed to the 

output for transmission to the peripheral. After all bytes in the packet payload have passed through the 

CRC shift register, the shift register contains the checksum. C15 contains the checksums MSB and C0 the 

LSB of the 16-bit checksum. The checksum is then appended to the data stream and sent to the receiver. 

Figure 7-102. 16 Bit CRC Generation Using a Shift Register 

Polynomial: x^16+x^12+x^5+x^0 

LSB 

C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 

x^12 x^15 

The check-sum generation/check can be enabled and disabled by software. It is defined by a common bit 

for all the VCs: 

• The DSS.DSI_CTRL[1] CS_RX_EN bit enables/disables the check-sum generation in the receive 

direction. 

• The DSS.DSI_VCn_CTRL[7] CS_TX_EN bit enables/disables the check-sum generation in the transmit 

direction 

7.4.3.12 End of Transfer Packet 

To allow the DSI protocol (rather than the DSI_PHY) at the display to detect the HS End Of Transfer 

(EOT), an EOT packet type is added. It is a fixed short packet (4 bytes) that is added at every HS-to-LP 

transition. This function is enabled by the DSI_CTRL[19] EOT_ENABLE bit. 

The EOT packet has a fixed format: 

• Data Type = DI [5:0] = 0b001000 

• Virtual Channel = DI [7:6] = 0b00 

• Payload Data [15:0] = 0x0F0F 

• ECC [7:0] = 0x01 

When more than one data lane is used, the bytes in the EOT packet are distributed across multiple lanes. 

EOT packet generation is supported only for the end of HS transmissions. No EOT packet is added at the 

end of LP transmissions. For LP reception, any EOT packet received is simply passed through the same 

as any other packet, but no internal decode or use is made of the EOT information. 

7.4.4 DSI PLL Controller Functionalities 

7.4.4.1 DSI PLL Controller Overview 

The DSI PLL controller module forms part of the display sub-system. Nevertheless, it uses the SCP (Serial 

Configuration Port) and PMP (Power Management Port) ports as the primary interfaces to the DSI 

protocol engine. The SCP interface is used to set the configuration of the DPLL and HSDIVIDER modules, 

primarily the various counter values. The PMP port is used to control the power state of the DPLL and 

HSDIVIDER modules. Figure 7-103 provides an overview of the DSI PLL controller module inside the 

display subsystem. 

The DSI PLL is also used to generate the 74.25-MHz frequency used for HDTV applications. 



dss-178

DSS 

DISPC 

L4/L3 

VP 

DSI 

protocol 

PMP 

Functional 



Figure 7-103. DSI PLL Controller Overview 

DSI PLL 

control 

Clocks 

Status 

Control 

DSI data/control 

PMP 

SCP 

ADPLLv2 ADPLLM 

HSDIVIDER 

2ch 

Clock 

NOTE: The DSI PLL controller module does not have an interface to L4 interconnect. The 

programmable features are managed by registers mapped into the DSI protocol engine. 

7.4.4.2 DSI PLL Controller Architecture 

DFT 

DSI_PHY 

The DSI PLL is an ADPLLM module. The pixel clock (PCLK) frequency range is 2 to 68.25 MHz. This may 

be divided by 2. This is performed by setting the DSS.DSI_PLL_CONFIGURATION2[12] 

DSI_PLL_HIGHFREQ bit to 1. 

Figure 7-104 shows the internal DSI PLL reference diagram. 



I/O 

dss-179 

1669


DSI PLL controller 

PCLKFREE PCLK 

÷ 2 

HIGHFREQ 

TIGHTPHASELOCK 

LOCK 

LOCKSEL[1:0] 

CLKSEL 

SYS_CLK 

0 

0 

1 

1 

0 

1 

2 

3 

REFEN 

Gating 



Figure 7-104. DSI PLL Reference Diagram 

SPARE 

CLKINP 

TIGHTPHASELOCK 

PHASELOCK 

FREQLOCK 

(TVALID) 

CLKIN4DDR 

(To DSI_PHY) 

DCOCLKLDO 

ADPLLM 

NOTE: PCLK is inverted as the falling edge is the reference edge and ADPLLM uses positive edge as reference 

(F/F should be positive edge clock also). 

The DSI PLL clock output corresponds to the CLKIN4DDR clock of the DSI complex I/O module. 

The DSI PLL reference clock is the DSI_PLL_REFCLK clock. Depending on the setting in 

DSS.DSI_PLL_CONFIGURATION2[11] DSI_PLL_CLKSEL bit, the reference clock can be either the 

DSS2_ALWON_FCLK provided by the PRCM or the PCLKFREE provided by the DISPC module. 

7.4.4.3 DSI PLL Operations 

camdss-180 

The signals of the DSI PLL configuration operate according to Table 7-37. The values in the table indicate 

the operation when the PLL is not locked. 

Table 7-37. DSI PLL Operation Modes When Not Locked 

DSI PLL Stop mode Stop mode Idle bypass 

Operation Mode Low power (1) Fast Relock (1) 

Mode Description Output clocks Output clocks Selects when PLL 

stopped stopped and HSDIVIDER 

Lowest Fastest bypass clocks 

power standby start-up time are used 

DSS.DSI_PLL_CONFIGURATION2[0] DSI_PLL_IDLE 0 0 1 

DSS.DSI_PLL_CONFIGURATION2[6] 1 0 1 

DSI_PLL_LOWCURRSTBY 

DSS.DSI_PLL_CONFIGURATION1[0] DSI_PLL_STOPMODE 1 1 X 

(1) Recommended 

When locked, the PLL output frequency is: [(2xREGM)/(REGN + 1)]x[CLKin(MHz)/(HIGHFREQ + 1)] 

where: 

• M multiplier is programmed in DSS.DSI_PLL_CONFIGURATION1[18:8] DSI_PLL_REGM bit field. 

• N divider is programmed in DSS.DSI_PLL_CONFIGURATION1[7:1] DSI_PLL_REGN bit field. 

• HIGHFREQ divider by 2 is enabled by setting the DSS.DSI_PLL_CONFIGURATION2[12] 

DSI_PLL_HIGHFREQ bit to 1. 





7.4.4.4 DSI PLL Controller Shadowing Mechanism 

The configuration registers are accessed through the DSI protocol engine register space using SCP port. 

This includes all the configuration signals and the returning status signals. 

CAUTION 

All writes must be 32-bit operations as the SCP always transfers 32 bits. Any 

16-bit or 8-bit operations may lead to unpredictable errors. 

A shadow mechanism is implemented for appropriate register values so that configurations may optionally 

be updated in synchronism with the display controller (DISPC) and DSI protocol engine. The front porch 

time from the DISPC indicates the time when making the update of the value. All the required updated 

values must have been written before this signal is asserted. See Section 7.4.3.5.1 for more details. 

7.4.4.5 Error Handling 

The PLL lock and recalibration signals may be monitored to detect loss of lock or requirement to 

recalibrate (due to large temperature change since the last lock request): 

• The DSS.DSI_PLL_STATUS[1] DSI_PLL_LOCK status bit gives the DSI PLL lock state. 

• The DSS.DSI_PLL_STATUS[2] DSI_PLL_RECAL status bit informs if the PLL must be uncalibrated 

These signals can also generate interrupts at DSI protocol engine level: 

• The PLL_LOCK_IRQ interrupt indicates that the DSI PLL control module has sent a lock request to the 

DSI PLL. To monitor this event, read the DSS.DSI_IRQSTATUS[7] PLL_LOCK_IRQ bit. Set this bit to 

1 to clear the status bit. 

• The PLL_UNLOCK_IRQ interrupt indicates that the DSI PLL control module has sent an unlock 

request to the DSI PLL. To monitor this event, read the DSS.DSI_IRQSTATUS[8] PLL_UNLOCK_IRQ 

bit. Set this bit to 1 to clear the status bit. 

• The PLL_RECAL_IRQ interrupt indicates that the DSI PLL control module has sent a recalibration 

request to the DSI PLL. To monitor this event, read the DSS.DSI_IRQSTATUS[9] PLL_RECAL_IRQ 

bit. Set this bit to 1 to clear the status bit. 

7.4.5 DSI Complex I/O Functionalities 

7.4.5.1 DSI Complex I/O Overview 

DSI_PHY is a complex I/O with 3 unidirectional (HS) Lane Modules. This includes 2 data lane modules 

and 1 clock lane module. Each lane module has 2 data pads (DX, DY). These data pads are connected 

with a complementary lane module on the DSI receiver device using point to point interconnect. 

Lane modules support high-speed burst mode. Forward direction and reverse direction escape modes are 

also supported. Escape modes maybe used for Low Power Data Transmission, among other things. 

The maximum data rate supported is 900 Mbps per data lane. The lane module function and position is 

configurable, that is, any lane module can be chosen as clock lane module, and DX/DY data pad for each 

lane module can be configured as either DP or DN pins defined by DSI_PHY spec. 

DSI_PHY interacts with the higher layers of the DSI link through the PHY-Protocol Interface (PPI). 

DSI_PHY does not include a PLL; a high frequency clock input is expected in HS mode (CLKIN4DDR). 

DSI_PHY supports also Serial Configuration Protocol (SCP) to set various configuration and control 

registers. The DSI_PHY supports GPIO operation on each of the six data pins. 

7.4.6 RFBI Functionalities 

The RFBI module can capture the output pixel from the display controller and send the data to the RFB in 

the LCD panel. The application configures the RFBI module, sends commands, reads data, and 

configures the display controller to send data fetched from the system memory by the display controller 

DMA engine. The commands/data are sent using an 8-, 9-, 12-, or 16-bit parallel interface. 



1671


clock domain 

Video port 

FIFO 

RFBI_DATA 

Interconnect 

FIFO 



The display controller is configured to send the data in 12-, 16-, 18-, or 24-BPP format. In the video port 

FIFO, the encoded pixel values are in an LSB alignment independently of the endianness in system 

memory. 

Figure 7-105 shows an overview of the RFBI architecture. 

7.4.6.1 RFBI FIFO 

Figure 7-105. RFBI Architecture Overview 

The input video port FIFO receives data from the display controller at the pixel clock. The data in the video 

port FIFO are read by the RFBI and are sent to the LCD panel. The video port FIFO is 24 bits wide and 

each pixel in 12-, 16-, 18-, and 24-BPP format is stored in the video port FIFO using one 24-bit value 

aligned on the 24-bit LSB. Section 7.4.6.4, Output Parallel Modes, shows an example of an output 

configuration based on the interface width (16 bits) and the pixel format output (24 bits). 

7.4.6.2 RFBI Interconnect FIFO 

The interconnect FIFO receives the data from RFBI_DATA write requests to the L4 interconnect slave 

port. The data in the interconnect FIFO are read by the RFBI and sent to the LCD panel. The width of the 

interconnect FIFO is 32 bits. The size of the interconnect FIFO is 24 words of 32 bits (that is, 24 words of 

RFBI_DATA). 

7.4.6.3 Input Pixel Formats 

The supported pixel formats in the RFBI module are: RGB24-888, RGB18-666, RGB16-565, and 

RGB12-444 as output from the display controller and from the L4 (for writing parameters). In both cases, 

the pixels are formatted in accordance with the configuration of the output interfaces (multiple cycles). 

7.4.6.4 Output Parallel Modes 

The RFBI output modes are 8-, 9-, 12-, and 16-bit interfaces. Any mode can be selected regardless of the 

pixel format. Set the right configuration in the cycle registers to define a valid configuration for each output 

cycle. 



dss-053



The following example is an output configuration based on the 16-bit interface width and the 24-bit pixel 

format (i = 0 or 1) (see also Table 7-38): 

• The DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT bit field is set to 0x3 (three cycles for two pixels). 

• The DSS.RFBI_DATA_CYCLE1_i register is set to 0x00000010 (16 bits from pixel 1 for the first cycle). 

• The DSS.RFBI_DATA_CYCLE2_i register is set to 0x00080808 (8 bits from pixel 1 and pixel 2 and 

alignment of 8 bits from pixel 2 for the second cycle). 

• The DSS.RFBI_DATA_CYCLE3_i register is set to 0x00100000 (16 bits from pixel 2 for the third 

cycle). 

Table 7-38. 16-Bit Interface Configuration/24-Bit Mode 

24-Bit Mode 

1st Cycle 2nd Cycle 3rd Cycle 

Data[15] R0[7] B0[7] G1[7] 

Data[14] R0[6] B0[6] G1[6] 

Data[13] R0[5] B0[5] G1[5] 

Data[12] R0[4] B0[4] G1[4] 

Data[11] R0[3] B0[3] G1[3] 

Data[10] R0[2] B0[2] G1[2] 

Data[9] R0[1] B0[1] G1[1] 

Data[8] R0[0] B0[0] G1[0] 

Data[7] G0[7] R1[7] B1[7] 

Data[6] G0[6] R1[6] B1[6] 

Data[5] G0[5] R1[5] B1[5] 

Data[4] G0[4] R1[4] B1[4] 

Data[3] G0[3] R1[3] B1[3] 

Data[2] G0[2] R1[2] B1[2] 

Data[1] G0[1] R1[1] B1[1] 

Data[0] G0[0] R1[0] B1[0] 

7.4.6.5 Unmodified Bits 

In a cycle, if every bit in the interface does not have a pixel value, the status of the unused bits can be 

programmed to be 0, 1, or the previous value (I/O power consumption optimization). 

7.4.6.6 Bypass Mode 

In bypass mode, the RFBI path is bypassed and the display controller data and signals are sent directly to 

the output interface of the RFBI. 

7.4.6.7 Send Commands 

The commands are written through the L4 interconnect and into the DSS.RFBI_CMD register. After a 

command is sent, another one can be accepted by the module and set. If the processing of a command is 

not complete, the MPU access to change the command stalls. 

7.4.6.8 Read/Write 

Depending on the status of A0, WE, and RE, the commands and display/parameter data are written to the 

panel (handled by the state-machine for the commands/parameter data and stored in memory for the 

display data), or the display data/status values are read from the LCD panel (status and display data in 

the LCD panel memory). The polarity of A0 (RFBI_A0 signal), WE (RFBI_WR signal), RE (RFBI_RD 

signal), and CSx (RFBI_CSx signal, with x = 0, 1) is programmable. 

Table 7-39 describes the read/write function. 



1673



Table 7-39. Read/Write Function Description 

A0 (RFBI_A0) WE (RFBI_WR) RE (RFBI_RD) Function Description 

1 0 1 Display data write, parameter data write 

1 1 0 Display data read 

0 1 0 Status read 

0 0 1 Command data write 

A minimum of RFBI_Cs cycle time, as defined in Table 7-40, is required to keep the RFBI_CSx signal 

asserted between write transfers of multiple pixels. 

Table 7-40 indicates the minimum cycle time for RFBI_CSx, depending on the source of pixels (display 

controller or L4 interconnect slave port) and the cycle format (1pixel/cycle, 1 pixel/2 cycles, 1 pixel/3 

cycles, or 2 pixels/3 cycles). 

Table 7-40. Minimum Cycle Time for CSx/WE Always Asserted 

RFBI Performance RFBI_CONFIGi[10:9] RFBI_CONFIGi[8:7] Minimum Cycle Time (in Number of L4 Cycles) 

CYCLEFORMAT L4FORMAT 

L4 interconnect 1 pixel/cycle 1 pixel 5 

1 pixel/2 cycles 1 pixel 4 

1 pixel/3 cycles 1 pixel 4 

2 pixels/3 cycles 1 pixel 6 

1 pixel/cycle 2 pixels 4 

1 pixel/2 cycles 2 pixels 4 

1 pixel/3 cycles 2 pixels 4 

2 pixels/3 cycles 2 pixels 6 

Display Controller 1 pixel/cycle N/A 4 

7.4.7 Video Encoder Functionalities 

1 pixel/2 cycles N/A 3 

1 pixel/3 cycles N/A 3 

2 pixels/3 cycles N/A 6 

The input formats supported by the encoders are 24-bit 4:4:4 RGB. The encoder output is the DAC stage 

(for more information, see Section 7.2, Display Subsystem Environment). In the display subsystem, the 

input format from the display controller is always 24-bit RGB. The RGB-to-YCbCr color space converter 

converts the 24-bit RGB pixel data to 24-bit YCbCr data. 

The remaining Cb and Cr color components enter the 2-to-1 chrominance decimation, which reduces by 

half the chrominance bandwidth and the amount of chrominance data. After the data manager, the 

encoder processes in 4:2:2 data path up to the 2x interpolation. A luma delay synchronizes luma to 

chrominance data. 

Figure 7-106 shows an overview of the video encoder architecture. 



YCbCr[7:0] 

Cr/R 

[7:0] 

Y 

Luma stage 

Y 

Y/G[7:0] 

Cb/B[7:0] 

HSYNC 

VSYNC 

FID 

AVID 

RESETB 

CLK1X(13.5MHz) 

CLK2X(27MHz) 

CLK4X(54MHz) 

Video encoder 

Color 

Space 

Converter 

EAV SAV 

Timing 

and 

synchronization 

CbCr 

Chroma stage 



Figure 7-106. Video Encoder Architecture Overview 

Cb 

Cr 

Y 

Modulator 

and 

hue control 

SIN/COS 

block 

Crosscolor 

filter 

C 

+ 

CVBS 

Data clock 

2x 

interpolation 

LUMA_ENABLE 

2x 

interpolation 

COMPOSITE_ENABLE 

TVDET 

2x 

interpolation 

Data clock 

Control 

registers 

Y[9:0] 

CVBS[9:0] 

NOTE: Output video mode can be either composite video (CVBS output) or separate video 

(S-video: Luma and Chroma outputs): 

7.4.7.1 Test Pattern Generation 

• Composite video: only AVDAC1 is used 

C[9:0] 

VENC_OUT_SEL 


Luma/ 

composite 

video DAC1 

Chroma video 

DAC2 

C[9:0] 

CHROMA_ENABLE DAC2 enable 

• Separate video (Luma/Chroma): Both AVDAC1 (Luma) and AVDAC2 (Chroma) are used 

The selection is programmed with DSS.DSS_CONTROL[6] VENC_OUT_SEL 

bit. Composite video is the default selection. 

1 

0 

1 

0 

CVBS_Y[9:0] 

DAC1 enable 

TV Detection 

pulse 

camdss_swpu176-public-079 

For diagnostic purposes, the data manager can be forced to output 100/100 color bar RGB/YCbCr data by 

setting the SVDS field VENC_F_CONTROL[7:6] register to 0x1. 

Table 7-41. 100/100 Color Bar Table 

COLOR R G B Y Cb Cr 

White 255 255 255 235 128 128 

Yellow 255 255 0 210 16 146 

Cyan 0 255 255 170 166 16 

Green 0 255 0 145 54 34 

Magenta 255 0 255 106 202 222 

Red 255 0 0 81 90 240 

Blue 0 0 255 41 240 110 

Black 0 0 0 16 128 128 





7.4.7.2 Luma Stage 

The luma stage includes a luma pipeline delay, luma shaping, 2x interpolation filter, and luma variable 

delay. The luma pipeline delay block is used to match luma path length to chroma path length. In the luma 

gain shaper, a programmable gain is first applied to the luminance data output. The luminance gain is 

defined by the DSS.VENC_GAIN_Y register. Horizontal sync, vertical sync, and setup insertion are then 

performed. 

Black level and blank level are programmable through the DSS.VENC_BLACK_LEVEL and 

DSS.VENC_BLANK_LEVEL registers. All the transition edges of the luminance signal, such as sync 

edges and active video edges, are properly shaped and filtered to keep the bandwidth within the 

standards. 

After all required components of the luminance signal are added, the resulting signal is low-passed and 

interpolated to 2x-pixel rate. This 2x interpolation simplifies the external analog reconstruction filter design 

and improves the signal-to-noise ratio. 

7.4.7.3 Chroma Stage 

The chroma stage includes a low-pass filter, first-stage 2x interpolation, chroma gain shaper, and 

second-stage 2x interpolation. A pair of programmable gains adjusts the time-multiplexed U/V signal. The 

gains for U and V are independently controlled by the DSS.VENC_GAIN_U and DSS.VENC_GAIN_V 

register bits. 

7.4.7.4 Subcarrier and Burst Generation 

The encoder uses a 32-bit subcarrier increment to synthesize the subcarrier. The value of the subcarrier 

increments required to generate the desired subcarrier frequency for NTSC and PAL format is found by: 

S_CARR = ROUND ([F sc/F clkenc] x 2 32 ) 

where: 

F sc = Frequency of the subcarrier 

F clkenc = Frequency of the internal video encoder 

The DSS.VENC_S_CARR register controls the subcarrier frequency. The DSS.VENC_C_PHASE register 

controls the phase of the subcarrier. The phase of the color subcarrier is reset to DSS.VENC_C_PHASE. 

Table 7-42 presents the VENC_S_CARR register values depending the standard and pixel type used. 

Table 7-42. VENC_S_CARR Register Recommended Values 

Standard Pixel Type 

Subcarrier 

Frequency (Fsc) 

(MHz) 

Fclkenc (MHz) 

VENC_S_CARR register 

value (hexa) 

NTSC-M, J ITU-R601 3.579545 27 0x21F07C1F 

PAL-M ITU-R601 3.5756083125 27 0x21E6EFE3 

PAL-B, D, G, H, I ITU-R601 4.43361875 27 0x2A098ACB 

NTSC-M, J Square pixel 3.579545 24.5454 0x25555555 

PAL-M Square pixel 3.579561149 24.5454 0x1F15C01E 

PAL-B, D, G, H, I Square pixel 4.43361875 29.50 0x26798C0C 

CAUTION 

In square pixel mode, an external clock generator is needed to provide 

sampling frequencies (49.09 MHz for NTSC square pixel or 59 MHz for PAL 

square pixel). 

The color subcarrier reset has four modes: 

• No reset 





• Reset every two lines 

• Reset every two fields 

• Reset every eight fields 

The DSS.VENC_C_PHASE register can be used to adjust the SCH (subcarrier to horizontal sync phase). 

The DSS.VENC_BSTAMP_WSS_DATA[6:0] BSTAP bit field sets the amplitude of the color burst. The 

DSS.VENC_M_CONTROL[1] PAL bit enables phase alternation line encoding. 

A phase switching subcarrier is generated to encode the chrominance signal when the 

DSS.VENC_M_CONTROL[1] PAL bit is set to 1. Otherwise, a normal subcarrier is generated. Phase 

alternation line refers to the encoding scheme in which the subcarrier alternates between two phases 

every scan line. Two possible alternation sequences are possible, and the DSS.VENC_M_CONTROL[5] 

PALPHS bit selects one of these sequences. 

7.4.7.5 Closed Caption Encoding 

The encoder can be programmed to encode closed-caption data and extended data in the selected line. 

The closed-caption data are sent to the encoder through the L4 interconnect. The data stream consists of 

7-bit US-ASCII code and 1 odd-parity bit (see Table 7-43). 

Table 7-43. Closed-Caption Data Format 

MSB LSB 

Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Odd parity 

The standard service encodes closed caption in both fields; the extended service encodes closed caption 

in even fields. When set to 1, the DSS.VENC_L21_WC_CTL L21EN[0] bit enables closed-caption 

encoding in odd fields. When set to 1, the DSS.VENC_L21_WC_CTL L21EN[1] bit enables closed-caption 

encoding in even fields. 

To select the scan line where the CC data are encoded, program the VENC_LN_SEL[4:0] SLINE bit field. 

CAUTION 

The setting of the value of the SLINE[4:0] bit field depends on the video 

standard: 

• PAL mode: Because there is a one-line offset, program the desired line 

number – 1. To activate the closed caption on line 21 (0x15), program the 

value 0x15 – 1 = 0x14. The default value is 0x15 + 1 = 0x16 (line 22). 

• NTSC mode: Because there is a four-line offset, program the desired line 

number – 4. To activate the closed caption on line 21 (0x15), program the 

value 0x15 – 4 = 0x11. The default value is 0x15 + 4 = 0x19 (line 25). 

The DSS.VENC_LN_SEL[25:16] LN21_RUNIN bit field should be kept at reset value (0x10B). Four 

closed-caption data registers contain the data to be encoded. The DSS.VENC_LINE21[15:8] L21O and 

DSS.VENC_LINE21[7:0] L21O bit fields contain the first and the second bytes, respectively, of 

closed-caption data to be encoded in the odd field. The DSS.VENC_LINE21[31:24] L21E and 

DSS.VENC_LINE21[23:16] L21E bit fields contain the first and the second bytes, respectively, of data to 

be encoded in the even field. 

Immediately after the closed-caption data is written to the registers, in either the odd field or even field, the 

corresponding closed-caption status bit (DSS.VENC_STATUS[4] CCE or DSS.VENC_STATUS[3] CCO) is 

reset to 0 to indicate that the closed-caption data is available in the closed-caption data registers and yet 

to be encoded. 

Immediately after the closed-caption data is encoded, the DSS.VENC_STATUS[4] CCE bit or the 

DSS.VENC_STATUS[3] CCO bit is set to 1 to indicate that the closed-caption data has been encoded and 

is ready to accept new data. As seen in Figure 7-107, a null character is automatically inserted if the 

closed-caption data is not written to the closed-caption data registers in time for encoding. 



1677

50 IRE 

0 

40 IRE 

Color Burst 

Hsync 

B E 

0.503/0.5 MHz 

Clock Run-in 



The running clock frequency is controlled by the DSS.VENC_CC_CARR_WSS_CARR[15:0] FCC bit field 

which should be kept at reset value (0x2631) to get 5034960.5Hz (32xfline) for NTSC-601. The 

closed-caption running clock common frequencies are detailed in Table 7-44. 

Table 7-44. Closed-Caption Run Clock Frequency Settings 

NTSC Square 

NTSC-601 PAL-601 PAL Square Pixel 

Pixel 

VENC_CC_CARR_WSS_C 

ARR[15:0] FCC bit field 0x2631 0x25ED 0x2A03 0x22B6 

value 

The closed-caption data is encoded in nonreturn-to-zero (NRZ) format. Additionally, the data translates to 

the IRE scale as follows: 0 = 0 IRE; 1 = 50 IRE. 

Figure 7-107 shows the parameters of closed-caption line data implemented in different standards. 

NOTE: 

Figure 7-107. Closed Captioning Timing 

S 

T 

A 

R 

T 

Start Bit 

Byte2 

D0-D6 

Null character 2 

P 

A 

R 

I 

T 

Y 

Byte1 

D0-D6 

Null character 1 

• The interval A is controlled by the DSS.VENC_LN_SEL[25:16] LN21_RUNIN bit field. 

• The interval B is controlled by DSS.VENC_CC_CARR_WSS_CARR[15:0] FCC bit field. 

Table 7-45. Closed-Caption Standard Timing Values 

Intervals Description Timing Values for Encoding Timing Values for Decoding 

P 

A 

R 

I 

T 

Y 

dss-080 

Minimal Nominal Maximal Lower Bound Nominal Upper Bound 

A HSYNC to clock running 10.250 µs 10.500 µs 10.750 µs 10.000 µs 10.500 µs 11.000 µs 

B Clock running 12.910 µs 12.910 µs 

Clock running to third start 

C 3.972 µs 3.972 µs 

bit 

D Start bit 1.986 µs 1.986 µs 

E Data characters 31.778 µs 31.778 µs 

NOTE: All timing values listed in Table 7-45 are measured from the mid-point (half amplitude) on all 

edges. 

For a complete description of copy protection including CGMS-A, please refer to CEA-608-x standard 





7.4.7.6 Wide-Screen Signaling (WSS) Encoding 

The encoder can embed data, encoded in accordance with the IEC61880 and ITU-R 1119 data insertion 

standard, within the vertical blanking interval. 

The encoder supports WSS data insertion on line 20 of every frame in the NTSC format. WSS data 

insertion is enabled by activating the DSS.VENC_L21_WC_CTL[14:13] EVEN_ODD_EN bit and by 

programming the VENC_BSTAMP_WSS_DATA[27:8] WSS_DATA bit field. 

The running clock frequency is controlled by the DSS.VENC_CC_CARR_WSS_CARR[31:16] FWSS bit 

field. The wide-screen signaling running clock common frequencies are detailed in Table 7-46 

Table 7-46. Wide-Screen Signaling Run Clock Frequency Settings 

NTSC Square 

NTSC-601 PAL-601 PAL Square Pixel 

Pixel 

VENC_CC_CARR_WSS_C 

ARR[31:16] FWSS bit field 0x043F 0x2F72 0x04AC 0x2B6D 

value 

To select the line where the WSS data are encoded, program the DSS.VENC_L21_WC_CTL[12:8] LINE 

bit field. 

CAUTION 

The setting of the LINE[12:8] bit field value depends on the video standard: 

• PAL mode: There is an one line offset, so program the wanted line number - 

1. The recommended value is line 0x16 + 1 = 0x17 (23rd line). Note that the 

default value is 0x14 + 1 = 0x15 (21st line). 

• NTSC mode: There is a four line offset, so program the wanted line number 

- 4. The recommended value is line 0x10 + 4 = 0x14 (20th line). Note that 

the default value is 0x14 + 4 = 0x18 (24th line). 

The WSS encoding block assumes that a full 10-bit video range is used to determine the 70 percent of 

peak-white amplitude of a logic-1 bit. The encoder also supports WSS data insertion on line 23 in the PAL 

format. Both waveforms are shown in Figure 7-108. 



1679

70 IRE 

40 IRE 

500 mV 

43 IRE 

11.2 S 

Color 

burst 

Start 

code 

1 0 

11 S 27.4 S 

Color 

burst 

Run 

IN 

Start 

code 

Data 

(D0−D13) 

49.1 S 

525-line line 20 WSS timing 

Start 

code 



Figure 7-108. WSS Timing 

625-line line 23 WSS timing 

7.4.7.7 Video DAC Stage – Architecture and Control 

Data 

(D0−D19) 

23.1 S 

Active 

video 

Figure 7-109 shows the architecture of the video DAC stage, comprising two 10-bit video DACs (AVDAC1 

and AVDAC2) instances. 



dss-081

Device 

Video 

encoder 

10 

10 

DAC stage with amplifier 

DAC 1 

DAC 2 



Figure 7-109. Video DAC Stage Architecture 

TVDET 

VREF 

TV DETECT 

TVOUT 

buffer 

TVOUT 

buffer 

TVINT 

vdda_dac vssa_dac 

GPIO2 

cvideo1_vfb 

cvideo1_out 

cvideo1_rset 

cvideo2_vfb 

cvideo2_out 

The display subsystem provides the necessary control signals to interface the memory frame buffer 

directly to external displays (TV sets). Two (one per channel) 10-bit current steering AVDACs are used to 

generate the video analog signal: 

• AVDAC1: Carries either the CVBS (composite) or S-Video Luma (Y) analog TV outputs; it provides 

also the TV detection/disconnection and power-down mode features. 

• AVDAC2 : Carries only the S-Video Chroma (C) analog TV output. 

The device system control module provides two dedicated AVDAC registers, 

CONTROL.CONTROL_AVDAC1 and CONTROL.CONTROL_AVDAC2, to configure the respective 

channels through the following bit field: 

• CONTROL.CONTROL_AVDACx [20:16] AVDACx_COMP_EN: Allows direct control over the 

configuration of the analog TV output. See Table 7-47, Section 7.5.8, Video Encoder Basic 

Programming Model, and Chapter 13, System Control Module. 

Register CONTROL.CONTROL_AVDACx [x=1, 2] Description 

Table 7-47. Analog TV Output Control 

[19] AVDACx_COMP_EN Single or dual channel operation 

0: Single channel (default) 

1: Dual channel 

[18] AVDACx_COMP_EN Channel role 

0: Luma video channel (dual-channel configuration) or Composite video 

channel (single-channel configuration) (default) 

1:Chroma video channel (dual-channel configuration) 



dss-082



Table 7-47. Analog TV Output Control (continued) 

Register CONTROL.CONTROL_AVDACx [x=1, 2] Description 

[17] AVDACx_COMP_EN Full scale swing selection 

0: High full-scale output swing: 1.3 V (default) 

1: Low full-scale output swing: 0.88 V 

[16] AVDACx_COMP_EN Current reference selection 

0: External current reference (set by external resistor connected to 

cvideo1_rset pin) (default) 

1: Internal current reference 

CAUTION 

Any change to the control register must be done only when the respective 

VDAC is off. 

High full-scale swing is the default mode. Low-swing mode does not comply 

with the NTSC and PAL video standards. It must be used only for backward 

compatibility to the OMAP35x. 

7.4.7.8 Video DC/AC Coupled TV Load 

The 10-bit video DAC stage supports both DC-coupled and AC-coupled TV loads. The 

CONTROL.CONTROL_DEVCONF1[11] TVACEN bit is used to define which output coupling is used (0: 

DC coupling; 1: AC coupling). This bit is the first one to be programed according to the TV load on the 

PCB board. 

NOTE: In high-swing mode, when DC coupling is used, there is a 180-mV DC offset at the TVOUT 

output (cvideo1_out for AVDAC1 and cvideo2_out for AVDAC2). 

In low-swing mode, when DC coupling is used, the DC offset at the maximum DAC code 

(@Max DAC current ~500 µA) is 300 mV. 

7.4.7.9 TV Detection/Disconnection Pulse Generation and Usage 

7.4.7.9.1 TV Detection/Disconnection Pulse Generation 

The TV detect block is an integral part of the video DAC stage. 

NOTE: 

• The TV detection/disconnection feature is supported only for AVDAC1. 

• The TV disconnection feature is recommended to save power. The TV 

detection/disconnection is operational only when video out is active. Therefore, to detect 

cable connection automatically, it is necessary to periodically activate the video out to 

test for cable presence. 

This block compares the output of AVDAC1 (cvideo1_out) to a reference, to sense the condition of the 

load. To operate, the TV detect requires two digital signals, TVACEN and TVDET. The TVACEN signal 

indicates to both TVOUT buffer and the TV detect circuit if the load is AC or DC coupled to adjust 

accordingly. To enable the detection of the load, the video encoder generates a negative TVDET pulse 

aligned with the TV sync pulses. The operation of the circuit is based on the difference in voltage levels in 

the output of the buffer depending on the load status. The TV detect block compares the output against a 

couple of references and the result is latched at the start of every sync pulse. The status, given by the 

TVINT output bit, is read later with the TVDET pulse rising edge. The TVINT signal of AVDAC1 is 

internally connected to channel 1 of the GPIO2 module, mapped as the TV detector interruption. 

The following registers are used to set the TV detection/disconnection pulse: 





• The DSS.VENC_TVDETGP_INT_START_STOP_X register defines which pixels are used to start and 

stop the pulse inside their respective line. 

• The DSS.VENC_TVDETGP_INT_START_STOP_Y register defines which lines are used to start and 

stop the pulse. 

• The DSS.VENC_GEN_CTRL[0] EN bit enables or disables the TVDET pulse (0: Disable; 1: Enable). 

• The DSS.VENC_GEN_CTRL[16] TVDP bit sets the TVDET pulse polarity (0: Active low; 1: Active 

high). 

7.4.7.9.2 TV Detection Procedure 

The TV detection procedure is the following: 

1. Initial setup: 

• Program the DSS.VENC_TVDETGP_INT_START_STOP_X and 

DSS.VENC_TVDETGP_INT_START_STOP_Y registers to define on which pixels and lines, 

respectively, the TVDET pulse will start and stop. 

• Set the DSS.VENC_GEN_CTRL[16] TVDP bit to 1 (reset value) for a TVDET pulse active high 

polarity. 

• Set the DSS.VENC_GEN_CTRL[0] EN bit to 1 to enable the TVDET pulse generation. 

2. The TVDET signal is set to low by hardware according to the settings in the 

DSS.VENC_TVDETGP_INT_START_STOP_X and DSS.VENC_TVDETGP_INT_START_STOP_Y 

registers. 

3. Set the VENC_OUTPUT_CONTROL[0] LUMA_ENABLE bit (in s-video mode) or the 

VENC_OUTPUT_CONTROL[1] COMPOSITE_ENABLE (in composite video mode) to 1 to enable the 

video DAC1 output. 

4. Power up the vdda_dac voltage for the DAC stage and the TVOUT buffer (repeat every TV field during 

the horizontal synchronization). This is software controlled through an I 2 C interface connected to the 

power IC. 

5. The TVDET pulse is set high by hardware according to the settings in the 


registers. 

6. Check the TVINT output signal: When TVINT is set to 1, the load is connected. 

CAUTION 

• If AC coupling is selected, two TVDET pulses are required to set high the 

TVINT signal. Due to the internal logic of the video DAC1, the TVINT signal 

is generated after the next positive edge of the TVDET signal that happens 

during the next VSYNC timing. 

• If DC coupling is selected, only one TVDET pulse is required to set high the 

TVINT signal. 

7.4.7.9.3 TV Disconnection Procedure 

The TV disconnection procedure is the following: 

1. Initial setup: 

• Program the DSS.VENC_TVDETGP_INT_START_STOP_X and 

DSS.VENC_TVDETGP_INT_START_STOP_Y registers to define on which pixels and lines, 

respectively, the TVDET pulse will start and stop. 

• Set the DSS.VENC_GEN_CTRL[16] TVDP bit to 1 (reset value) for a TVDET pulse active high 

polarity. 

• Set the DSS.VENC_GEN_CTRL[0] EN bit to 1 to enable the TVDET pulse generation. 

2. The TVDET signal is set to low by hardware according to the settings in the 


registers. 

3. The TVDET pulse is set high by hardware according to the settings in the 



1683

cvideo1_out 

(vertical sync pulse) 

TVDET 

TVINT 

TV disconnected TV connected TV disconnected 

Start of 

sync pulse 

Load 

detection 

End of 

sync pulse 

Tdm 

Status of the load is latched 

to the output on the 1st rising 

edge of TVDET 




registers. 

4. Check the TVINT output signal: When TVINT is reset to 0, the load is disconnected. 

5. Reset the VENC_OUTPUT_CONTROL[0] LUMA_ENABLE bit (in s-video mode) or the 

VENC_OUTPUT_CONTROL[1] COMPOSITE_ENABLE (in composite video mode) to 0 to disable the 

video DAC1 output. 

6. Power-down the vdda_dac voltage for the DAC stage and the TVOUT buffer (repeat every TV field 

during the horizontal synchronization). This is software controlled through an I 2 C interface connected to 

the power IC. 

CAUTION 

• If DC coupling is selected, two TVDET pulses are required to set low the 

TVINT signal. Due to the internal logic of the video DAC1, the TVINT signal 

is generated after the next positive edge of the TVDET signal that happens 

during the next VSYNC timing. 

• If AC coupling is selected, only one TVDET pulse is required to set low the 

TVINT signal. 

7.4.7.9.4 Recommended TV Detection/Disconnection Pulse Waveform 

To enable the detection/disconnection of the load, the circuit requires that the TVDET pulse resembles the 

following waveform. As explained in Section 7.4.7.9.2, TV Detection Procedure, and in Section 7.4.7.9.3, 

TV Disconnection Procedure by using the video encoder registers, the TVDET pulse polarity, start and 

stop is programmable. The only critical parameter is Tdm, which should be longer than the delay through 

the AVDAC and TVOUT buffer, which is at least 750 ns. 

If DC-coupling is selected, the TVINT output signal for TV detection is latched at the rising edge of the first 

TVDET signal but the TVINT output signal for TV disconnection is latched after the next rising edge of the 

TVDET signal that happens during the next VSYNC timing. Figure 7-110 shows the waveforms for the 

DC-coupling TV detect pulse (TVDET) when load is connected and disconnected. 

Figure 7-110. DC-Coupling TV Detect Waveforms for TV Connected and Disconnected 

Start of 

sync pulse 

Load 

detection 

End of 

sync pulse 

Start of 

sync pulse 

End of 

sync pulse 


to the output on the 2nd rising 

edge of TVDET 

If AC-coupling is selected, the TVINT output signal for TV detection is latched after the next rising edge of 

the TVDET signal that happens during the next VSYNC timing but the TVINT output signal for TV 

disconnection is latched at the rising edge of the first TVDET signal. Figure 7-111 shows the waveforms 

for the AC-coupling TV detect pulse (TVDET) when load is connected and disconnected. 



dss-083

cvideo1_out 

(vertical sync pulse) 

TV disconnected TV connected TV disconnected 

TVDET 

TVINT 

Start of 

sync pulse 

Load 

detection 

End of 

sync pulse 

Tdm Tdm 


to the output on the 2nd rising 

edge of TVDET 



Figure 7-111. AC-Coupling TV Detect Waveforms for TV Connected and Disconnected 

NOTE: 

Start of 

sync pulse 

Load 

detection 

End of 

sync pulse 


to the output on the 1st rising 

edge of TVDET 

• When setting the DSS.VENC_TVDETGP_INT_START_STOP_X register, software 

users must ensure that the TVDET signal is in the active area. To avoid any problem, 

the TVDET signal must not be longer than one line. 

• The activation of the TVDET signal will not have a visual impact on the cvideo1_out 

output signal. 

7.4.7.9.5 TV Detection/Disconnection Usage 

The TV-detection/TV-disconnection is based on the difference in voltage levels in the output of the TV 

buffer depending on the load status. The operation is slightly different for ac and for dc operation. For DC 

operation, the cvideo1_out voltage is compared against a voltage reference that makes the comparator 

trigger in each sync pulse while the load is connected. For AC operation, the cvideo1_out voltage is 

compared against a voltage reference that makes the comparator trigger in each sync pulse while the load 

is disconnected. In both cases, the TVINT output signal produces a logic 1 when a load is connected and 

a logic 0 when a load is disconnected. 

For DC-coupling mode, see Figure 7-112 and for AC-coupling mode, see Figure 7-113. 

NOTE: Because the video DAC stage and the video encoder must be awake for connection 

detection, consider that the video DAC stage can take up to 10 µs to wake up. 



dss-084 

1685

TVDET 

cvideo1_out 

TV threshold 

GPIO_33 

GPIO2_MPU_IRQ 

or 

GPIO2_IVA2_IRQ 

TVDET 

cvideo1_out 

GPIO_33 

GPIO2_MPU_IRQ 

or 

GPIO2_IVA2_IRQ 

TV threshold 

TV disconnected 


TV connected 

TV connected 



TV connected TV disconnected 

TV disconnected TV connected 





Figure 7-112. GPIO Signal Waveform Proposal for TV Detection/Disconnection in DC-Coupling Mode 

Figure 7-113. GPIO Signal Waveform Proposal for TV Detection/Disconnection in AC-Coupling Mode 

7.4.7.10 Video DAC Stage Bypass Mode 

TV connected 


TV connected TV disconnected 

The 10-bit video DAC stage has a TVOUT buffer bypass mode that turns off the TVOUT buffers and 

redirects directly the outputs of the DACs to the VFB pins (cvideo1_vfb for AVDAC1 and cvideo2_vfb for 

AVDAC2). 

This bypass mode is activated by setting the CONTROL.CONTROL_DEVCONF1[18] TVOUTBYPASS bit 

to 1. The reset value of the CONTROL.CONTROL_DEVCONF1[18] TVOUTBYPASS bit is 0 (that is, the 

TVOUT buffer is not bypassed). 

NOTE: In bypass mode: 

• The cvideo1_rset pin requires a Rset resistor connected to the ground. The typical value 

of the Rset resistor is 10K. 

• Both cvideo1_vfb and cvideo2_vfb pins require a Rout resistors connected to the ground. 

The typical values of Rout1 and Rout2 resistors are 1,5K. 



dss-085 

dss-086

RGB[23:0] 

Video Encoder Module 

DAC TEST register: 

VENC_OUTPUT_TEST[9:0] 

COMPOSITE_TEST (DAC1) 

RGB[9:0] 



CAUTION 

• The TV detect feature is not available in bypass mode. 

• In bypass mode, an external amplifier is needed on the cvideo1_vfb and 

cvideo2_vfb pins. 

7.4.7.11 Video DAC Stage Test Mode 

The DAC stage can be tested for debug using either 10-bit external data or 10-bit internal register values 

directly connected to the DACs. See Figure 7-114 for video DAC test in composite video mode, and see 

Figure 7-115 for video DAC test in separate video mode. 

Figure 7-114. DAC Test Mode in Composite Video Mode 

0 

1 

CVBS[9:0] 

(DAC1) 

VENC_OUTPUT_CONTROL[4] 

TEST_MODE 

VENC_OUTPUT_CONTROL[6] COMPOSITE_SOURCE for DAC1 

0 

1 

DAC[9:0] 



dss-087 

1687

RGB[23:0] 

Video Encoder Module 

DAC TEST registers: 

VENC_OUTPUT_CONTROL[25:16] 

LUMA_TEST (DAC1) or 

VENC_OUTPUT_TEST[25:16] 

CHROMA_TEST (DAC2) 

RGB[9:0] 



Figure 7-115. DAC Test Mode in Separate video Mode 

0 

1 

Y[9:0] 

(DAC1) 

C[9:0] 

(DAC2) 

VENC_OUTPUT_CONTROL[4] 

TEST_MODE 

VENC_OUTPUT_CONTROL[5] LUMA_SOURCE for DAC1 

or 

VENC_OUTPUT_CONTROL[7] CHROMA_SOURCE for DAC2 

0 

1 

DAC[9:0] 

• Use the DSS.VENC_OUTPUT_CONTROL[4] TEST_MODE bit to select between DAC normal mode 

(0x0) and DAC test mode (0x1). 

• Use the DSS.VENC_OUTPUT_CONTROL[7] CHROMA_SOURCE bit for AVDAC2 and either the 

DSS.VENC_OUTPUT_CONTROL[6] COMPOSITE_SOURCE bit (in composite video mode) or the 

DSS.VENC_OUTPUT_CONTROL[5] LUMA_SOURCE bit (in s-video mode) for AVDAC1 to select the 

test mode: 

– 0x0: From the internal register DSS.VENC_OUTPUT_TEST[25:16] CHROMA_TEST bit field for 

AVDAC2 and either DSS.VENC_OUTPUT_TEST[9:0] COMPOSITE_TEST bit field (composite 

video) or DSS.VENC_OUTPUT_CONTROL[25:16] LUMA_TEST (s-video mode) for AVDAC1 

– 0x1: From the video port G[1:0], B[7:0] 

NOTE: In the external data test mode (bypass mode), the display controller must provide the data 

(G[1:0], B[7:0]) externally. To do this, configure the video encoder to generate correct timing 

signals, without which the display controller cannot operate (even if the encoder core is 

bypassed from the data path perspective). 

7.4.7.12 Video DAC Stage Power Management 

After device reset, the DSS_CONTROL[5] DAC_POWERDN_BGZ register bit is set to 0, and the video 

DAC stage is powered down. 

Table 7-48 shows possible power management configurations and the corresponding register settings. 



dss-088



Table 7-48. Video DAC Stage Power Management 

AVDAC2 AVDAC1 

Power Management Controls 

DSS_CONTRO VENC_OUTPUT_ VENC_OUTPUT_C VENC_OUTPUT 

CONTROL_DEV CONTROL_D 

L[5] CONTROL[2] ONTROL[1] _CONTROL[0] 

CONF1[18] EVCONF1[11] Description 

DAC_POWERD CHROMA_ENAB COMPOSITE_ENA LUMA_ENABL 

TVOUTBYPASS TVACEN 

N_BGZ LE BLE E 

Total power down. 

0 x x x x x Bandgaps powered 

down. 

Standby (analog in 

1 0 0 0 x x power down except 

bandgaps/LDOs) 

1 1 1 1 0 0 

1 1 1 1 0 1 

Full power up in DC 

mode 

Full power up in AC 

mode 

Full power up in 

1 1 1 1 1 x TVOUT bypass mode 

(DAC-only mode) 



1689


Display Subsystem Basic Programming Model www.ti.com 

7.5 Display Subsystem Basic Programming Model 

This section describes how to configure the display subsystem for the desired functionalities and also 

describes the programming models of the display controller, the RFBI and the video encoder. 

The main configuration scenarios are: 

• LCD panel support (bypass or RFBI mode) 

Configure the RFBI module (only if in RFBI mode; otherwise, the default values must remain), and then 

configure the display controller to the desired functionalities before the activities start. 

• TV set support 

Configure the video encoder and then the display controller. 

• Both LCD panel support (bypass or RFBI mode) and TV set support 

Configure the RFBI module (only if in RFBI mode; otherwise, leave the default values), configure the 

video encoder, and then configure the display controller. 

7.5.1 Display Subsystem Reset 

The display subsystem can receive a software reset that is propagated through all of the submodules to 

initialize the subsystem. The following procedure describes a possible sequence: 

1. If the LCD is on, stop the LCD by setting the DSS.DISPC_CONTROL[0] LCDENABLE bit to 0. 

(a) Reset the frame done status bit by writing 1 in the DSS.DISPC_IRQSTATUS[0] FRAMEDONE bit. 

(b) Wait until the DSS.DISPC_IRQSTATUS[0] FRAMEDONE bit is set to 1. This shows that the end of 

frame has taken place and the LCD stop is complete. 

2. To take the display subsystem out of reset, all clocks related to the display subsystem must be 

enabled and the DPLL4 must be enabled. The following clocks must be enabled to take the display 

subsystem out of reset: 

• PRCM.CM_FCLKEN_DSS[0] EN_DSS1 bit set to 1 

• PRCM.CM_FCLKEN_DSS[1] EN_DSS2 bit set to 1 

• PRCM.CM_FCLKEN_DSS[2] EN_TV bit set to 1 

• PRCM.CM_ICLKEN_DSS[0] EN_DSS bit set to 1 

Once the clocks are enabled as shown, the display subsystem can be taken out of reset. 

3. Write 1 in the DSS.DSS_SYSCONFIG[1] SOFTRESET bit to apply the soft reset to the subsystem. 

4. Read the DSS.DSS_SYSSTATUS[0] RESETDONE bit. If this bit is 1, the reset sequence is complete; 

otherwise, read this bit again (the reset sequence is not completed). 

7.5.2 Display Subsystem Configuration Phase 

The display subsystem configuration phase is important to configure the data flow for using the LCD panel 

or the TV set. Use the following flow: 

1. To configure the top level of the functional clock of the display controller clock, set the 

DSS.DSS_CONTROL[0] DSS_CLK_SWITCH bit. 

2. To configure the top level of the video encoder, set the DSS.DSS_CONTROL[2] 

VENC_CLOCK_MODE bit and the DSS.DSS_CONTROL[3] VENC_CLOCK_X4 bit for TV set support. 

3. To configure the top level of the DAC stage, set the DSS.DSS_CONTROL[4] DAC_DEMEN bit for TV 

set support (if required). 

4. Configure the RFBI module and/or the video encoder as needed. 

5. Configure the display controller. 

7.5.3 Display Controller Basic Programming Model 

Some display controller registers are termed shadow registers, which are associated with the digital output 

and/or the LCD output. A shadow register change has no direct effect on the configuration of the display 

controller unless the DSS.DISPC_CONTROL[5] GOLCD bit is set for the LCD output and/or the 

DSS.DISPC_CONTROL[6] GODIGITAL bit is set for the digital output. 




www.ti.com Display Subsystem Basic Programming Model 

In the case of the digital output, after programming the shadow registers, the DSS.DISPC_CONTROL[6] 

GODIGITAL bit must be set to 1. If this bit is not set, the configuration of the display controller will have no 

effect. This setting indicates that all display controller shadow registers are programmed and that 

hardware can update the internal registers at the external EVSYNC. 

In the case of the LCD output, after programming the shadow registers, the DSS.DISPC_CONTROL[5] 

GOLCD bit must be set to 1. If this bit is not set, the configuration of the display controller will have no 

effect. This setting indicates that all display controller shadow registers are programmed and that 

hardware can update the internal registers at the VFP start period. 

Before setting either the DSS.DISPC_CONTROL[5] GOLCD or DSS.DISPC_CONTROL[6] GODIGITAL 

bit, ensure that the bit is cleared. 

Table 7-49 lists the shadow registers. 

Table 7-49. Shadow Registers 

Shadow Register Name Updated on VFP Start Period Updated on External VSYNC 

(LCD output) (Digital output) 

DSS.DISPC_CONTROL X (1) 

DSS.DISPC_CONFIG X X 

DSS.DISPC_DEFAULT_COLOR_m (m = 0) X 

DSS.DISPC_DEFAULT_COLOR_m (m = 1) X 

DSS.DISPC_TRANS_COLOR_m (m = 0) X 

DSS.DISPC_TRANS_COLOR_m (m = 1) X 

DSS.DISPC_LINE_NUMBER X 

DSS.DISPC_TIMING_H X 

DSS.DISPC_TIMING_V X 

DSS.DISPC_POL_FREQ X 

DSS.DISPC_DIVISOR X 

DSS.DISPC_SIZE_DIG X 

DSS.DISPC_SIZE_LCD X 

DSS.DISPC_GFX_BAj (j = 0,1) X X 

DSS.DISPC_GFX_POSITION X X 

DSS.DISPC_GFX_SIZE X X 

DSS.DISPC_GFX_ATTRIBUTES X X 

DSS.DISPC_GFX_FIFO_THRESHOLD X X 

DSS.DISPC_GFX_ROW_INC X X 

DSS.DISPC_GFX_PIXEL_INC X X 

DSS.DISPC_GFX_WINDOW_SKIP X X 

DSS.DISPC_GFX_TABLE_BA X X 

DSS.DISPC_GFX_PRELOAD X X 

DSS.DISPC_CPR_COEF_R X 

DSS.DISPC_CPR_COEF_G X 

DSS.DISPC_CPR_COEF_B X 

DSS.DISPC_VIDn_BAj (j= 0,1) X X 

DSS.DISPC_VIDn_POSITION X X 

DSS.DISPC_VIDn_SIZE X X 

DSS.DISPC_VIDn_ATTRIBUTES X X 

DSS.DISPC_VIDn_FIFO_THRESHOLD X X 

DSS.DISPC_VIDn_ROW_INC X X 

DSS.DISPC_VIDn_PIXEL_INC X X 

DSS.DISPC_VIDn_FIR X X 

DSS.DISPC_VIDn_PICTURE_SIZE X X 

(1) Some of the register bit fields are shadow bits. For more information, see Section 7.7, Display Subsystem Register Manual. 



X (1)



Table 7-49. Shadow Registers (continued) 

Shadow Register Name Updated on VFP Start Period Updated on External VSYNC 

(LCD output) (Digital output) 

DSS.DISPC_VIDn_ACCUl (l = 0,1) X X 

DSS.DISPC_VIDn_FIR_COEF_Hi (i = 0 to 7) X X 

DSS.DISPC_VIDn_FIR_COEF_HVi (i = 0 to 7) X X 

DSS.DISPC_VIDn_FIR_COEF_Vi (i = 0 to 7) X X 

DSS.DISPC_VIDn_CONV_COEFi (i = 0 to 4) X X 

DSS.DISPC_VIDn_PRELOAD X X 

DSS.DISPC_DATA_CYCLEk (k = 0 to 3) X 

7.5.3.1 Display Controller Configuration 

The following registers define the display controller configuration: 

• DSS.DISPC_SYSCONFIG 

• DSS.DISPC_SYSSTATUS 

• DSS.DISPC_IRQSTATUS 

• DSS.DISPC_IRQENABLE 

7.5.3.2 Graphics Layer Configuration 

The graphics layer configuration is common to the LCD and the TV set. 

7.5.3.2.1 Graphics DMA Registers 

The following registers define the graphics DMA engine configuration: 

• DSS.DISPC_CONTROL 

• DSS.DISPC_GFX_BAj 

• DSS.DISPC_GFX_ATTRIBUTES 

• DSS.DISPC_GFX_ROW_INC 

• DSS.DISPC_GFX_PIXEL_INC 

• DSS.DISPC_GFX_FIFO_THRESHOLD 

• DSS.DISPC_GFX_TABLE_BA 

The following fields define the attributes of the graphics DMA engine: 

• Graphics layer enable (DSS.DISPC_GFX_ATTRIBUTES[0] GFXENABLE bit): The default value of this 

bit at reset time is 0x0 (Disabled). The graphics DMA engine fetches encoded pixels from the system 

memory only when the graphics layer is enabled (a valid configuration is programmed for the graphics 

layer). The graphics window is present and the graphics pipeline is active. 

• Burst size (DSS.DISPC_GFX_ATTRIBUTES[7:6] GFXBURSTSIZE field): The default burst size at 

reset time is 4 x 32 bytes. The possible values are 4 x 32, 8 x 32, and 16 x 32 bytes. The burst size is 

initialized at boot time by the software and never changes as long as the display controller is enabled. 

This field indicates the maximum burst size for the specific pipeline. In case of misalignment, the DMA 

engine may issue single and/or smaller burst requests because the burst size must be aligned to the 

burst boundary. 

• Preload configuration (DSS.DISPC_GFX_ATTRIBUTES[11] GFXFIFOPRELOAD bit): The default 

preload configuration uses the DSS.DISPC_GFX_PRELOAD register value (the reset value is 256 

bytes) to define the number of bytes to be fetched from system memory into the display controller 

graphics FIFO. By programming the DSS.DISPC_GFX_ATTRIBUTES[11] GFXFIFOPRELOAD bit, 

software users select between preload register (with 256 bytes as the reset value) and the high 

threshold value for preload of the encoded pixels. For best performance, the configuration of 

thresholds is defined using the FIFO size (in bytes) minus 1 for the high threshold, and the FIFO size 

(in bytes) minus the burst size (in bytes) for the low threshold, which provides 960, 992, and 1008, 

respectively, for burst sizes 16x32, 8x32, and 4x32. Note also that the preload value is defined based 

on the following display types: 





– Active matrix (TFT) display: DSS.DISPC_GFX_PRELOAD[11:0] PRELOAD = 0x60 (value is 96) 

– Color passive matrix (STN) display: DSS.DISPC_GFX_PRELOAD[11:0] PRELOAD = 0x72 (value is 

114) 

– Monochrome passive matrix (STN) display: DSS.DISPC_GFX_PRELOAD[11:0] PRELOAD = 0xE0 

(value is 224) 

• Base address of the graphics buffer in system memory (DSS.DISPC_GFX_BAj registers): The default 

value of these two registers at reset time is 0x0. The horizontal resolution is one pixel because the 

base address is aligned on a pixel size boundary. In case of 4 BPP, the resolution is two pixels; for 2 

BPP, resolution is four pixels; for 1 BPP, resolution is eight pixels; and for RGB24 packed format, the 

resolution is four pixels. The vertical resolution is one line. The register DSS.DISPC_GFX_BA0 defines 

the base address of the even field; and DSS.DISPC_GFX_BA1 defines the base of the odd field in the 

case of an external synchronization and based on the value of the input signal DISPC_FID and the 

polarity. To improve system throughput, the base address should be aligned on the burst size 

boundary. 

• Graphics FIFO threshold (DSS.DISPC_GFX_FIFO_THRESHOLD register): The low threshold 

(DSS.DISPC_GFX_FIFO_THRESHOLD[11:0] GFXFIFOLOWTHRESHOLD) and the high threshold 

(DSS.DISPC_GFX_FIFO_THRESHOLD[27:16] GFXFIFOHIGHTHRESHOLD) values define the FIFO 

DMA behavior. When the low level is reached, one or more requests are issued to the L3-based 

interconnect to fill up the FIFO to reach the high threshold. A request is issued as long as the FIFO 

has enough space available to accept a burst. The DMA engine then waits until the low level is 

reached to restart the requests. By setting the DSS.DISPC_CONFIG[14] FIFOMERGE bit to 1, users 

merge the three FIFOs (GFX, VID1, and VID2). In this case, the low threshold (the 

DSS.DISPC_GFX_FIFO_THRESHOLD[11:0] GFXFIFOLOWTHRESHOLD bit field) and the high 

threshold (DSS.DISPC_GFX_FIFO_THRESHOLD[27:16] GFXFIFOHIGHTHRESHOLD bit field) values 

must be programmed with a multiplier factor of three (3 x value). By default, the FIFOs are not merged 

(the DSS.DISPC_CONFIG[14] FIFOMERGE bit reset value is 0). 

• Palette/gamma table used (DSS.DISPC_CONFIG[3] PALETTEGAMMATABLE bit): The bit indicates if 

the palette must be loaded before the graphics data for the following frame. The bit is set by software 

and reset by hardware. 

• Base address of the palette/gamma table buffer in system memory (DSS.DISPC_GFX_TABLE_BA 

register): The default value of this register at reset time is 0x0. The base address is aligned on a 32-bit 

address. Depending on the pixel size of graphics data (1, 2, 4, or 8 BPP), 16 (1, 2, or 4 BPP), or 256 

(8 BPP) x 32-bit values are loaded from system memory into the internal table memory. To load the 

table when using the memory as a gamma table, the graphics pipeline is enabled and then disabled by 

the software when the palette loaded interrupt is generated. The overlay manager ignores the graphics 

pipe when the table is used as a gamma table. 

NOTE: In case of RGB16 format and optimization enabled, the base address is aligned on a 32-bit 

boundary and the number of bytes to skip is a multiple of 4 bytes. 

• Graphics Priority (DSS.DISPC_GFX_ATTRIBUTES[14] GFXARBITRATION): The default value at reset 

time is 0x0. It is used to change between normal priority (value of 0) to high priority (value of 1) to 

change priority for the graphics channel vs. video channels. It can be used to give higher priority to the 

pipelines with real time constraint vs. non real time pipelines. For that is, pipelines associated to the 

LCD output in RFBI mode should have lower priority than pipelines associated to TV output. 

• Graphics Self-Refresh (DSS.DISPC_GFX_ATTRIBUTES[15] GFXSELFREFRESH): The default value 

at reset time is 0x0. It is used to use the DMA FIFO without accessing the interconnect for multiple 

frames. Once, the data have been loaded to the DMA FIFO for displaying the frame, they are used for 

the following frames. 

The sequence to activate the self-refresh is the following: 

– Frame t: The bit field should be set at anytime during frame 

– Frame t+1: Fetch of the data in the DMA FIFO and display of the frame 

– Frame t+2: No access to the L3 interconnect, DMA FIFO uses to provide the pixels 

The sequence to deactivate the self-refresh is the following: 

– Frame t: No access to the L3 interconnect, DMA FIFO uses to provide the pixels, bit field can be 

changed at any time during the frame 

– Frame t+1: Fetch of the data from system memory using the L3 interconnect 



1693



7.5.3.2.2 Graphics Layer Configuration Registers 

The following registers define the graphics layer configuration: 

• DSS.DISPC_CONFIG 

• DSS.DISPC_GFX_POSITION 

• DSS.DISPC_GFX_SIZE 

• DSS.DISPC_GFX_ATTRIBUTES 

The graphics layer is enabled/disabled by setting/resetting the DSS.DISPC_GFX_ATTRIBUTES[0] 

GFXENABLE bit. When the graphics layer is disabled, the graphics window does not exist on the screen 

and the graphics pipeline and DMA are inactive. 

Set a valid configuration before enabling the graphics layer. After a register change, either the 

DSS.DISPC_CONTROL[6] GODIGITAL or DSS.DISPC_CONTROL[5] GOLCD bit must be set. The 

software must wait for the hardware to reset the bit before setting it. The software reset is not 

recommended because the application cannot ensure that the bit is reset before the hardware reset. 

7.5.3.2.3 Graphics Window Attributes 

The following fields define the attributes of the graphics window: 

• Graphics format (DSS.DISPC_GFX_ATTRIBUTES[4:1] GFXFORMAT bit field): The default value of 

this bit field at reset time is 0x0 (BITMAP 1-BPP). The graphics format can be either: BITMAP1, 

BITMAP2, BITMAP4, or BITMAP8 (CLUT) or RGB12, RGB16, or RGB24 (true-color formats). 

• Graphics window X-position (DSS.DISPC_GFX_POSITION[10:0] GFXPOSX bit field): The default 

value at reset time is 0x0. The window X-position is from 0 to 2047 columns. All integer values in the 

range [0:2047] are allowed. 

• Graphics window Y-position (DSS.DISPC_GFX_POSITION[26:16] GFXPOSY bit field): The default 

value of this bit field at reset time is 0x0.The window Y-position is from 0 to 2047 rows. All integer 

values in the range [0:2047] are allowed. 

• Graphics window width (DSS.DISPC_GFX_SIZE[10:0] GFXSIZEX bit field): The default value at reset 

time is 0x0 (1 pixel). The window width is from 1 to 2048 pixels. All integer values in the range [1:2048] 

are allowed for the following formats: 8 BPP, RGB12, RGB16, and RGB24. The width must be a 

multiple of eight pixels for 1 BPP, four pixels for 2 BPP, and two pixels for 4 BPP. The maximum 

bandwidth efficiency for accessing the pixels in system memory is reached when the width of the 

graphics window (in bytes) is a multiple of the graphics burst size defined in the 

DSS.DISPC_GFX_ATTRIBUTES[7:6] GFXBURSTSIZE bit field (in bytes). 

NOTE: When the RGB24 packed format is selected, the width must be a multiple of 12 bytes when 

the DSS.DISPC_GFX_ROW_INC register is not 1. When DSS.DISPC_GFX_ROW_INC 

register is 1, the width can be any size from 1 to 2048 pixels. 

The entire pixels of the graphics window must be inside the LCD screen. Depending on the 

width of the buffer to be displayed in the graphics layer and the position, the width should be 

adjusted by software to limit the right edge of the window inside the screen. 

• Graphics window height (DSS.DISPC_GFX_SIZE[26:16] GFXSIZEY bit field): The default value at 

reset time is 0x0 (1 pixel). The window height is from 1 to 2048 pixels. All integer values in the range 

[1:2048] are allowed. The entire pixels of the graphics window must be inside the LCD screen. 

Depending on the height of the buffer to be displayed in the graphics layer and the position, the height 

should be adjusted by software to limit the bottom edge of the window inside the screen 

• Graphics data endianness (DSS.DISPC_GFX_ATTRIBUTES[10] GFXENDIANNESS bit): This bit 

indicates the endianness (little or big) of the graphics pixels. The default value at reset time is 0x0 (little 

endian). 

• Graphics data nible mode (DSS.DISPC_GFX_ATTRIBUTES[9] GFXNIBBLEMODE bit): This bit 

indicates the nibble mode of the graphics pixels. The default value at reset time is 0x0 (Disable). 

• Graphics replication logic enable (DSS.DISPC_GFX_ATTRIBUTES[5] GFXREPLICATIONENABLE 

bit): The default value at reset time is 0x0 (Disable). The encoded pixel data in RGB format (RGB16) 

can be extended to 24-bit format with or without replication of the MSB part to fill up the LSB due to the 

24-bit left alignment. If the replication logic is turned off, the LSB part is filled up with 0s. 



GFX 

GFX 

GFX 

X = DISPC_GFX_SIZE[10:0] GFXSIZEX + 1 

VID1 

VID1 

VID1 

Y 

Y 

Y = DISPC_VID1_POSITION[26:16] VIDPOSY + DISPC_VID1_SIZE[26:16] VIDSIZEY 

– DISPC_GFX_POSITION[26:16] GFXPOSY + 1 





• Graphics window skip enable (DSS.DISPC_CONTROL[12] OVERLAYOPTIMIZATION bit): By 

setting/resetting the bit, the overlay optimization is enabled or disabled. Before enabling the overlay 

optimization, the DSS.DISPC_GFX_WINDOW_SKIP[31:0] GFXWINDOWSKIP bit field must be set 

according to the video1 and graphics windows overlap. The default value at reset time is 0x0 (Disable). 

When video1 is not present, the DSS.DISPC_GFX_WINDOW_SKIP[31:0] GFXWINDOWSKIP bit field 

should be reset. When the color key is used, the DSS.DISPC_GFX_WINDOW_SKIP[31:0] 

GFXWINDOWSKIP bit field should be reset. 

• Graphics window skip (DSS.DISPC_GFX_WINDOW_SKIP[31:0] GFXWINDOWSKIP bit field): The bit 

field represents the number of bytes to skip while fetching the graphics-encoded pixels when reaching 

the beginning of the video window. The optimization allows fetching only the visible graphics pixels. 

The color key cannot be selected because the graphics pixels under the video window are not present. 

The default value at reset time is 0x0 (0 byte). 

Figure 7-116 through Figure 7-119 give examples of how to program the GFXWINDOWSKIP field for 

overlay optimization: 

Figure 7-116. Overlay Optimization: Case 1 

Y = DISPC_VID1_SIZE[26:16] VIDSIZEY + 1 

Y = DISPC_GFX_POSITION[26:16] GFXPOSY + DISPC_GFX_SIZE[26:16] GFXSIZEY 

- DISPC_VID1_POSITION[26:16] VIDPOSY + 1 

DISPC_GFX_WINDOW_SKIP[31:0] 

= Y * [X* (DISPC_GFX_PIXEL_INC[15:0] 

GFCPIXELINC + BPP) + 

DISPC_GFX_ROW_INC[31:0] GFXROWINC – 1 + BPP] 

BPP defines the number of bytes per pixel for graphics buffer. 



dss-090 

1695

VID1 

OR 

OR 

OR 

GFX GFX 

GFX 

VID1 GFX 

VID1 

X 

X 

X 

X 

X = DISPC_VID1_POSITION[10:0] VIDPOSX + DISPC_VID1_SIZE[10:0] VIDSIZEX 

– DISPC_GFX_POSITION[10:0]GFXPOSX + 1 

GFX 

VID1 

OR 

VID1 

GFX 

VID1 

OR 

VID1 

GFX 

X 

X 

X = DISPC_GFX_POSITION[10:0] GFXPOSX + DISPC_GFX_SIZE[10:0] GFXSIZEX 

-DISPC_VID1_POSITION[10:0] VIDPOSX + 1 

X 

X 

VID1 

GFX 

OR 

VID1 

GFX 

X = DISPC_VID1_SIZE[10:0]VIDSIZEX + 1 

GFX 

X 

VID1 

OR 

GFX 

X 

VID1 

X 

OR 

OR 

GFX 

X = DISPC_VID1_SIZE[10:0] VIDSIZEX + 1 




X 

GFX 

VID1 

X 

VID1 



=X* (DISPC_GFX_PIXEL_INC[15:0] 

GFCPIXELINC – 1 + BPP) 

BPP defines the number of bytes per pixel 

for graphics buffer. 


= X* (DISPC_GFX_PIXEL_INC[15:0] 

GFCPIXELINC – 1 + BPP) + 1 

dss-091 

BPP defines the number of bytes per pixel for 

graphics buffer. 



dss-092

X X 

GFX 

VID1 VID1 

VID1 => GFX 

GFX 



7.5.3.3 Video Layer Configuration 


The video layer configuration is common to the LCD and the TV set. 

7.5.3.3.1 Video DMA Registers 

The following registers define the video DMA engine configuration: 


• DSS.DISPC_VIDn_BAj 

• DSS.DISPC_VIDn_ATTRIBUTES 

• DSS.DISPC_VIDn_ROW_INC 

• DSS.DISPC_VIDn_PIXEL_INC 

• DSS.DISPC_VIDn_FIFO_THRESHOLD 

• DSS.DISPC_VIDn_PICTURE_SIZE 

The following fields define the attributes of the graphics DMA engine: 

Y 

When the VID1 window overlaps the 

GFX window equally or more, the 

DISPC_GFX_ATTRIBUTES[0] GFX 

ENABLE bit should be clear. 

camdss-093 

• Video layer enable (DSS.DISPC_VIDn_ATTRIBUTES[0] VIDENABLE bit): The default value of this bit 

at reset time is 0x0 (Disabled). The video DMA engine fetches encoded pixels from the system 

memory only when the video layer is enabled (a valid configuration is programmed for the video layer). 

The video window is present and the video pipeline is active. 

• Burst size (DSS.DISPC_VIDn_ATTRIBUTES[15:14] VIDBURSTSIZE bit field): The default burst size at 

reset time is 4 x 32 bytes. The possible values are 4 x 32, 8 x 32, and 16 x 32 bytes. The burst size is 

initialized at boot time by the software and never changes as long as the display controller is enabled. 

This bit field indicates the maximum burst size for the specific pipeline. In case of misalignment, the 

DMA engine may issue single and/or smaller burst requests, because the burst size must be aligned to 

the burst boundary. 

• Preload configuration (DSS.DISPC_VIDn_ATTRIBUTES[19] VIDFIFOPRELOAD bit): The default 

preload configuration uses the DSS.DISPC_VIDn_PRELOAD register value (the reset value is 256 

bytes) to define the number of bytes to be fetched from system memory into the display controller 

graphics FIFO. By programming the DSS.DISPC_VIDn_ATTRIBUTES[19] VIDFIFOPRELOAD bit, 

software users select between preload register (with 256 bytes as the reset value) and the high 

threshold value for preload of the encoded pixels. For best performance, the configuration of 

thresholds is defined using the FIFO size (in bytes) minus 1 for the high threshold, and the FIFO size 

(in bytes) minus the burst size (in bytes) for the low threshold, which provides 960, 992, and 1008, 

respectively, for burst sizes 16x32, 8x32, and 4x32. Note also that the preload value is defined based 

on the following display types: 

– Active matrix (TFT) display: DSS.DISPC_VIDn_PRELOAD[11:0] PRELOAD = 0xB0 (value is 176) 

– Color passive matrix (STN) display: DSS.DISPC_VIDn_PRELOAD[11:0] PRELOAD = 0x110 (value 

is 272) 

– Monochrome passive matrix (STN) display: DSS.DISPC_VIDn_PRELOAD[11:0] PRELOAD = 

0x1B0 (value is 432) 

• Base address of the video buffer in system memory (DSS.DISPC_VIDn_BAj registers): The default 



1697



value at reset time is 0x0. The horizontal resolution is one pixel because the base address is aligned 

on pixel size boundary. In case of YCbCr 4:2:2 formats, the resolution is 2 pixels. In case of RGB24 

packed format, the resolution is 4 pixels. The vertical resolution is one line. The register 

DSS.DISPC_VIDn_BA0 defines the base address of the even field, and DSS.DISPC_VIDn_BA1 

defines the base of the odd field in the case of an external synchronization and based on the value of 

the input signal DISPC_FID and the polarity. To improve system throughput, the base address should 

be aligned on the burst size boundary. 

• Video FIFO threshold (DSS.DISPC_VIDn_FIFO_THRESHOLD register): The low threshold 

(DSS.DISPC_VIDn_FIFO_THRESHOLD[11:0] VIDFIFOLOWTHRESHOLD) and the high threshold 

(DSS.DISPC_VIDn_FIFO_THRESHOLD[27:16] VIDFIFOHIGHTHRESHOLD) values define the FIFO 

DMA behavior. When the low level is reached, one or more requests are issued to the L3-based 

interconnect to fill up the FIFO to reach the high threshold. A request is issued as long as the FIFO 

has enough space available to accept a burst. The DMA engine then waits until the low level is 

reached to restart the requests. By setting the DSS.DISPC_CONFIG[14] FIFOMERGE bit to 1, users 

merge the three FIFOs (GFX, VID1, and VID2). In this case, the low threshold (the 

DSS.DISPC_VIDn_FIFO_THRESHOLD[11:0] VIDFIFOLOWTHRESHOLD bit field with n 

corresponding to the active video channel 1 or 2) and the high threshold 

(DSS.DISPC_VIDn_FIFO_THRESHOLD[27:16] VIDFIFOHIGHTHRESHOLD bit field with n 

corresponding to the active video channel 1 or 2) values must be programmed with a multiplier factor 

of three (3 x value). By default, the FIFOs are not merged (the DSS.DISPC_CONFIG[14] FIFOMERGE 

bit reset value is 0). 

• Video buffer width (DSS.DISPC_VIDn_PICTURE_SIZE[10:0] VIDORGSIZEX): The default value at 

reset time is 0x0 (1 pixel). The buffer width in system memory is from 1 up to 2048 pixels. All the 

integer values in the range [1:2048] are allowed. Software users must program this bit field to the value 

minus 1. 

• Video buffer height (DSS.DISPC_VIDn_PICTURE_SIZE[26:16] VIDORGSIZEY): The default value at 

reset time is 0x0 (1 pixel). The buffer height in system memory is from 1 up to 2048 pixels. All the 

integer values in the range [1:2048] are allowed. Software users must program this field to the value 

minus 1. 

• Video data endianness (DSS.DISPC_VIDn_ATTRIBUTES[17] VIDENDIANNESS bit, with n=1 or 2): 

This bit indicates the endianness (little or big) of the video pixels. The default value at reset time is 0x0 

(little endian). 

7.5.3.3.2 Video Configuration Register 

The following shadow registers define video layer n (with n = 1 or 2) configuration: 


• DSS.DISPC_VIDn_POSITION 

• DSS.DISPC_VIDn_SIZE 


• DSS.DISPC_VIDn_FIR 

• DSS.DISPC_VIDn_PICTURE_SIZE 

• DSS.DISPC_VIDn_FIR_COEF_Hi (with i = 0 to 7) 

• DSS.DISPC_VIDn_FIR_COEF_HVi (with i = 0 to 7) 

• DSS.DISPC_VIDn_CONV_COEFi (with i = 0 to 4) 

• The video layer n (with n = 1 or 2) is enabled/disabled by setting/resetting the 

DSS.DISPC_VIDn_ATTRIBUTES[0] VIDENABLE field. If the video layer is disabled, the video window 

does not exist on the screen and the whole video pipeline and DMA are inactive. Before enabling the 

video layer, a valid configuration must be set. After a register change, either the 

DSS.DISPC_CONTROL[6] GODIGITAL or DSS.DISPC_CONTROL[5] GOLCD bit must be set. The 

software must wait for the hardware to reset the bit before setting this bit. The software reset is not 

recommended because the application cannot ensure that the bit is reset before the hardware reset. 

7.5.3.3.3 Video Window Attributes 

The following fields define the attributes of video window n: 





• Video format (DSS.DISPC_VIDn_ATTRIBUTES[4:1] VIDFORMAT bit field, with n = 1 or 2): The default 

value at reset time is 0x0 (BITMAP 1 BPP, nonsupported format by the video pipeline).The video 

format can be RGB16, RGB24, YUV2 4:2:2 co-DSS sited, and UYVY 4:2:2 co-sited. 

• Video window X-position (DSS.DISPC_VIDn_POSITION[10:0] VIDPOSX bit field, with n = 1 or 2): The 

default value at reset time is 0x0 (first column starting on the left edge of the screen). The window 

X-position is from 0 to 2047 columns. All integer values in the range [0:2047] are allowed. 

• Video window Y-position (DSS.DISPC_VIDn_POSITION[26:16] VIDPOSY bit field, with n = 1 or 2): 

The default value at reset time is 0x0 (first row starting at the top of the screen). The window Y-position 

is from 0 to 2047 rows. All integer values in the range [0:2047] are allowed. 

• Video window width (DSS.DISPC_VIDn_SIZE[10:0] VIDSIZEX bit field, with n = 1 or 2): The default 

value at reset time is 0x0 (1 pixel). The window width is from 1 to 2048 pixels. All integer values in the 

range [1:2048] are allowed. The maximum bandwidth efficiency for accessing the pixels in system 

memory is reached when the width (in bytes) of the video window is a multiple of the video burst size 

defined in the DSS.DISPC_VIDn_ATTRIBUTES[15:14] VIDBURSTSIZE bit field (in bytes). 

NOTE: When the RGB24 packed format is selected, the width must be a multiple of 12 bytes when 

the DSS.DISPC_VIDn_ROW_INC register is not 1. When the DSS.DISPC_VIDn_ROW_INC 

register is 1, the width can be any size from 1 to 2048 pixels. 

The entire pixels of the video window must be inside the LCD screen. Depending on the 

width of the buffer to be displayed in the video layer and the position, the width should be 

adjusted by software to limit the right edge of the window inside the screen. 

• Video window height (DSS.DISPC_VIDn_SIZE[26:16] VIDSIZEY bit field, with n = 1 or 2): The default 

value at reset time is 0x0 (1 pixel). The window height is from 1 to 2048 pixels. All integer values in the 

range [1:2048] are allowed. The entire pixels of the video window must be inside the LCD screen. 

Depending on the height of the buffer to be displayed in the video layer and the position, the height 

should be adjusted by software to limit the bottom edge of the window inside the screen. 

• Video picture width in system memory (DSS.DISPC_VIDn_PICTURE_SIZE[10:0] VIDORGSIZEX bit 

field, with n = 1 or 2): The default value at reset time is 0x0 (1 pixel). The window width is from 1 to 

2048 pixels. All integer values in the range [1:2048] are allowed with RGB16 and RGB24 video data. 

For YUV2 4:2:2 and UYVY 4:2:2 formats, the width must be a multiple of two pixels. The maximum 

bandwidth efficiency for accessing the pixels in system memory is reached when the width (in bytes) of 

the video picture is a multiple of the video burst size defined in the 

DSS.DISPC_VIDn_ATTRIBUTES[15:14] VIDBURSTSIZE bit field (in bytes). 

• Video picture height in system memory (the DSS.DISPC_VIDn_PICTURE_SIZE[26:16] VIDORGSIZEY 

bit field, with n = 1 or 2): The default value at reset time is 0x0 (1 pixel). The window width is from 1 to 

2048 pixels. All integer values in the range [1:2048] are allowed. 

• Video Priority (DSS.DISPC_VIDn_ATTRIBUTES[23] VIDARBITRATION): The default value at reset 

time is 0x0. It is used to change between normal priority (value of 0) to high priority (value of 1) to 

change priority for the video channel vs. other channels. It can be used to give higher priority to the 

pipelines with real time constraint vs. non real time pipelines. For that is, pipelines associated to the 

LCD output in RFBI mode should have lower priority than pipelines associated to TV output. 

• Video Self-Refresh (DSS.DISPC_VIDn_ATTRIBUTES[24] VIDSELFREFRESH): The default value at 

reset time is 0x0. It is used to use the DMA FIFO without accessing the interconnect for multiple 

frames. Once, the data have been loaded to the DMA FIFO for displaying the frame, they are used for 


The sequence to activate the self-refresh is the following: 

– Frame t: The bit field should be set at anytime during frame 

– Frame t+1: Fetch of the data in the DMA FIFO and display of the frame 

– Frame t+2: No access to the L3 interconnect, DMA FIFO uses to provide the pixels 

The sequence to deactivate the self-refresh is the following: 

– Frame t: No access to the L3 interconnect, DMA FIFO uses to provide the pixels, bit field can be 

changed at any time during the frame 

– Frame t+1: Fetch of the data from system memory using the L3 interconnect 



1699

VIDFIRVINC[12:0] 1024 x 

VIDORGSIZEY[10:0] 

VIDSIZEY[10:0] 

 

 

 

 

 

dss-E093 

VIDORGSIZEX[10:0] 

VIDFIRHINC[12:0] 1024 x 

VIDSIZEX[10:0] 



7.5.3.3.4 Video Up-/Down-Sampling Configuration 

The video horizontal up/downsampling block for video pipeline n (with n = 1 or 2) is enabled/disabled by 

setting/resetting the DSS.DISPC_VIDn_ATTRIBUTES[5] VIDRESIZEENABLE bit. 

The video vertical up/downsampling block for video pipeline n is enabled/disabled by setting/resetting the 

DSS.DISPC_VIDn_ATTRIBUTES[6] VIDRESIZEENABLE bit. 

Set a valid configuration before enabling the video up/downsampling block. 

NOTE: Vertical and horizontal downsampling are limited to a 1/4 resize factor. 

After a register change, either the DSS.DISPC_CONTROL[6] GODIGITAL or DSS.DISPC_CONTROL[5] 

GOLCD bit must be set. The software must wait until the hardware resets this bit before setting it. The 

software reset is not recommended because the application cannot ensure that the bit is reset before the 

hardware reset. 

The following fields define the configuration of the video up/downsampling block for video pipeline n: 

• Vertical up/downsampling increment value (DSS.DISPC_VIDn_FIR[27:16] VIDFIRVINC bit field, with n 

= 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the 

following equation: 

NOTE: 

• If the VIDFIRVINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If 

VIDSIZEY[10:0] equals 0x1, VIDSIZEY[10:0] is replaced by 0x2 in the previous 

equation. 

• The VIDORGSIZEY[10:0] and VIDSIZEY[10:0] bit field values must be programmed with 

the value desired minus 1. 

• Horizontal up/downsampling increment value (DSS.DISPC_VIDn_FIR[11:0] VIDFIRHINC bit field, with 

n = 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the 


NOTE: 

 

 

 

dss-E094 

• If the VIDFIRHINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If 

VIDSIZEX[10:0] equals 1, VIDSIZEX[10:0] is replaced by 2 in the previous equation. 

• The VIDORGSIZEX[10:0] and VIDSIZEX[10:0] bit field values must be programmed with 


• Vertical up/downsampling accumulator value (DSS.DISPC_VIDn_ACCUl[25:16] VIDVERTICALACCU 

bit field): The unsigned integer value range is [0:1023]. The accumulator value indicates in which 

phase the vertical filtering starts. The value 0 indicates that 0 is the first phase used by the hardware to 

generate the first data (see Table 7-50). 

• Vertical up/downsampling line buffer configuration (DSS.DISPC_VIDn_ATTRIBUTES[22] 

VIDLINEBUFFERSPLIT bit): The default value at reset time is 0x0 (line buffers are not split). The 

backward compatibility is maintained versus OMAP2420 and OMAP2430 devices. When the bit field is 

set, each line buffer is split into two line buffers to be able to use six line buffers instead of three. 


VIDVERTICALTAPS bit): The default value at reset time is 0x0 (3-tap configuration is used). If the bit 

field is reset, the 3-tap configuration is used. The backward compatibility is maintained versus 

OMAP2420 and OMAP2430 devices. When the bit field is set, the 5-tap configuration is used and the 

DSS.DISPC_VIDn_ATTRIBUTES[22] VIDLINEBUFFERSPLIT bit must be set to 1. 



(10) 

(11)




VIDDMAOPTIMIZATION bit): The default value at reset time is 0x0 (no optimization). If the bit is set, 

the DMA engine fetches two pixels for each 32-bit OCP request (RGB16 and YUV4:2:2) while doing 

90- and 270-degree rotation. If the bit is clear, the DMA engine fetches one pixel for each 32-bit OCP 

request (RGB16 and YUV4:2:2) while doing 90- and 270-degree rotation. The width and height of 

picture should be even to use the optimization. Even width is required for the input picture when the 

5-tap configuration is used. 


picture must be a multiple of 2 pixels and more than 5 pixels. This leads to the following 

register configuration: 



For more information about the configuration of video DMA optimization, see Section 7.5.3.4.5, Video 

DMA Optimization. 

• Horizontal up/downsampling accumulator value (DSS.DISPC_VIDn_ACCUl[9:0] 

VIDHORIZONTALACCU bit field): The unsigned integer value range is [0:1023]. The accumulator 

value indicates in which phase the horizontal filtering starts. The value 0 indicates that 0 is the first 

phase used by the hardware to generate the first data (see Table 7-50). 

Table 7-50. Vertical/Horizontal Accumulator Phase 

Accumulator Value Phases f 

0 0 

128 1 

256 2 

384 3 

512 4 

640 5 

768 6 

896 7 

• Vertical up/downsampling coefficients (DSS.DISPC_VIDn_FIR_COEF_HVi registers, with n = 1 or 2, 

i = 0 to 7): The 3-tap vertical up/downsampling coefficients are defined in these registers. There are 

eight registers for the eight phases with three coefficients for each, or a total of 24 programmable 

coefficients for the vertical up/downsampling block. Each register contains two 8-bit signed coefficients 

and one 8-bit unsigned coefficient (the central one). 

In addition, there are 2-tap vertical up/downsampling coefficients defined in 

DSS.DISPC_VIDn_FIR_COEF_Vi registers. There are 8 registers for the 8 phases with 2 coefficients 

for each of them so a total of 16 programmable coefficients for the vertical up/downsampling block 

used in addition of the 3-tap registers defined above. Each register contains two 8-bit signed 

coefficients. In case of 5-tap configuration, both sets of registers DSS.DISPC_VIDn_FIR_COEF_HVi 

and DSS.DISPC_VIDn_FIR_COEF_Vi are used. In case of 3-tap configuration, only one set of 

registers DSS.DISPC_VIDn_FIR_COEF_HVi is used. 

• Horizontal up/downsampling coefficients (DSS.DISPC_VIDn_FIR_COEF_Hi and 

DISPC_VIDn_FIR_COEF_HVi registers, with n = 1 or 2, i = 0 to 7): The 

DSS.DISPC_VIDn_FIR_COEF_Hi register and the DSS.DISPC_VIDn_FIR_COEF_HVi register define 

the 5-tap horizontal up/downsampling coefficients. There are eight registers for the eight phases with 

five coefficients for each register, or a total of 40 programmable coefficients for the horizontal 

up/downsampling block. 

Each DSS.DISPC_VIDn_FIR_COEF_Hi register contains three 8-bit signed coefficients and one 8-bit 

unsigned coefficient (the central one). Each DSS.DISPC_VIDn_FIR_COEF_HVi register contains one 

8-bit signed coefficient. 

The programmable coefficient for the FIR up/downsampling method must be adjusted based on 

application needs. For more details on scaling programming settings, see Section 7.6.1. 



1701

R 

G 

B 

= 

1 

256 * 

RY 

GY 

BY 

RCr 

GCr 

BCr 

RCb 

GCb 

BCb 



7.5.3.3.5 Video Color Space Conversion Configuration 

The DSS.DISPC_VIDn_CONV_COEFi registers (with i = 0 to 4) has nine 11-bit coefficients defined for the 

programmable color space conversion block for video pipeline n (with n = 1 or 2). 

The standard register coefficients are: 

YCbCr-to-RGB Registers (VidFullRange=0) 

YCbCr to RGB Registers (VidFullRange=1) 

* 

Y 

dssE095 

Cr - 128 

Cb - 128 

Table 7-51 lists the color space conversion register values. 

dss-E096 

Table 7-51. Color Space Conversion Register Values 

Coefficients BT.601-5 BT.601-5 BT.709 BT.709 Range 

Range [0:255] [0:255] 

RY 298 256 298 256 

RCr 409 351 459 394 

RCb 0 0 0 0 

GY 298 256 298 256 

GCr –208 –179 –137 –118 

GCb –100 –86 –55 –47 

BY 298 256 298 256 

BCr 0 0 0 0 

BCb 517 443 541 465 

VidFullRange 0 1 0 1 

7.5.3.4 Rotation/Mirroring Display Subsystem Settings 

This section describes rotation/mirroring settings. The device provides flexible mechanisms for an efficient 

implementation of rotation using the display-subsystem, its DMA engine, and the rotation engine of the 

SMS module. Depending on whether the image data is located in on-chip SRAM or external SDRAM, 

either a DMA rotation or a VRFB rotation is used. When configuring the rotation, the image data format 

(RGB or YUV) must also be taken into account. The video pipelines also perform the interpolation of YUV 

image data and the color conversion from YUV into RGB format for displaying the images on an LCD 

screen. 

7.5.3.4.1 Image Data Formats 

To understand the programming of the rotation mechanisms described underneath, the supported 

representations of the image data in memory must also be considered. Differences exist between the 

supported formats on the graphics and video pipelines. The graphics pipeline supports RGB and RGB 

with a color look-up table (CLUT), whereas the video pipelines support two versions of YUV 4:2:2 and 

RGB16. In the case of YUV, the interpolation and color conversion hardware in the video pipelines 

converts the image data to the RGB format suitable for the LCD screen. 



(12) 

(13)

Row Increment 

= (iw * (ih - 1) * ps) + 1 

2 

Pixel Increment 

= -iw * ps - (ps -1) 

Buffer Base 

Address (ba) 

3 

Memory 



The graphics pipeline supports: 

• 1-, 2- ,4-, and 8-bits-per-pixel color look-up table 

• 12-, 16-, and 24-bits-per-pixel RGB 

The video pipelines support the following data formats (always 2 bytes/pixel): 

• RGB16 

• YUV2 

• UYVY 

For more information on the graphics data formats, please refer to Section 7.4.2.2, Graphics Pipeline. 

For more information on the video data formats, please refer to Section 7.4.2.3, Video Pipeline. 

In the video pipeline, the YUV 4:2:2 format is converted into a full YUV 4:4:4 format by interpolation of the 

chrominance values from neighboring pixels. After this interpolation is completed, the conversion to the 

RGB format (suitable for displaying the image on the LCD screen) is performed. 

For more information on YUV 4:2:2 to RGB conversion, please refer to Section 7.4.2.3.2, Color Space 

Conversion. 

7.5.3.4.2 Image Data from On-Chip SRAM 

For image data located in the on-chip SRAM, the DSS DMA is used to perform 90-degree, 180-degree, 

and 270-degree rotation. This is done by using the double-indexed addressing mode of the DMA. This 

addressing mode allows a pixel and a row increment to be specified. These address increments are used 

after each pixel or each row (line), respectively. Figure 7-120 illustrates the principle steps for a 90-degree 

rotation. 

Figure 7-120. 90° DMA Rotation Example 

1 

iw 

Readout Start Address for 90° Rotation 

= ba + (iw * (ih -1) * ps) 

ih 

Pixel output Direction 

LCD Screen 

Table 7-52. 90-degree DMA Rotation Example Description 

Parameter Description Additional parameters for formulas 

ba Buffer Base Address in Memory 

IW Image Width in pixels iw = IW-1 

IH Image Height in pixels ih = IH-1 

ps Pixel Size (in bytes) 



ih 

iw 

dss-097 

1703



Figure 7-120 shows how the image is stored in memory and how it is read out to achieve a 90-degree 

rotated orientation. The first pixel for the 0-degree orientation is located at the buffer base address (ba). If 

the image is to be shown on an LCD screen with a 90-degree rotation, the readout starts at the 90-degree 

base address (1). To proceed from one pixel to the next in the same line in the rotated orientation, the 

pixel increment (2) must be applied. At the end of each line of the rotated view, the row increment (3) is 

the offset to advance to the beginning of the next line in the memory buffer. 

Hence, by setting the three DMA parameters (base address, pixel increment, and row increment), a 

90-degree rotation can be achieved, as can 180-degree and 270-degree rotation. Each of the parameters 

can also be combined with an optional mirroring on the vertical axis. 

Following there is a description the setup required to perform the rotation via the DSS DMA. This rotation 

mechanism is used when the image data is stored in internal SRAM. 

7.5.3.4.2.1 Rotation/Mirroring Registers 

To set up the rotation and/or mirroring, the following registers must be programmed: 

• Graphics pipeline (GFX): 

– DSS.DISPC_GFX_BAj 

– DSS.DISPC_GFX_PIXEL_INC 

– DSS.DISPC_GFX_ROW_INC 

– DSS.DISPC_GFX_ATTRIBUTES 

– DSS.DISPC_GFX_POSITION 

– DSS.DISPC_GFX_SIZE 

– DSS.DISPC_GFX_FIFO_THRESHOLD 

• Video pipelines (VID) 1 and 2: 

– DSS.DISPC_VIDn_BAj 

– DSS.DISPC_VIDn_PIXEL_INC 

– DSS.DISPC_VIDn_ROW_INC 

– DSS.DISPC_VIDn_ATTRIBUTES 

– DSS.DISPC_VIDn_POSITION 

– DSS.DISPC_VIDn_SIZE 

– DSS.DISPC_VIDn_CONV_COEF0 to DSS.DISPC_VIDn_CONV_COEF4 

– DSS.DISPC_VIDn_FIFO_THRESHOLD 

• DSS.DISPC_xxx_BAj: These registers contain the base address of the image data at which the DSS 

DMA transfer of the image starts. The register values depend on the rotation chosen (see Table 7-53 

for the formulas). When using the LCD interface, the registers DISPC_xxx_BA0 are used. The 

registers DISPC_xxx_BA1 are only used for the TV output. 

• DSS.DISPC_xxx_PIXEL_INC[15:0]: This bit field contains the DMA addressing increment after each 

pixel. This bit field is used to perform the DSS DMA rotation (see Table 7-53 for the formula). 

NOTE: When the RGB24 packet format is selected, the only valid value is 1. 

• DSS.DISPC_xxx_ROW_INC[31:0]: This bit field contains the DMA addressing increment after each 

row (line) of pixels. This bit field is used to perform the DSS DMA rotation (see Table 7-53 for the 

formula). 

NOTE: When the RGB24 packet format is selected, the valid values are 1 and any value multiples 

of 12 bytes (4x32 bit). When the value is a multiple of 12 bytes, the width must be a multiple 

of 12 bytes. When the value is 1, the width can be any size from 1 to 2048 pixels. 

• DSS.DISPC_xxx_ATTRIBUTES: These registers contain the main settings for the pipeline, such as the 

image data format, the rotation value, and the enable bit for the pipeline. The bit fields of these 

registers play a role in the rotation and in the image data format setup. 

– The following bit fields are used by the graphics pipeline to set up the image format: 

• GFXENABLE: Set this field to activate the hardware path in use. 





• GFXFORMAT: Use this field to specify the format of the graphic frame. 

• GFXROTATION: Set this field to the value corresponding to the rotation angle desired only if the 

frame contains RGB24 pixel data; otherwise, set it to 0x0 regardless of the degree of rotation. 

• GFXREPLICATIONENABLE: Use this bit to determine whether the encoded pixel data in RGB 

formats (RGB12 and RGB16) is extended to 24-bit format with or without replication of the MSB 

to fill the LSBs of each color component. If the replication logic is turned off, the LSB parts are 

filled with 0s. It is recommended to always enable this feature. 

• GFXCHANNELOUT: Set this field based on whether the frame is to be rendered on the LCD or 

on the TV set. 

– The following bit fields for the two video pipelines: 

• VIDENABLE: Set this field to activate the hardware path in use. 

• VIDFORMAT: Use this field to specify the format of the video frame (RGB16 or YUV4:2:2). 

• VIDCOLORCONVENABLE: If the video is in YUV4:2:2 format, set this field to enabled. 

• VIDROTATION: Set this field to the value corresponding to the rotation angle desired only if the 

frame contains non-RGB pixel data; otherwise, set it to 0x0 regardless of the degree of rotation. 

See Section 7.5.3.4.4 for more information. 

• VIDROWREPEATENABLE: Set this field to enabled only if the frame contains YUV pixel data 

and the rotation is 90-degree or 270-degree so that the row pixel data are fetched twice to 

extract both Y components. See Section 7.5.3.4.4 for more information. 

• VIDCHANNELOUT: Set this field based on whether the frame is to be rendered on the LCD or 

on the TV set. 

• DSS.DISPC_xxx_POSITION: Use this register to configure the position of the window. 

• DSS.DISPC_xxx_SIZE: Use this register to configure the size of the window. 

• DSS.DISPC_VIDn_CONV_COEF0, DSS.DISPC_VIDn_CONV_COEF1, 

DSS.DISPC_VIDn_CONV_COEF2, DSS.DISPC_VIDn_CONV_COEF3, and 

DSS.DISPC_VIDn_CONV_COEF4: These registers contain the conversion coefficients required for 

YUV-to-RGB color conversion. 

• DSS.DISPC_xxx_FIFO_THRESHOLD: Set the low threshold 

(DSS.DISPC_GFX_FIFO_THRESHOLD[11:0] GFXFIFOLOWTHRESHOLD) and the high threshold 

(DSS.DISPC_GFX_FIFO_THRESHOLD[27:16] GFXFIFOHIGHTHRESHOLD) values to define the 

FIFO DMA behavior. When the low level is reached, one or more requests are issued to the L3-based 

interconnect to fill up the FIFO to reach the high threshold. The DMA engine then waits until the low 

level is reached to restart the requests. 

7.5.3.4.2.2 DMA Register Settings 

To configure the display controller for rotation and/or mirroring, use the following settings: 



1705

Start 

Set the window size and position: 

DISPC_xxx_SIZE 

DISPC_xxx_POSITION 

If YUV 

Video ? 

No 

Set the new base address value: 

DISPC_xxx_BAi 

Set the row increment value: 

DISPC_xxx_ROW_INC 

Set the pixel increment value: 

DISPC_xxx_PIXEL_INC 

End 



Figure 7-121. Rotation/Mirroring Settings 

Set the FIFO threshold: 

DISPC_xxx_FIFO_THRESHOLD 

Set DISPC_xxx_ATTRIBUTES bitfields 

Yes 

Set YUV-to-RGB conversion coefficients: 

DISPC_VIDn_COEFi 

NOTE: These registers are shadow registers. To take into account the new values, software users 

must set the DSS.DISPC_CONTROL[5] GOLCD bit to 1. 

Table 7-53 details the base address, the row and pixel increment values to access the buffer in memory 

(contiguous pixels) except for the RGB24 packet format. Table 7-54 lists the rotation register settings for 

RGB24 packet format (only for the two video pipelines). 

Table 7-53. DMA Rotation Register Settings 

Rotation Registers GFX/VIDx (1) 

0 degree DSS.DISPC_xxx_BAj ba 

DSS.DISPC_xxx_PIXEL_INC 1 

DSS.DISPC_xxx_ROW_INC 1 

90 degrees DSS.DISPC_xxx_BAj ba + (iw x (ih-1) x ps) 

dss-098 

DSS.DISPC_xxx_PIXEL_INC -(iw x ps) - 1 

DSS.DISPC_xxx_ROW_INC (iw x (ih-1)) x ps + 1 

180 degrees DSS.DISPC_xxx_BAj ba + (iw x ih-1) x ps 

(1) 

DSS.DISPC_xxx_PIXEL_INC -2 x ps 

DSS.DISPC_xxx_ROW_INC -2 x ps 

• ba = start address of image buffer in memory 

• iw = image width in pixels per row - 1 (for YUV: pixels per row divided by 2) 

• ih = image height - 1 (number of rows) 

• ps = pixel size in bytes (RGB: 2 bytes per pixel, YUV: 4 bytes per pixel) 

See Table 7-52 for more information of these parameters. 



Memory 

90° rotation 



Table 7-53. DMA Rotation Register Settings (continued) 


270 degrees DSS.DISPC_xxx_BAj ba + (iw -1) x ps 

DSS.DISPC_xxx_PIXEL_INC (iw -1) x ps + 1 

DSS.DISPC_xxx_ROW_INC -(iw x (ih-1)) x ps - ps + 1 

NOTE: In case of RGB16 format and optimization enabled, the base address is aligned on a 32-bit 

boundary and the number of bytes to skip is a multiple of 4 bytes. 

Table 7-54. Video Rotation Register Settings (With RGB24 Packet Format) 

Rotation Registers SDRAM Direct Access (1) 

(with n = 1 or 2) 

0 degree DSS.DISPC_VIDn_BAj ba 

DSS.DISPC_VIDn_PIXEL_INC 1 

DSS.DISPC_VIDn_ROW_INC 1 

180 degrees DSS.DISPC_VIDn_BAj ba+(iw*ih*3)-4 

(1) 

DSS.DISPC_VIDn_PIXEL_INC -7 

DSS.DISPC_VIDn_ROW_INC -7 

• ba = physical base address of the buffer in the system memory (top-left corner of the picture) 

• iw = number of pixels per row - 1 (original picture in system memory) for BITMAP and RGB formats and number of pixels 

per row divided by 2 for YUB422 formats 

• h = number of lines - 1 (original picture in system memory) 

• ps = pixel size in bytes (BITMAP8: 1 byte; RGB16: 2 bytes; YUV4:2:2: 4 bytes) 


The DMA rotation described above can be also combined with an optional mirroring on the vertical axis 

(see Figure 7-122). The only settings that must be changed to achieve this mirroring are the registers 

described above: DISPC_xxx_BAj, DISPC_xxx_PIXEL_INC, and DISPC_xxx_ROW_INC. Table 7-55 

provides the DMA setup formulas for rotation with mirroring to access the buffer in memory (contiguous 

pixels) except for the RGB24 packet format. 

Figure 7-122. 90° Rotation With Mirroring 

Mirroring 

Screen 



dss-100 




Table 7-55. Register Settings for DMA Rotation With Mirroring 


0 degree DSS.DISPC_xxx_BAj ba + (iw-1) x ps 

DSS.DISPC_xxx_PIXEL_INC -2 x ps + 1 

DSS.DISPC_xxx_ROW_INC 2 x (iw-1) x ps + 1 

90 degrees DSS.DISPC_xxx_BAj ba 

DSS.DISPC_xxx_PIXEL_INC (iw-1) x ps 

DSS.DISPC_xxx_ROW_INC (-iw x (ih-1)) x ps 

180 degrees DSS.DISPC_xxx_BAj ba + iw x (ih-1) x ps 


DSS.DISPC_xxx_ROW_INC -2 x iw x ps 

270 degrees DSS.DISPC_xxx_BAj ba + (iw x ih - 1) x ps 

(1) 

DSS.DISPC_xxx_PIXEL_INC (iw -1) x ps + 1 

DSS.DISPC_xxx_ROW_INC - (iw x (ih-1)) x ps - ps + 1 

• ba = start address of image buffer in memory 

• iw = image width in pixels per row - 1 (for YUV: pixels per row divided by 2) 

• ih = image height - 1 (number of rows) 

• ps = pixel size in bytes (RGB: 2 bytes per pixel, YUV: 4 bytes per pixel) 


7.5.3.4.3 Image Data From External SRAM 

The device offers a rotation engine in the SMS called the VRFB. This rotation method must be used for 

maximum efficiency when the image data is located in SDRAM. To use the VRFB rotation, both the SMS 

module and the DSS DMA must be configured. 

In the DSS, the same registers must be set up as described for DMA rotation (see Section 7.5.3.4.2, 

Image Data from On-Chip SRAM). The differences are in the setup of the following registers: 

• DISPC_xxx_ROW_INC: This field contains the DMA addressing increment after each row (line) of 

pixels. This field is used to add the remaining delta at the end of each line, to reach the 2048-pixel line 

size of the VRFB (see Table 7-56 for the formula). 

• DISPC_xxx_PIXEL_INC: This field contains the DMA addressing increment after each pixel. For VRFB 

rotation, this value is set always to 1 (see Table 7-56). 

Table 7-56. VRFB Rotation - DMA Settings 


0 degree DSS.DISPC_xxx_BAj VBA0 


DSS.DISPC_xxx_ROW_INC (2048 - iw) x ps + 1 

90 degrees DSS.DISPC_xxx_BAj VBA90 + offset 


DSS.DISPC_xxx_ROW_INC (2048 - ih) x ps + 1 



DSS.DISPC_xxx_ROW_INC (2048 - iw) x ps + 1 


(1) 


DSS.DISPC_xxx_ROW_INC (2048 - ih) x ps + 1 

• VBAx = virtual address of the chosen VRFB context and orientation 

• iw = image width (width in pixels for RGB, width in pixels divided by 2 for YUV) 

• ih = image height 

• ps = pixel size in bytes (2 bytes per pixel for RGB, 4 bytes per pixel for YUV) 

• Offset = see below 



VBA 0° 

VBA 180° 

Offset 

= 2048*Δih+Δiw Pixels 

= (2048*Δih+Δiw)*ps Bytes 

Δiw 

0° Rotation 90° Rotation 

2048 Pixels 

2048 Pixels 

Δiw 

Δih 



Figure 7-123 provides the offset values that must be added to the virtual base addresses for 90-degree, 

180-degree, and 270-degree rotation. This offset is applicable only when the defined image size in the 

VRFB module is greater than the actual image size, because it must be a multiple of the page width and 

height. In the example discussed above, the image height was set to 256 lines, instead of 240, because 

the page height was 32 lines. This offset must be added to the virtual base addresses, because the VRFB 

module is not aware of the actual image size. Figure 7-123 illustrates why this occurs and how the offset 

is calculated. 

Figure 7-123. Offset for VRFB Rotation 

VBA 90° 

Offset 

= Δih Pixels 

= Δih*ps Bytes 


2048 Pixels 2048 Pixels 

Δih 

VBA 270° 

Offset 

= 2048*Δiw Pixels 

= 2048*Δiw*ps Bytes 

Δiw = Image width delta between the actual image width and the programmed image width because of the 

page width 

Δih = Image height delta between the actual image height and the programmed image height because of 

the page height: 

• Offset 90-degree: Δih pixels = Δih x ps bytes 

• Offset 180-degree: 2048 x Δih+ Δiw pixels = 2048 x Δih x ps+ Δiw x ps bytes 

• Offset 270-degree: 2048 x Δiw pixels = 2048 x Δiw x ps bytes 

In the example given above, the delta in the image height is 256 – 240 = 16 lines (Δih = 16), whereas the 

exact value of the width can be programmed (Δiw = 0). In that case, the resulting offset values are: 

• YUV: 

– Offset 90-degree: 16 x 4 bytes 

– Offset 180-degree: 2048 x 16 x 4 bytes 

– Offset 270-degree: 0 bytes 

• RGB: 

– Offset 90-degree: 16 x 2 bytes 



Δih 

Δih 

Δiw 

Δiw 

dss-099 

1709



– Offset 180-degree: 2048 x 16 x 2 bytes 

– Offset 270-degree: 0 bytes 

As with DMA rotation, mirroring along the vertical axis can be added on top of the rotation when using the 

VRFB. This mirroring is achieved by combining an appropriate VRFB rotation with a readout of the VRFB 

by the DSS DMA, going backwards from the last line to the first line of the rotated image. Table 7-57 

provides the DMA settings for VRFB rotation with mirroring. 

Table 7-57. VRFB Rotation With Mirroring - DMA Settings 


0 degree DSS.DISPC_xxx_BAj VBA180 + 2048 x (ih - 1) x ps + offset 


DSS.DISPC_xxx_ROW_INC -(2048 + iw) x ps + 1 

90 degrees DSS.DISPC_xxx_BAj VBA270 + 2048 x (iw - 1) x ps + offset 


DSS.DISPC_xxx_ROW_INC -(2048 + ih) x ps + 1 

180 degrees DSS.DISPC_xxx_BAj VBA0 + 2048 x (ih - 1) x ps 


DSS.DISPC_xxx_ROW_INC -(2048 + iw) x ps + 1 

270 degrees DSS.DISPC_xxx_BAj VBA90 + 2048 x (iw - 1) x ps + offset 

(1) 


DSS.DISPC_xxx_ROW_INC -(2048 + ih) x ps + 1 

• VBAx = virtual address of the chosen VRFB context and orientation 

• iw = image width (width in pixels for RGB, width in pixels divided by 2 for YUV) 

• ih = image height 

• ps = pixel size in bytes (2 bytes per pixel for RGB, 4 bytes per pixel for YUV) 

• Offset = see below 

Some offsets are required if there is a delta between the programmed image size in the VRFB and the 

actual image size. As shown in Figure 7-124, this applies to 0-degree rotation with mirroring (using VBA 

180-degree), 90-degree rotation with mirroring (VBA 270-degree), and 270-degree rotation with mirroring 

(VBA 90-degree). The offsets are calculated in this manner: 

• Offset 0-degree (mirroring): 2048 x Δih + Δiw pixels = 2048 x Δih x ps + Δiw x ps bytes 

• Offset 90-degree (mirroring): 2048 x Δiw pixels = 2048 x Δiw x ps bytes 

• Offset 270-degree (mirroring): Δih pixels = Δih x ps bytes 



VBA 180° 

VBA 0° 

Δiw 

Offset 

= 2048*Δih+Δiw Pixels 

= (2048*Δih+Δiw)*ps Bytes 


2048 Pixels 

2048 Pixels 


2048 Pixels 2048 Pixels 

Δiw 

Δih 

Δih 

screen 

screen 



Figure 7-124. Offset for VRFB Rotation With Mirroring 

VBA 270° 

Offset 

= 2048*Δiw Pixels 

= 2048*Δiw*ps Bytes 

VBA 90° 

7.5.3.4.4 Additional Configuration When Using YUV Format 

Δih 

Offset 

= Δih Pixels 

= Δih*ps Bytes 

Δih 

Δiw 

Δiw 

screen 

screen 

The rotation flag (DSS.DISPC_VIDn_ATTRIBUTES[13] VIDROTATION bit , with n = 1 or 2) and the 

repeat flag (DSS.DISPC_VIDn_ATTRIBUTES[18] VIDROWREPEATENABLE) indicate the rotation to 

apply to the video-encoded pixels from the SDRAM and SRAM. The 2D addressing mode is used, but 

even when accessing the SDRAM buffer, some post-processing must be performed on the YUV 4:2:2 

data depending on the rotation. These bits are set only when the video format is not RGB; otherwise, the 

bit field is reset to 0. Table 7-58 and Table 7-59 describe the configuration of these registers. 

Table 7-58. Video Rotation Register Settings (YUV Only) 

Rotation Registers (with n = 1 or 2) SDRAM + Rotation 

engine 

0 degree DSS.DISPC_VIDn_ATTRIBUTES[13] VIDROTATION 0x0 

DSS.DISPC_VIDn_ATTRIBUTES[18] VIDROWREPEATENABLE 0x0 

90 degrees DSS.DISPC_VIDn_ATTRIBUTES[13] VIDROTATION 0x1 






dss-101



Table 7-58. Video Rotation Register Settings (YUV Only) (continued) 


engine 



Table 7-59. Video Rotation With Mirroring Register Settings (YUV only) 


engine 









NOTE: For YUV4:2:2 video-encoded pixels, the hardware must always fetch a 32-bit value from the 

system memory to generate a YUV4:4:4 value before YUV-to-RGB conversion. 

• For 90- and 270-degree rotation, the missing chrominance samples for the odd pixels are generated by 

duplicating the chrominance samples of the previous even pixels. 

• For 0- and 180-degree rotation, the missing chrominance samples for the odd pixels are generated by 

averaging the contiguous chrominance samples. 

7.5.3.4.5 Video DMA Optimization 

When a rotation of 90 or 270 degrees is required, the memory traffic can be reduced as described in 

Section 7.4.2.8, Rotation. 

1. Enable DMA optimization for the video pipelines VID1 and VID2 by applying the following settings to 

the DISPC: 

(a) Enable DISPC DMA optimization by setting: 

• DISPC_VIDn_ATTRIBUTES[20] VIDDMAOPTIMIZATION = 1 

• DISPC_VIDn_ATTRIBUTES[18] VIDROWREPEATENABLE = 0 

• DISPC_VIDn_ATTRIBUTES[13:12] VIDROTATION = 0x1 or 0x3 

(b) Configure DISPC for the following format: 

• DISPC_VIDn_ATTRIBUTES[4:1] VIDFORMAT = 0x6, 0xA, or 0xB 

• DISPC_VIDn_ATTRIBUTES[9] VIDCOLORCONVENABLE = 0x1 (only for YUV format) 

(c) Configure DISPC scaler in 5-tap mode by setting: 

• DISPC_VIDn_ATTRIBUTES[21] VIDVERTICALTAPS = 0x1 

• DISPC_VIDn_ATTRIBUTES[6:5] VIDRESIZEENABLE = 0x2 (vertical resize only, minimum 

setting) or 0x3 (vertical + horizontal resize) 

• DISPC_VIDn_ATTRIBUTES[22] VIDLINEBUFFERSPLIT = 0x1 

2. Configure the rotation engine (VRFB) inside the SDRAM memory scheduler (SMS) as follows: 

(a) Set the SMS-VRFB context pixel size to 32 bits by setting: 

• For RGB16 pixel format: 

– Writing context: SMS.SMS_ROT_CONTROLn[1:0] PS = 1 

– Reading context: SMS.SMS_ROT_CONTROLn[1:0] PS = 2 

• For YUV pixel format: 

– Writing and reading context: SMS.SMS_ROT_CONTROLn[1:0] PS = 2 

(b) Set the SMS-VRFB context width to one half of the original width: 





• SMS.SMS_ROT_SIZEn[10:0] IMAGEWIDTH = Picture width in pixels /2 (because 2 pixels are 

present in each 32-bit container) 

For more information about the VRFB module, see Section 10.2.4.1.5, Rotation Engine, in Section 10.2, 

SDRAM Controller (SDRC) Subsystem. 

NOTE: When 5-tap mode is used, the scaling coefficients must be set even, if 1:1 scaling is 

required. 

Matrix color space coefficients must be set for YUV format inside 

DISPC_VIDn_CONV_COEF0 through the DISPC_VIDn_CONV_COEF4 registers. 

The width of the input original picture must be even (for YUV4:2:2 and RGB16 formats). 

The DMA optimization feature must be used only for YUV and RGB16 formats when 90- or 

270-degree rotation is required. In all other configurations, the 

DISPC_VIDn_ATTRIBUTES[20] VIDDMAOPTIMIZATION bit must be kept at reset value 

(0x0). 

7.5.3.5 LCD-Specific Control Registers 

The following registers define the LCD output configuration: 



• DSS.DISPC_DEFAULT_COLOR_m (m=0) 

• DSS.DISPC_TRANS_COLOR_m (m=0) 

• DSS.DISPC_TIMING_H 

• DSS.DISPC_TIMING_V 

• DSS.DISPC_POL_FREQ 

• DSS.DISPC_DIVISOR 

• DSS.DISPC_SIZE_LCD 

• DSS.DISPC_DATA_CYCLEk 

• DSS.DISPC_CPR_COEF_R, DSS.DISPC_CPR_COEF_G, DSS.DISPC_CPR_COEF_B 

Setting/resetting the DSS.DISPC_CONTROL[0] LCDENABLE bit enables/disables the LCD output. A valid 

configuration must be set before enabling the LCD output. 

7.5.3.5.1 LCD Attributes 

The following fields define the attributes of the panel connected to the display controller: 

• Monochrome or color panel (the DSS.DISPC_CONTROL[2]MONOCOLOR bit) 

• Passive Matrix or active Matrix panel (the DSS.DISPC_CONTROL[3] STNTFT bit) 

• Color depth (the DSS.DISPC_CONTROL[9:8] TFTDATALINES bit field) 

• Number of lines per panel (the DSS.DISPC_SIZE_LCD[26:16] LPP bit field) 

• Number of pixels per line (the DSS.DISPC_SIZE_LCD[10:0] PPL bit field) 

• 4- or 8-bit interface for Passive Matrix monochrome panel (the DSS.DISPC_CONTROL[4] M8B bit) 

7.5.3.5.2 LCD Timings 

The following bit fields define the timing generation of HSYNC/VSYNC: 

• Horizontal front porch (the DSS.DISPC_TIMING_H[19:8] HFP bit field) 

• Horizontal back porch (the DSS.DISPC_TIMING_H[31:20] HBP bit field) 

• Horizontal synchronization pulse width (the DSS.DISPC_TIMING_H[7:0] HSW bit field) 

• Vertical front porch (the DSS.DISPC_TIMING_V[19:8] VFP bit field) 

• Vertical back porch (the DSS.DISPC_TIMING_V[31:20] VBP bit field) 

• Vertical synchronization pulse width (the DSS.DISPC_TIMING_V[7:0] VSW bit field) 



1713

VSW[7:0] (IVS=0) 

(line clock cycle unit) 

VS 

HS 

LCD panel 

(0,0) x 

y 

HBP[11:0] 




• On/Off control of HSYNC/VSYNC pixel clock (the DSS.DISPC_POL_FREQ[17] ONOFF bit) 

• Program HSYNC/VSYNC rise or fall (the DSS.DISPC_POL_FREQ[16] RF bit) 

• Invert HSYNC (the DSS.DISPC_POL_FREQ[13] IHS bit) 

• Invert VSYNC (the DSS.DISPC_POL_FREQ[12] IVS bit) 

• HSYNC gated (the DSS.DISPC_CONFIG[6] HSYNCGATED bit) 

• VSYNC gated (the DSS.DISPC_CONFIG[7] VSYNCGATED bit) 

Table 7-60 describes the programming rules for LCD timing. 

Table 7-60. Programming Rules 

No Downsampling Downsampling 

Downsampling H or V H + V 

(HBP + HSW + HFP) * PCD 8 10 20 

Figure 7-125 shows the timing values description in the case of an active matrix display. 

Figure 7-125. Timing Values Description (Active Matrix Display) 

Active region 

PPL[10:0] 

(pixel unit) 

HFP[11:0] 

(pixel clock cycle unit) 

HSW[7:0] (IHS=0) 

(pixel clock cycle unit) 

LPP[10:0] 

(line unit) 

VBP[11:0] 


VFP[11:0] 


The following bit fields define the timing generation of ac-bias (output enable in active matrix mode): 

• Invert output enable (DSS.DISPC_POL_FREQ[15] IEO bit) 

• ac-bias pin frequency (DSS.DISPC_POL_FREQ[7:0] ACB bit field) 

• ac-bias pin transitions per interrupt (DSS.DISPC_POL_FREQ[11:8] ACBI bit field) 

• ac-bias gated (DSS.DISPC_CONFIG[8] ACBIASGATED) 

The following bit fields define the timing generation of the pixel clock: 

• Pixel clock divisor (DSS.DISPC_DIVISOR[7:0] PCD bit field) 

• Invert pixel clock (DSS.DISPC_POL_FREQ[14] IPC bit) 

• Pixel clock gated (DSS.DISPC_CONFIG[5] PIXELCLOCKGATED bit) 

The 8-bit pixel clock divider (the DSS.DISPC_DIVISOR[7:0] PCD bit field) selects the pixel clock 

frequency. This bit field generates a range of pixel clock frequencies from LC/1 to LC/255, where LC is the 

logic clock from the divided functional clock of the display controller by the DSS.DISPC_DIVISOR[23:16] 

LCD bit field. 

The pixel clock is defined by the following equation: 



dss-102



Pixel Clock = (FunctionalClock/LCD[7:0])/PCD[7:0] 

Table 7-61 through Table 7-64 show the pixel clock frequency limitations depending the panel type (active 

or passive matrix) and the mode (color or monochrome). 

Table 7-61. Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Active Matrix Display 

Min PCD Values Horizontal Resampling 

Vertical Off 2 (1) (1) 

Resampling 

Up 2 (1) 

Off Up 1:1 - 1:2 1:2 - 1:3 1:3 - 1:4 

2 (1) 

2 (1) (1) 

2 3 4 

2 3 4 

1:1 - 1:2 3-tap 2 2 4 6 8 

5-tap PCDmin PCDmin PCDmin PCDmin PCDmin 

1:2 - 1:4 PCDmin PCDmin PCDmin PCDmin PCDmin 

(1) The PCD value can be 1 in case all the data and synchronization signals are asserted and deasserted on the rising edge of the 

pixel clock. 

Table 7-62. Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - 

Mono4 


Off Up 1:1 - 1:2 1:2 - 1:3 1:3 - 1:4 

Vertical Off 4 4 8 12 16 

Resampling 

Up 4 4 8 12 16 

1:1 - 1:2 3-tap 8 8 16 24 32 

5-tap 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 

1:2 - 1:4 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 4xPCDmin 


Mono8 


Off Up 1:1 - 1:2 1:2 - 1:3 1:3 - 1:4 


Resampling 

Up 8 8 16 24 32 

1:1 - 1:2 3-tap 16 16 32 48 64 




Color 


Off Up 1:1 - 1:2 1:2 - 1:3 1:3 - 1:4 


Resampling 

Up 3 3 6 9 12 

1:1 - 1:2 3-tap 6 6 12 18 24 



NOTE: In case of RGB24 format, Figure 7-126 is still valid, except the PCDmin values which must 

be multiplied by two. 

The PCDmin for vertical downsampling only is defined by the following equations: 



1715



Figure 7-126. PCDmin Formulas (V Down-Sampling Only) 

DISPC_ 

SIZE _ LCD[ 

10 : 0] 

PLL 

h _ ratio 

DISPC _VIDn 

_ SIZE[ 

10 : 0] 

VIDZSIZEX 

DISPC _VIDn 

_ PICTURE _ SIZE[ 

10 : 0] 

VIDORGSIZEY 

v _ ratio 

DISPC _VIDn 

_ SIZE[ 

10 : 0] 

VIDSIZEY 

v _ ratio 

PCD min 1 v _ ratio 2 

2 

h _ ratio 

v _ ratio v _ ratio 2 

PCD min max( , 

) 2 v _ ratio 4 

2 

h _ ratio 2 

( h _ ratio 1) 

dss-E103 

The PCDmin for horizontal downsampling only is defined by the following formula: 

While downsampling by n, PCDmin = n 

For H+V downsampling, the formula is the following: 

PCDmin = max(PCDmin H only, PCDmin V only) as defined above 

The refresh rate depends on the following parameters: 

• Horizontal front porch (the DSS.DISPC_TIMING_H[19:8] HFP bit field) 

• Horizontal back porch (the DSS.DISPC_TIMING_H[31:20] HBP bit field) 

• Horizontal synchronization pulse width (the DSS.DISPC_TIMING_H[7:0] HSW bit field) 

• Vertical front porch (the DSS.DISPC_TIMING_V[19:8] VFP bit field) 

• Vertical back porch (the DSS.DISPC_TIMING_V[31:20] VBP bit field) 

• Vertical synchronization pulse width (the DSS.DISPC_TIMING_V[7:0] VSW bit field) 

• Number of lines per panel (the DSS.DISPC_SIZE_LCD[26:16] LPP bit field) 

• Number of pixels per line (the DSS.DISPC_SIZE_LCD[10:0] PPL bit field) 

• 4- or 8-bit interface for the passive matrix monochrome panel (the DSS.DISPC_CONTROL[4] M8B bit) 

The following bit fields define the behavior of the internal blocks: 

• Spatial/temporal dithering logic enabled (DSS.DISPC_CONTROL[7] 

SPATIALTEMPORALDITHERENABLE bit) 

• Spatial/temporal dithering logic number of frames (DSS.DISPC_CONTROL[31:30] 

SPATIALTEMPORALDITHERFRAMES bit field). The default value of this bit field at reset time is 0x0, 

which is 1 frame only (spatial processing without temporal dithering). The possible values are 0x0 (one 

frame), 0x1 (two frames), and 0x2 (four frames). The number of frames is initialized before enabling 

the spatial/temporal dithering unit. The software must not change this bit field value while the 

spatial/temporal unit is enabled. 

The following bit field defines the clock gating strategy: 

• In active matrix mode, the pixel clock is always gated or only when valid data are present (the 

DSS.DISPC_CONFIG[0] PIXELGATED bit). 

7.5.3.5.3 LCD Overlay 

The following bit fields define the overlay attributes of the LCD output: 

• Transparency color key (the DSS.DISPC_TRANS_COLOR0i register (i = 0)) 

• Transparency color key enable (the DSS.DISPC_CONFIG[10] TCKLCDENABLE bit) 

• Transparency color key selection between the destination graphics transparency color key and the 

source video transparency color key (the DSS.DISPC_CONFIG[11] TCKLCDSELECTION bit) 

• The default solid background color is defined in the DSS.DISPC_DEFAULT_COLOR_m[23:0] 

DEFAULTCOLOR bit field (i=0). 

• Alpha blender Enable (DSS.DISPC_CONFIG[18] LCDALPHABLENDERENABLE) 

• Global alpha blending values (DSS.DISPC_GLOBAL_ALPHA[23:16] VID2GLOBALALPHA and 

DSS.DISPC_GLOBAL_ALPHA[7:0] GFXGLOBALALPHA). The value 0xFF corresponds to 100% 

opaque and 0 to 100% transparent 





NOTE: The destination graphics transparency color key is available only to the overlay with which 

the graphics pipeline is connected. The software must set the correct configuration of the 

LCD and digital overlays. 

NOTE: When the alpha blender is enabled, the destination transparency color key is not available 

and the source transparency color key applies to the graphics pixels and not the video pixels. 

When all of these fields are set to the appropriate values, set the DSS.DISPC_CONTROL[5] GOLCD bit to 

indicate that all shadow registers of the pipelines connected to the LCD output are latched by the 

hardware (only if the DSS.DISPC_CONTROL[0] LCDENABLE bit is already set to 1). If the LCD output is 

disabled, the new values will be updated when the DSS.DISPC_CONTROL[0] LCDENABLE bit will be set 

to 1. 

7.5.3.5.4 LCD TDM 

The following fields define the multiple cycle output configuration: 

• First cycle (the DSS.DISPC_DATA_CYCLEk (k=0) register) 

• Second cycle (the DSS.DISPC_DATA_CYCLEk (k=1) register) 

• Third cycle (the DSS.DISPC_DATA_CYCLEk (k=2) register) 

• Enable (the DSS.DISPC_CONTROL[20] TDMENABLE bit) 

• Parallel mode (the DSS.DISPC_CONTROL[22:21] TDMPARALLEMODE field) 

• Cycle format (the DSS.DISPC_CONTROL[24:23] TDMCYCLEFORMAT field) 

• Unused bits (the DSS.DISPC_CONTROL[26:25] TDMUNUSEDBITS field) 

When all of these bit fields are set to the appropriate values, set the DSS.DISPC_CONTROL[5] GOLCD 

bit to indicate that all shadow registers of the pipelines connected to the LCD output are latched by the 



to 1. 

7.5.3.5.5 LCD Spatial/Temporal Dithering 

The following bit fields define the LCD spatial/temporal dithering configuration: 

• Number of frames (the DSS.DISPC_CONTROL[31:30] SPATIALTEMPORALDITHERINGFRAMES bit 

field) with: 

– 0x0 Spatial only (default value) 

– 0x1 Spatial + Temporal over two frames 

– 0x2 Spatial + Temporal over four frames 

– 0x3 Reserved 

• Enable (the DSS.DISPC_CONTROL[7] SPATIALTEMPORALDITHERENABLE bit) 

– 0x0 Disabled (default value) 

– 0x1 Enabled 





to 1. 

7.5.3.5.6 LCD Color Phase Rotation 

The following bit fields define the color phase rotation configuration: 

• Enable (the DSS.DISPC_CONFIG[15] CPR bit) 

– 0x0 Disabled (default value) 



1717



– 0x1 Enabled 

• Red 10-bit signed coefficients used by the color phase rotation matrix (the DSS.DISPC_CPR_COEF_R 

register) 

• Green 10-bit signed coefficients used by the color phase rotation matrix (the 

DSS.DISPC_CPR_COEF_G register) 

• Blue 10-bit signed coefficients used by the color phase rotation matrix (the 

DSS.DISPC_CPR_COEF_B register) 

The programmable color phase rotation block for the LCD output has nine 10-bit coefficients defined in the 

DSS.DISPC_CPR_COEF_R, DSS.DISPC_CPR_COEF_G, and DSS.DISPC_CPR_COEF_B, as 

described in Figure 7-127 through Figure 7-130. 

Figure 7-127. Color Phase Rotation Matrix 

Rout 

RR 

1 

 

 

 

Gout 

 

* 

 

GR 

256 

 

 

Bout 

 

 

BR 

RG 

GG 

BG 

RB 

Rin 

 

 

 

GB 

 

 

* 

 

Gin 

 

 

BB 

 

 

Bin 

 

dss-E105 

Figure 7-128. Color Phase Rotation Matrix (R Component Only) 

1 

Riout * ( RR* 

Rin RG * Gin RB* 

Bin) 

256 

dss-E106 

Figure 7-129. Color Phase Rotation Matrix (G Component Only) 

1 

Gout * ( GR * Rin GG * Gin GB * Bin) 

256 

dss-E107 

Figure 7-130. Color Phase Rotation Matrix (B Component Only) 

1 

Bout * ( BR* 

Rin BG * Gin BB* 

Bin) 

256 





to 1. 

7.5.3.5.6.1 Color Phase Rotation - Diagonal Matrix 

The Color Phase Rotation feature is useful when using an LCD backlight that is not white. By using a 

correct configuration of the R, G and B coefficients of CPR, the color bias of the screen can be corrected. 

The following paragraphs give an example of configuration of the CPR feature. 

The easiest example of CPR configuration is a diagonal matrix. This way, the output colors depends on 

one input color only. Figure 7-131 gives the example of a diagonal matrix and the corresponding equation 

of the output components. 


dss-E104 


Rout 

RR 

1 

 

 

 

Gout 

 

* 

 

0 

256 

 

 

Bout 

 

 

0 

Rout = 

Gout = 

Bout = 

Rout 

256 

1 

 

 

 

Gout 

 

* 

 

0 

256 

 

 

Bout 

 

 

0 

Rout = 

Gout = 

Bout = 



Figure 7-131. Diagonal Matrix Configuration 

0 

GG 

0 

1 

* 

RR * Rin 

256 

1 

* 

GG * Gin 

256 

1 

* 

BB * Bin 

256 

0 

256 

0 

1 

* 

256 * Rin 

256 

1 

* 

256 * Gin 

256 

1 

* 

128 * Bin 

256 

0 Rin 

 

 

 

0 

 

 

* 

 

Gin 

 

 

BB 

 

 

Bin 

 

According to these 3 new equations, each output component only depends on the corresponding input 

color. The coefficients can easily be used to reduce the impact of a non-white backlight. 

Let's take the example of a "blue" backlight. In this case, users have the feeling that a blue film has been 

added on the screen, and then each color seems to be "too much blue". The goal is then to reduce the 

"Blue" component and to keep the "Red" and "Green" ones unchanged. The following matrix can be used 

for a reduction by a half of the blue component. Figure 7-132 gives the corresponding matrix and 

equations for each component. 

0 Rin 

 

 

 

0 

 

 

* 

 

Gin 

 

 

128 

 

 

Bin 

 

 

 

 

 

 

 

dss-200 

Figure 7-132. Example - Diagonal Matrix Configuration 

=> Rout = Rin 

=> Gout = Gin 

=> Bout = 0.5 * Bin 

Figure 7-133 shows the result of an image on a "blue" backlight screen with and without CPR. 


dss-201 


1719

Initial Figure on LCD (No CPR) 



Figure 7-133. Image With and Without CPR (Diagonal Matrix) 

Initial Figure 

Initial Figure on LCD (With CPR) 

dss-202 

A drawback of this diagonal matric is that the color reduction is linear. The contrast is then different from 

the initial image. It is then necessary to use the 6 other coefficients of the CPR matrix to better correct a 

non-white backlight. The goal is to find the correct coefficients that remove the color offset added by the 

non-white backlight. 

7.5.3.5.6.2 Color Phase Rotation - Standard Matrix 

In the following example, the LCD backlight adds an offset of 128 (B_offset) to the Blue component. 

Figure 7-134 shows an example of matrix that reduces the offset of the screen, the corresponding 

equations and the resulting output colors. 



Rout 

256 

0 0 Rin 

 

1 

 

 

 

 

Gout 

 

* 

 

0 256 0 

 

* 

 

Gin 

 

 

256 

 

 

 

Bout 

 

 

-129 -129 370 

 

Bin 

 

Rout = 

Gout = 

Bout = 

1 

* 

 

256 * Rin 

256 

1 

* 

256 

1 

* 

256 

Resulting pixel on LCD (no CPR correction) 

256 * Gin 

Rout 255 0 0 255 0 128 

Gout 0 255 0 255 0 128 

Bout 128 128 255 255 128 255 



Figure 7-134. Example - Image With and Without CPR (Standard Matrix) 

 

 

 

-129 * Rin + -129 * Gin + 370 * Bin + B_offset 

Initial pixel to send to LCD 

Rin 255 0 0 255 0 128 

Gin 0 255 0 255 0 128 

Bin 0 0 255 255 0 128 

 

 

Resulting pixel on LCD (after CPR correction) 

Rout 255 0 0 255 0 128 

Gout 0 255 0 255 0 128 

Bout 0 0 255 255 128 184 

This CPR matrix gives inputs and outputs very close. However, black cannot be corrected because of it's 

zero-components. No matter which coefficients are used in the matrix, the result will always be equal to 

the offset added by the LCD backlight. 

7.5.3.6 TV Set-Specific Control Registers 

The following registers define the digital output configuration: 



• DSS.DISPC_DEFAULT_COLOR_m (m=1) 

• DSS.DISPC_TRANS_COLOR_m (m=1) 

• DSS.DISPC_SIZE_DIG 

The digital output is enabled/disabled by setting/resetting the DSS.DISPC_CONTROL[1] DIGITALENABLE 

bit. A valid configuration must be set before the digital output can be enabled. 

Perform the initialization sequence as follows: 

1. Initialize the video encoder and the display controller configuration registers. 

2. Set the DSS.DISPC_CONTROL[6] GODIGITAL bit and the DSS.DISPC_CONTROL[1] 

DIGITALENABLE bit to 1. 

3. Wait for the first VSYNC pulse signal. 

4. Clear the SYNCLOSTDIGITAL interrupt by setting the DSS.DISPC_IRQSTATUS[15] 

SYNCLOSTDIGITAL bit to 1. 

5. Enable the SYNCLOSTDIGITAL interrupt by setting the DSS.DISPC_IRQENABLE[15] 




dss-203 

1721



7.5.3.6.1 Digital Timings 

The following bit fields define the timing information: 

• Data hold time (the DSS.DISPC_CONTROL[19:17] HT bit field) 

• Logic clock divisor (the DSS.DISPC_DIVISOR[23:16] LCD bit field) 

The 8-bit pixel clock divider (DSS.DISPC_DIVISOR[23:16]) bit field is used to select the logic clock 

frequency. The LCD generates a range of pixel clock frequencies from FCK/1 to FCK/255, where FCK is 

the input functional clock of the display controller. 

7.5.3.6.2 Digital Frame/Field Size 

The following bit fields define the field size (frame if progressive mode): 

• Number of lines per panel (the DSS.DISPC_SIZE_DIG[26:16] LPP bit field) 

• Number of pixels per line (the DSS.DISPC_SIZE_DIG[10:0] PPL bit field) 

7.5.3.6.3 Digital Overlay 

The following bit fields define the overlay attributes of the digital output: 

• Transparency color key (the DSS.DISPC_TRANS_COLOR_m register (m=1)) 

• Transparency color key enable (the DSS.DISPC_CONFIG[12] TCKDIGENABLE bit) 

• Transparency color key selection between the destination graphics transparency color key and the 

source video transparency color key (the DSS.DISPC_CONFIG[13] TCKDIGSELECTION bit) 

• The default solid background color is defined in the DSS.DISPC_DEFAULT_COLOR_m[23:0] 

DEFAULTCOLOR bit field (i=1). 

• Alpha blender Enable (DSS.DISPC_CONFIG[19] TVALPHABLENDERENABLE) 

• Global alpha blending values (DSS.DISPC_GLOBAL_ALPHA[23:16] VID2GLOBALALPHA and 

DSS.DISPC_GLOBAL_ALPHA[7:0] GFXGLOBALALPHA). The value 0xFF corresponds to 100% 

opaque and 0 to 100% transparent 

NOTE: The destination graphics transparency color key is available only to the overlay with which 

the graphics pipeline is connected. The software must set the correct configuration of the 

LCD and digital overlays. 

NOTE: When the alpha blender is enabled, the destination transparency color key is not available 

and the source transparency color key applies to the graphics pixels and not the video pixels. 

When this bit field is set to the appropriate values, set the DSS.DISPC_CONTROL[6] GODIGITAL bit to 

indicate that all shadow registers of the pipelines connected to the digital output are latched by the 

hardware (only if the DSS.DISPC_CONTROL[1] DIGITALENABLE bit is already set to 1). If the digital 

output is disabled, the new values will be updated when the DSS.DISPC_CONTROL[1] DIGITALENABLE 

bit will be set to 1. 

7.5.4 DSI Protocol Engine Basic Programming Model 

This section describes the programming model of the DSI protocol engine. 

7.5.4.1 Software Reset 

The DSI protocol engine can be reset by software. This reset can be done for debug purposes or after a 

protocol error and has the same effect as the hardware reset. The DSI protocol engine can be reset by 

setting the DSS.DSI_SYSCONFIG[1] SOFT_RESET bit to 1. The software can monitor the 

DSS.DSI_SYSSTATUS[0] RESET_DONE status bit to wait for the completion of the reset procedure. If 

after 5 reads, the DSS.DSI_SYSSTATUS[0] RESET_DONE status bit still returns 0, it can be assumed 

that an error occurred during the reset stage. 





NOTE: This software reset is optional as an hardware reset is always performed on the DSI 

protocol engine at device reset. 


The power management behavior of the DSI protocol engine is controlled by the DSS.DSI_SYSCONFIG 

register. This register completely controls the way the module interferes with the PRCM module. The 

DSS.DSI_SYSCONFIG[0] AUTO_IDLE bit should be set to 1 (default value) to enable automatic clock 

gating in the module. 

7.5.4.3 Interrupts 

There is a single interrupt request: DSI_IRQ. This interrupt line is merged with another interrupt line from 

the DISPC_IRQ in a single interrupt request DSS_IRQ. The DSI_IRQ events are generated only for the 

enabled VC(s). Two registers are used to enable and monitor the DSI interrupt events: 

• DSS.DSI_IRQENABLE register: This register indicates the enabled/disabled event for the VCs. Each 

event for the VC is configured in the DSS.DSI_VCn_IRQENABLE register dedicated to the VC number. 

In addition, it includes one bit for the enable of error reporting for the complex I/O: Error signaling from 

the complex I/O: The interrupt is triggered when any error is received from the complex I/O 

(ErrSyncEsc[4:0], ErrEsc[4:0] (edge trigger interrupt), ErrControl[4:0] and ErrContentionLP0[4:0], 

ErrContentionLP1[4:0] from the complex I/O). 

• DSS.DSI_IRQSTATUS register : The register DSI_IRQSTATUS flags which VC(s) is/have generated 

an interrupt. Based on the VC number, the register DSI_VCn_IRQSTATUS indicates the event 

generating the interrupt. In addition, it includes one bit for the status of error reporting for the complex 

I/O. 

7.5.4.4 Global Register Controls 

Prior to receive data from the DSI complex I/O, the DSI_PHY_SCP registers in the DSI complex I/O must 

be configured. Refer to Section 7.5.6 for more details. Table 7-65 details the register access width 

limitations for all the DSI modules. 

Table 7-65. Register Access Width Limitations 

Register Name Register Access Width 

All DSI complex I/O register 32-bit only 

(DSI_PHY_SCP) 

All DSI PLL control module registers 32-bit only 

DSI_VCn_LONG_PACKET_HEADER 32-bit only 

DSI_VCn_SHORT_PACKET_HEADER 32-bit only 

DSI_VCn_LONG_PACKET_PAYLOAD 16-bit, 32-bit 

All others DSI protocol engine registers 8-bit, 16-bit and 32-bit 

CAUTION 

In case of different access width detailed in Table 7-65, an OCP error is 

generated in response to the write using SResp=ERR. 

The DSI protocol engine is globally controlled by the DSS.DSI_CTRL register. The interface to the 

complex I/O is enabled by setting the DSS.DSI_CTRL[0] IF_EN bit. When the interface is disabled, it is 

possible to provide data to the TX FIFO and read pending data in the RX FIFO. When the 

DSS.DSI_CTRL[0] IF_EN bit is set to 1, the pending packets should be sent to the DSI complex I/O, the 

data transfer from the video port should be ignored only when received the next Vertical Sync Event which 

is received but not send to the DSI complex I/O. 



1723



When the DSS.DSI_CTRL[0] IF_EN bit is reset by software, the hardware should finish the transfer of the 

pending data in the TX FIFO and wait for response if BTA has been sent (Protocol engine is receive 

mode), then the hardware resets the DSS.DSI_CTRL[0] IF_EN bit. When using the video mode, the VC 

associated with the video port should be enabled prior to enable the interface according to the following 

sequence: 

• DSS.DSI_CTRL[0] IF_EN bit is equal to 0 

• Enable the VC associated with video mode by setting the DSS.DSI_VCn_CTRL[0] VC_EN 

• Set the DSS.DSI_CTRL[0] IF_EN bit to 1 

7.5.4.5 Virtual Channels 

There is one set of registers for each VC. The attributes of the VC define the following characteristics: 

• Transfer mode (DSS.DSI_VCn_CTRL[4] MODE bit): 

– Video mode 

– Command mode 

• Data type 

• Source (DSS.DSI_VCn_CTRL[1] SOURCE bit) 

– Video port 

– L4 interconnect port 

• HS or LP forward transmission 

• Automatic bus turn-around generation 

– Short packets (DSS.DSI_VCn_CTRL[2] BTA_SHORT_EN bit) 

– Long packets (DSS.DSI_VCn_CTRL[3] BTA_LONG_EN bit) 

• DMA request configurations for RX and TX 

– DMA request number (DSS.DSI_VCn_CTRL[29:27] DMA_RX_REQ_NB bit field for RX FIFO and 

DSS.DSI_VCn_CTRL[23:21] DMA_TX_REQ_NB bit field for TX FIFO) 

– DMA threshold (DSS.DSI_VCn_CTRL[26:24] DMA_RX_THRESHOLD bit field for RX FIFO and 

DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD bit field for TX FIFO) 

• Mode speed (DSS.DSI_VCn_CTRL[9] MODE_SPEED bit) 

• ECC transmission (DSS.DSI_VCn_CTRL[8] ECC_TX_EN bit) 

• CS transmission (DSS.DSI_VCn_CTRL[7] CS_TX_EN bit) 

The VC ID not calculated by the DSI module but provided while writing into the registers 

DSI_VCn_SHORT_PACKET_HEADER and DSI_VCn_LONG_PACKET_HEADER. 

7.5.4.6 Packets 

The DSS.DSI_VCn_SHORT_PACKET_HEADER register is used to send only short packets (ECC can be 

calculated by hardware or by software user for debug purpose). The register is not used for video mode 

data since the short packets are generated by the hardware using the following information: 

• synchronization events received on the video port (assertion/deassertion of the HSYNC and VSYNC 

input signals) 

• DSS.DSI_CTRL[18] VP_HSYNC_END 

• DSS.DSI_CTRL[17] VP_HSYNC_START 

• DSS.DSI_CTRL[16] VP_VSYNC_END 

• DSS.DSI_CTRL[15] VP_VSYNC_START 

• DSS.DSI_CTRL[10] VP_HSYNC_POL 

• DSS.DSI_CTRL[11] VP_VSYNC_POL 

• DSS.DSI_VCn_CTRL[1] SOURCE 

The DSS.DSI_VCn_LONG_PACKET_HEADER register is used to provide header for long packets (ECC 

is always calculated by hardware). The register is used for video mode and command mode. If the video 

mode is enabled for the VC, it is not possible to transfer concurrently (interleaved in a frame) data using 





long packets received on the video port and on the L4 interconnect port since the 

DSS.DSI_VCn_LONG_PACKET_HEADER register is used by the video mode. The register can be 

unprogrammed by users to send long packets received on the L4 interconnect port only when software 

users know that there is no expected data on the video port. The software should correctly program the 

register to send sequentially long packets in video and command modes. 

The DSS.DSI_VCn_LONG_PACKET_PAYLOAD register is used to provide payload data for long packets 

(Check-sum is calculated by hardware when DSS.DSI_VCn_CTRL[7] CS_TX_EN is set to 1 otherwise the 

value 0x00 is used). The register is not used in video mode since payload data are provided by the video 

port. The software should ensure that the following sequence for write accesses to the header and 

payload registers (DSS.DSI_VCn_LONG_PACKET_HEADER and 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD, respectively) is followed: 

• A long packet header value with WC=0 written in DSS.DSI_VCn_LONG_PACKET_HEADER register 

can be followed by any access. 

• A long packet header value with WC0 written in DSS.DSI_VCn_LONG_PACKET_HEADER register 

should be followed by one or more writes to the DSS.DSI_VCn_LONG_PACKET_PAYLOAD register 

defined by the WC value before writing again to the same DSS.DSI_VCn_LONG_PACKET_HEADER 

register. 

7.5.4.7 DSI Complex I/O 

CAUTION 

If this sequence is not followed, no error is generated. The access to other DSI 

registers during this sequence is allowed. 

Prior to send/receive any data from the complex I/O, the DSI complex I/O timings should be set according 

to the display module timings. The DSI complex I/O pads must also be configured first. See Section 7.5.6, 

DSI Complex I/O Basic Programming Model. 

7.5.4.8 Video Mode 

The DSS.DSI_VM_TIMING1, DSS.DSI_VM_TIMING2, DSS.DSI_VM_TIMING3, DSS.DSI_VM_TIMING4, 

DSS.DSI_VM_TIMING5, DSS.DSI_VM_TIMING6, and DSS.DSI_VM_TIMING7 registers define the 

timings of the video mode. 

The DSS.DSI_CTRL[20] BLANKING_MODE bit defines if the long blanking packets or LPS state are used 

during the blanking periods (except HFP, HBP, HSA defined by other bits) when there is no pending data 

in TX FIFO ready to be sent. The software should ensure that there is no data in the TX FIFO, no BTA, no 

RESET trigger sent, and the DSS.DSI_VCn_CTRL[9] MODE_SPEED bit is set to 1 (High-Speed mode) to 

keep the video mode transfer is HS mode during blanking periods (except for the last blanking period 

since it is required to go LPS at least once per frame). 

The DSS.DSI_CTRL[21] HFP_BLANKING_MODE, DSS.DSI_CTRL[22] HBP_BLANKING_MODE and 

DSS.DSI_CTRL[23] HSA_BLANKING_MODE define if these blanking can send packets from the TX FIFO 

or should be kept in HS mode using only long blanking packets. 

To ensure that the writes to the register DSS.DSI_VCn_LONG_PACKET_HEADER are correctly handled 

as header information for video mode long packets, the following registers should be programmed: 

• DSS.DSI_VCn_CTRL[0] VC_EN bit set to 1 

• DSS.DSI_VCn_CTRL[4] MODE bit set to 1 

• DSS.DSI_VCn_LONG_PACKET_HEADER register access 

• DSS.DSI_VCn_CTRL[0] VC_EN bit set to 1 

NOTE: The DSS.DSI_VCn_CTRL[1] SOURCE and DSS.DSI_VCn_CTRL[9] MODE_SPEED bits 

are ignored by hardware when the video mode is selected (DSS.DSI_VCn_CTRL[4] MODE 

bit set to 1) 

The interrupt events SYNC_LOST_IRQ and RESYNCHRONIZATION_IRQ indicates if the DSI protocol 



1725



engine has not been able to resynchronize the video port timing to its own timing base or if it has been 

done. The RESYNCHRONIZATION_IRQ indicates software users that the video port works but the 

configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to 

be modified to avoid the resynchronization to occur. The SYNC_LOST_IRQ and 

RESYNCHRONIZATION_IRQ events can be respectively monitored in DSS.DSI_IRQSTATUS[18] 

SYNC_LOST_IRQ and DSS.DSI_IRQSTATUS[5] RESYNCHRONIZATION_IRQ status bits. 

The DSS.DSI_VM_TIMING2[27:24] WINDOW_SYNC bit field defines the synchronization period. The 

recommended value is 0x4 based on the implementation of the resynchronization scheme. 

7.5.4.9 Video Port Data Bus 

The DSS.DSI_CTRL[7:6] VP_DATA_BUS_WIDTH bit field is used to determine the width of the data bus 

on the video port. The supported formats are 16-bit, 18-bit and 24-bits. 

7.5.4.10 Command Mode 

7.5.4.10.1 Command Mode TX FIFO 

The single TX FIFO is used on the L4 interconnect port to receive the data to be sent to the peripheral. 

The configuration of the FIFO for a specific VC should be done only when the VC is disabled. 

Users should not enable the VC if there is still some pending data in the TX FIFO for the corresponding 

space allocated for the VC from previous active period. When the VC space in the TX FIFO is empty, the 

VC can be enabled. 

For each VC, two dedicated DSS.DSI_VCn_LONG_PACKET_HEADER and 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD registers are used to provide data for long packets. The 

register DSS.DSI_VCn_SHORT_PACKET_HEADER is used to provide data for short packets (32-bit 

long). 

For each long packet, the DSS.DSI_VCn_LONG_PACKET_HEADER register should be written first and 

then the DSS.DSI_VCn_LONG_PACKET_PAYLOAD register. The only exception is when the word count 

defined in the header is equal to 0. In that case, it is not required to write into the payload register. For 

consecutive long packets, the header should be written into the 

DSS.DSI_VCn_LONG_PACKET_HEADER register even if the value remains the same. 

The TX FIFO stores all the pending bytes to be sent to the peripheral(s). Multiple receivers can be 

addressed using the VC capability. 

The 32-bit write requests only for each VC to the TX FIFO should be kept in order while sending the data 

to the DSI_PHY inside the VC requests. The only exception is in the case of last 32-bit write for the last 

bytes of the payload data since it could be 1, 2, 3, or 4 bytes. 

Also in case the last transfer is a 32-bit write but the number of valid bytes is 1, 2, or 3 only (calculated 

using the header word count and the number of bytes are received for the payload), the hardware should 

store the 32-bit value into the TX FIFO but the invalid bytes are not sent, and are discarded. 

When the word count defined in DSS.DSI_VCn_LONG_PACKET_HEADER register is not a multiple of 

the request threshold value defined in DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD bit field, 

32-bit requests and/or bytes should be discarded by the hardware to store in FIFO only the exact number 

of valid bytes. 

The DSI protocol module should be able to determine if the bytes in the TX FIFO correspond to a short or 

long packet without decoder the DT field. When the bytes are written into the 

DSS.DSI_VCn_SHORT_PACKET_HEADER, DSS.DSI_VCn_LONG_PACKET_HEADER, and 

DSS.DSI_VCn_LONG_PACKET_PAYLOAD registers, the hardware should store the information 

concerning long or short packet. A 1-bit flag should be used for each entry of the TX FIFO. 

When the VC is disabled, the remaining bytes in the FIFO should be sent to the DSI link. The start event 

to send data to the DSI link one of the following events: 

• All bytes have been received in the FIFO (header + payload). 

• The space of the FIFO allocated for the VC is full. 

• The space of the FIFO allocated for the VC is not enough to request more data using DMA request 





(threshold value bigger than space left in the TX FIFO for the VC). 

NOTE: In case the video mode is active, the blanking period should be large enough to allow the 

transfer of the packet(s). 

Sequential arbitration must be set (TX_FIFO_ARBITRATION[3] DSI_CTRL bit = 0x1) if only 

one VC is used to send multiple packets during the same blanking period. 

When consecutive packets should be sent in HS mode, to ensure that there is no LP transition between 

them at least one of the following condition should be valid: 

• Packets from the same VC 

• Short packets or long packets with a payload size multiple of 4 bytes 

To flush the FIFO (discard of the data) for some pending bytes, the software should change the allocated 

size of the chuck FIFO by: 

• First disabling the VC resetting DSS.DSI_VCn_CTRL[0] VC_EN bit to 0 

• Second change the size of the space of FIFO to 0 by writing the DSS.DSI_TX_FIFO_VC_SIZE 

VCn_FIFO_SIZE (n is the VC value between 0 and 3) 

If there is an on-going packet transfer from the TX FIFO to DSI_PHY, the flush of the FIFO should stop 

immediately the transfer. Because the FIFO is accessible to users, it must ensure that there are no bytes 

left in the FIFO before starting the flush operation. But it can be required in dead-lock situation to flush the 

FIFO even if there are still bytes in the FIFO, in that case, the software should also take care of having a 

known state of the whole DSI protocol engine module (software reset may be required) To start of new 

transfer through the TX FIFO. 

Users can check that there is no pending request before changing the size of the allocated FIFO for the 

VC by reading the relevant DSS.DSI_VCn_CTRL[15] VC_BUSY bit or by using the interrupt 

PACKET_SENT_IRQ: All the packets have been sent by counting the transferred requests to the L4 

interconnect port and the number of requests sent to the DSI complex I/O. This interrupt can be 

monitoring by reading the DSS.DSI_VCn_IRQSTATUS[2] PACKET_SENT_IRQ status bit. 

The DSS.DSI_CTRL[3] TX_FIFO_ARBITRATION bit defines if the arbitration scheme is: 

• Round-robin between enabled VCs with pending ready requests (pending ready request means that all 

bytes for the packets are in the FIFO or the space of the FIFO for the VC is full) starting from the VC 

which has the least VC ID number. 

• Sequential: All the pending ready requests for one VC are sent before moving to another VC. The 

condition of "space of the FIFO is full" should be evaluated after the end of each packet. 

If users want to use sequential arbitration for all requests for all channels, a single VC should be used. 

(the VC ID defined in the header provided to the hardware using either the 

DSS.DSI_VCn_LONG_PACKET_HEADER or DSS.DSI_VCn_SHORT_PACKET_HEADER register is not 

used and not modified by the DSI protocol engine). 

The register DSS.DSI_TX_FIFO_VC_SIZE defines the allocated number of 33-bit values for each VC in 

the TX FIFO and the start address for each VC. The size of the space allocated in the TX FIFO defined by 

DSS.DSI_TX_FIFO_VC_SIZE VCn_FIFO_SIZE (n corresponds to the VC number n) bit fields should be a 

multiple of the threshold defined in DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD bit field. Only the 

enabled VCs should be taken into account. To change the size of the space of the memory allocated for a 

specific VC, the VC should be disabled by setting the DSS.DSI_VCn_CTRL[0] VC_EN bit to 0. The whole 

FIFO may not be used by all the VCs at a given time since a VC can be disabled to change one or 

multiple parameters. Software users are responsible for correctly configuring the start address and the 

size for each VC. 

Table 7-66 indicates the corresponding values for the size of the space allocated in the FIFO. 

Table 7-66. Virtual Channel TX FIFO Size Values 

DSI_TX_FIFO_VC_SIZE.VCn_FIFO_SIZE[n = 0, 3] Space Size (up to the size of the FIFO) 

0 0 x 33 bits 

1 32 x 33 bits 





Table 7-66. Virtual Channel TX FIFO Size Values (continued) 

DSI_TX_FIFO_VC_SIZE.VCn_FIFO_SIZE[n = 0, 3] Space Size (up to the size of the FIFO) 

2 64 x 33 bits 

3 96 x 33 bits 

4 128 x 33 bits 

The total size of TX FIFO is 128*33 bits. Therefore, the sum of all virtual channel FIFO allocation cannot 

exceed 128*33 bits. 

Table 7-67 indicates the start address of the space in the FIFO. 

Table 7-67. Virtual Channel TX FIFO Start Address 

DSI_TX_FIFO_VC_SIZE.VCx_FIFO_ADD[x = 0, 2] Start Address 

0 0 

1 32 

2 64 

3 96 

4 128 

CAUTION 

There must be no overlap of different VCs spaces. 

When the TX FIFO is full: 

• the overflow interrupt (FIFO_TX_OVF_IRQ) is generated. To monitor this interrupt request, users can 

read the DSS.DSI_VCn_IRQSTATUS[3] FIFO_TX_OVF_IRQ status bit. 

• there is no L4 interconnect error generated 

• the commands are accepted but the data are not written into the FIFO 

To ensure that all writes are correctly stored in the TX FIFO, the FIFO should not be full. The software 

must read the room in the space allocated for the VC in the TX FIFO by reading the 

DSS.DSI_TX_FIFO_VC_EMPTINESS register. In case there is no space allocated in the TX FIFO for the 

VC, the DSS.DSI_TX_FIFO_VC_EMPTINESS register indicates a value of 0 for the VC space emptiness. 

When waiting to receive the first VSYNC event on the video port to start the video mode on DSI link no 

command data from TX FIFO should be sent on the interface. It is required to ensure that when receiving 

the VSYNC event, there is no on-going command mode transfer that could delay the start of video mode 

on the DSI link. 

7.5.4.10.2 Command Mode RX FIFO 

The RX FIFO is used to store the data received from the DSI complex I/O. The data are always packed in 

the RX FIFO (single or multiple packets receiving during a single or multiple BTA periods). 

The read requests access to corresponding VC locations to transfer data for a specific VC. The logic 

managing the FIFO must be able to extract 32-bit values in-order for a specific VC upon read requests. 

The byte enable of the read access is ignored. Each read returns one 32-bit value from the RX FIFO. If 

the application accesses the RX FIFO should extract always 32-bit values. Only in the case of 1, 2, or 3 

bytes are remaining in the RX FIFO. 

The read requests (single or burst) can be less, equal or greater than the packet size. If the packet size is 

smaller than the read request, the following packet(s) is also transferred. If the packet size is longer than 

the read request, only part of the packet is transfer. In that case, the logic should keep the VC information 

to provide the rest of the data during the next read request(s). 





The register DSS.DSI_RX_FIFO_VC_SIZE defines the allocated number of 33-bit values for each VC in 

the RX FIFO and the start address for each VC. Only the enabled VCs should be taken into account. to 

change the size of the space of the memory allocated for a specific VC, the VC should be disabled by 

resetting the DSS.DSI_VCn_CTRL[0] VC_EN bit to 0. The whole FIFO may not be used by the entire VC 

at a given time since a VC can be disabled to change one or multiple parameters. Software users are 

responsible for correctly configuring the start address and the size for each VC. 

Table 7-68 indicates the corresponding values for the size of the space allocated in the FIFO: 

Table 7-68. Virtual Channel RX FIFO Size Values 

DSI_RX_FIFO_VC_SIZE.VCx_FIFO_SIZE[x = 0, 3] Space Size (up to the size of the FIFO) 

0 0 x 33 bits 

1 32 x 33 bits 

2 64 x 33 bits 

3 96 x 33 bits 

4 128 x 33 bits 

The total size of RX FIFO is 128*33 bits. Therefore, the sum of all virtual channel FIFO allocation cannot 

exceed 128*33 bits. 

Table 7-69 indicates the start address of the space in the FIFO. 

Table 7-69. Virtual Channel RX FIFO Start Address 

DSI_RX_FIFO_VC_SIZE.VCx_FIFO_ADD[x = 0, 2] Start Address 

0 0 

1 32 

2 64 

3 96 

4 128 

CAUTION 

There must be no overlap of different VCs spaces. 

While reading the received bytes in the RX FIFO, only the DSS.DSI_VCn_SHORT_PACKET_HEADER 

register is used since the hardware does not keep track of the header position for long packets and 

start/end of each packet. The software must extract the information from the bytes read from the RX FIFO. 

There is no specific hardware to track the received bytes in the RX FIFO. The 

DSS.DSI_VCn_LONG_PACKET_HEADER and DSS.DSI_VCn_LONG_PACKET_PAYLOAD registers are 

not used. 

The ECC is only used by the first header when receiving multiple packets during the same LP RX transfer 

from the peripheral since the DSI Protocol engine does not parse the header to identify the length of the 

packets. In case of multiple packets, the Check-sum does not be enabled since the hardware checks the 

check-sum considering a single packet. The ECC in the first header is used to correct and check the 

header. For the following headers in the same LP RX transfer, the hardware does not detect any header 

and cannot check or/and detect errors in the headers of the packets except for the first packet. 

When the RX FIFO is empty: 

• there is no OCP error generated 

• the commands are accepted and the data for the responses are 0s 

7.5.4.10.3 Command Mode DMA Requests 

The DMA requests (DSI_DMA_REQ) are used to allow automatic transfer by the system DMA or MPU 

(with less efficiency and through-put capability) from the DSI RX FIFO to the system memory and from the 



1729



system memory to the DSI TX FIFO. Two independent DMA requests for RX FIFO and TX FIFO for the 

same VC are supported. The read and write accesses can use burst structure. The DSI protocol engine 

should access each write request in a burst without any IDLE between. For read OCP request in a burst to 

RX FIFO, the acceptance is sent immediately and the response is delayed by at least four L4 interface 

clock (DSS_L4_ICLK) cycles. In case of register reads, the response is returned in the first clock cycle. 

The thresholds used for requests for the TX FIFO and RX FIFO are programmable by software. Users 

program the DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD and DSS.DSI_VCn_CTRL[26:24] 

DMA_RX_THRESHOLD bit fields for TX FIFO and RX FIFO, respectively. Hardware asserts the DMA 

request based on the threshold value. The size of the space allocated in TX FIFO for each VC must be a 

multiple of the DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD bit field value. 

The only exception is in the case of the RX FIFO when the LP data transfer finishes and the threshold 

value is not reached. In that case the DMA request must be asserted. Therefore, the drain of the FIFO is 

supported in that configuration to empty the FIFO even if the number of data received is not a multiple of 

the threshold value. 

In case of TX FIFO, if all the bytes defined by the word count field in the 

DSS.DSI_VCn_LONG_PACKET_HEADER header register have been received, the DMA request is no 

longer asserted even during the last transfer less than DMA_TX_THRESHOLD number of bytes have 

been received because of the word count being not a multiple of the DMA_TX_THRESHOLD value. 

In case of RX FIFO, while the DMA request is used to transfer the data from the RX FIFO to the system 

memory, the system DMA must be programmed to read the number of received bytes in the FIFO. If users 

do not know the size of the received bytes, the direct access of the RX FIFO through the 

DSS.DSI_VCn_SHORT_PACKET_HEADER register is performed until the DSS.DSI_VCn_CTRL[20] 

RX_FIFO_NOT_EMPTY bit goes to 0. 

The use of each DMA request is programmable by software. The DSS.DSI_VCn_CTRL[23:21] 

DMA_TX_REQ_NB is dedicated to DMA request numbering for the TX FIFO. The 

DSS.DSI_VCn_CTRL[29:27] DMA_RX_REQ_NB is dedicated to DMA request numbering for the RX 

FIFO. 

When the DMA request is used to indicate the number of 32-bit values ready in the RX FIFO or BTA has 

been received from peripheral indicating end of the transfer from peripheral to host for a transfer to the 

system memory, the DMA request corresponding to the VC ID is generated. 

The system DMA transfers the number of 32-bit values defined in the threshold register or the exact 

number of bytes received from the peripheral (user should know the number of expected received bytes to 

program correctly the system DMA). When the system DMA transfers a multiple number of threshold 

value, the DSI protocol engine should send 0s for the data when there is no more received data in the RX 

FIFO for the VC. Software users must parse the data and determine the valid bytes. 

Software users can decide to determine the number of data received in the RX FIFO to read the 

information in the DSS.DSI_RX_FIFO_VC_FULLNESS register. Then the system DMA can be 

programmed to read the number of bytes from the RX FIFO. The BTA interrupt (BTA_IRQ) must be used 

to know when to read the number of received bytes. To monitor the BTA interrupt, the user must read the 

DSS.DSI_VCn_IRQSTATUS[5] BTA_IRQ status bit. The DMA request must not be selected until the 

system DMA is programmed with the correct number of data to read from RX FIFO. 

If the RX FIFO space for the VC is expected to be overflow because the number of data to be received is 

greater than the space allocated for the VC, the previous programming model must be used. In place, the 

DMA request must be asserted as soon as the threshold is reached or when BTA is received. 

When the DMA request is used to indicate the number of 33-bit entries empty in the TX FIFO for a 

transfer from the system memory, the DMA request corresponding to the VC ID is generated. 

NOTE: To obtain best efficiency of the transfer the size of the request (read or write, single or burst) 

must be aligned with the threshold value. 

Concurrent access using interlaced requests (read/write) to the TX and RX FIFO is supported for the 

same VC ID or different VC IDs. 





7.5.4.11 Ultra-Low Power State 

This section describes how to enter/exit to/from ultralow-power state (ULPS). 

NOTE: The DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIGy bits (x range is 1 to 3 

corresponding to lane #1 to lane #3, and y range is 1 to 2) must be read back after writing to 

verify that the write operations are effective before proceeding to the next step. This is to 

take latency at low TxClkEsc frequencies into account. 

7.5.4.11.1 Entering ULPS 

To enter into ULPS for a clock lane, the following sequence is required: 

1. Wait for DSS.DSI_COMPLEXIO_CFG2[16] HS_BUSY and DSS.DSI_COMPLEXIO_CFG2[17] 

LP_BUSY bits to be reset to 0 and ensure that the DSS.DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON 

bit is 0. 

2. TxUlpsClk state changes from inactive to active by setting the DSS.DSI_COMPLEXIO_CFG2 

LANEx_ULPS_SIG2 (x range is 1 to 3 corresponding to lane #1 to lane #3) bit to 1. 

To enter into ULPS for a data lane, the following sequence is required: 

1. Wait for all TX_FIFOs for all VCs working in HS are empty, for video mode is not active, and for 

DSS.DSI_COMPLEXIO_CFG2[16] HS_BUSY bit is reset to 0 (in addition for data lane #1, 

DSS.DSI_COMPLEXIO_CFG2[17] LP_BUSY bit is reset to 0) 

2. TxRequestEsc state changes from inactive to active by setting the DSS.DSI_COMPLEXIO_CFG2. 


NOTE: When the DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG2 and 

DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 bits are both being written to 0, they can 

be combined into one write. Both bits must be read back to confirm they are effective before 

proceeding. 

7.5.4.11.2 Exiting ULPS 

To exit from ULPS for a clock lane, the following sequence is required: 

1. Change the state of TxUlpsExit for each lane to ACTIVE by setting the DSS.DSI_COMPLEXIO_CFG2 


2. Wait for the ULPSACTIVENOT_ALL1_IRQ interrupt indicating that all lanes with TxUlpsExit active 

have acknowledged by asserting UlpsActiveNot. This is performed by monitoring the 

DSS.DSI_COMPLEXIO_IRQSTATUS[31] ULPSACTIVENOT_ALL1_IRQ status bit. 

3. Start the wake-up timer (GPTimer). 


5. Change TxUlpsClk signals to INACTIVE state for the clock lane by resetting the 

DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG2 (x range is 1 to 3 corresponding to lane #1 to lane 

#3) bit to 0. 

6. Reset the DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 (x range is 1 to 3 corresponding to lane 

#1 to lane #3) bit to 0. 




proceeding. 

To exit from ULPS for a clock lane, in case ComplexIO is in OFF state (the DSI protocol engine sends 

ComplexIO to OFF state by setting DSS.DSI_COMPLEXIO_CFG1[28:27] PWROFF = 0x0), the sequence 

is: 



1731



1. Change TxUlpsClk signals to INACTIVE state for the clock lane by resetting the 


#3) bit to 0. 

2. Change the state of TxUlpsExit for clock lane to INACTIVE state by resetting the 


#3) bit to 0. This step is necessary only in case a PWROFF command (the command for power control 

of the complex I/O) is issued while the sequence for exiting is in progress (TxUlpsExit signal is already 

in ACTIVE state). 




proceeding. 

To exit from ULPS for a data lane, the following sequence is required: 

1. Change the state of TxUlpsExit for each lane to ACTIVE by setting the DSS.DSI_COMPLEXIO_CFG2 


2. Wait for the ULPSACTIVENOT_ALL1_IRQ interrupt indicating that all lanes with TxUlpsExit active 

have acknowledged by asserting UlpsActiveNot. This is performed by monitoring the 

DSS.DSI_COMPLEXIO_IRQSTATUS[31] ULPSACTIVENOT_ALL1_IRQ status bit. 

3. Start the application wake-up timer (GPtimer). 


5. Change TxRequestEsc signals to INACTIVE state for the data lane by resetting the 


#3) bit to 0. 

6. Reset the DSS.DSI_COMPLEXIO_CFG2 LANEx_ULPS_SIG1 (x range is 1 to 3 corresponding to lane 

#1 to lane #3) bit to 0. 




proceeding. 

To exit from ULPS for a data lane, in case ComplexIO is in OFF state (the DSI protocol engine sends 

ComplexIO into OFF state by setting DSS.DSI_COMPLEXIO_CFG1[28:27] PWROFF = 0x0), the 

sequence is: 

1. Change TxRequestEsc signals to INACTIVE state by resetting the DSS.DSI_COMPLEXIO_CFG2 


2. Change the state of TxUlpsExit to INACTIVE state by resetting the DSS.DSI_COMPLEXIO_CFG2 

LANEx_ULPS_SIG1 (x range is 1 to 3 corresponding to lane #1 to lane #3) bit to 0. This step is 

necessary only in case a PWROFF command is issued while the sequence for exiting is in progress 

(TxUlpsExit signal is already in ACTIVE state). 




proceeding. 

When the sequence for entering/exiting into/from ULP state is started for specific lanes, users must wait 

for the sequence to complete before changing the state of the same or other lanes. 

7.5.4.12 DSI Programming Sequence Example 

This section describes distinct configurations of the DSI protocol engine to support different type of traffics. 





NOTE: When the VC is used to send video mode data from the video port, the 

DSS.DSI_VCn_CTRL[9] MODE_SPEED and the DSS.DSI_VCn_CTRL[1] SOURCE bits are 

ignored. 

7.5.4.12.1 Video Mode Transfer 

Description: One channel, video mode, no DMA requests, no bus turn-around. 

1. Configure the display controller with the timing parameters. 

2. Configure the DSS.DSI_VCn_CTRL register as follows: 

• SOURCE bit is ignored by hardware 

• BTA_LONG_EN bit is set to 0: No BTA on long packet 

• BTA_SHORT_EN bit is set to 0: No BTA on short packet 

• MODE bit set to 1: The video mode is selected 

• MODE_SPEED bit is ignored by hardware 

3. Configure the DSS.DSI_VM_TIMING1 to DSS.DSI_VM_TIMING7 registers. 

4. Set the ForceTxStopMode bit to 1 in the DSS.DSI_TIMING1 register. 

5. Enable the channel by setting the DSS.DSI_VCn_CTRL[0] VC_EN bit to 1 

6. Enable the module by setting the DSS.DSI_CTRL[0] IF_EN bit to 1. 

7. Poll the ForceTxStopMode bit to 0 in the DSS.DSI_TIMING1 register. 

8. Enable the LCD video output by setting the DSS.DISPC_CONTROL[0] LCDENABLE bit to 1 

CAUTION 

The restriction for stopping the video mode is that no frame must be sent by the 

display controller (DISPC) after disabling video mode in DSI. 

7.5.4.12.2 Command Mode Transfer Example 1 

CAUTION 

In DSI command mode, the display controller must be configured in stall mode 

by setting the DSS.DISPC_CONTROL[11] STALLMODE bit to 1. 

Description: One channel, command mode, no DMA requests, manual bus turn-around 


• SOURCE bit set to 0: The source is the L4 interconnect port 

• BTA_LONG_EN bit is set to 0: No automatic BTA on long packet 

• BTA_SHORT_EN bit is set to 0: No automatic BTA on short packet 

• MODE bit set to 0: The command mode is selected 

2. Enable the packet sent interrupt by setting the DSS.DSI_VCn_IRQENABLE[2] 

PACKET_SENT_IRQ_EN bit to 1 

3. Set the ForceTxStopMode bit to 1 in the DSS.DSI_TIMING1 register. 


5. Enable the module by setting the DSS.DSI_CTRL[0] IF_EN bit to 1 

6. Poll the ForceTxStopMode bit to 0 in the DSS.DSI_TIMING1 register. 

For long packet: 

• Write the header value into the DSS.DSI_VCn_LONG_PACKET_HEADER register 

• Write the data into the DSS.DSI_VCn_LONG_PACKET_PAYLOAD register for the full payload. 

Repeat step until WC is reached (see DSI_VCn_LONG_PACKET_HEADER) 

For short packet: 

• Send short packets through the L4 interconnect: Write the header value into the 



1733



DSS.DSI_VCn_SHORT_PACKET_HEADER register. Repeat step for each short packet. 

7. Send one or more packets through L4 interconnect: 

• Write the header value into DSS.DSI_VCn_LONG_PACKET_HEADER register 

• Write the data into DSS.DSI_VCn_LONG_PACKET_PAYLOAD register for the full payload. 

• Repeat step 5 for all the long packets 

8. Send short packets through L4 interconnect: 

• Write the header value into DSS.DSI_VCn_SHORT_PACKET_HEADER register 

• Repeat step 6 for all the short packets 

9. Interrupt routine: Wait for PACKET_SENT_IRQ interrupt generation by polling the 

DSS.DSI_VCn_IRQSTATUS[2] PACKET_SENT_IRQ status bit and notify the application software 

when received. 

10. The applicative software forces the bus turn-around: 

• Wait until the PACKET_SENT_IRQ has happened as many times as the number of sent packets 

• Set the DSS.DSI_VCn_CTRL[6] BTA_EN bit to 1 to send manually a BTA 

• Wait until the DSS.DSI_VCn_CTRL[6] BTA_EN bit is reset to 0 by hardware 

11. Receive the packets from the peripheral 

• Start polling the DSS.DSI_VCn_CTRL[20] RX_FIFO_NOT_EMPTY status bit 

• Whenever the RX_FIFO_NOT_EMPTY bit equals to 1, read one word in the RX FIFO 

7.5.4.12.3 Command Mode Transfer Example 2 

CAUTION 

In DSI command mode, the display controller must be configured in stall mode 

by setting the DSS.DISPC_CONTROL[11] STALLMODE bit to 1. 

Description: One channel, command mode, DMA request, automatic bus turn-around 


• SOURCE bit set to 0: The source is the L4 interconnect port 

• BTA_LONG_EN bit is set to 1: Automatic BTA on long packet 

• BTA_SHORT_EN bit is set to 1: Automatic BTA on short packet 

• MODE bit set to 0: The command mode is selected 

2. Enable the packet sent interrupt by setting the DSS.DSI_VCn_IRQENABLE[2] 

PACKET_SENT_IRQ_EN bit to 1 

3. Set the ForceTxStopMode bit to 1 in DSS.DSI_TIMING1 register. 


5. Configure the TX FIFO threshold and DMA requests parameters: 

• Program the DSS.DSI_VCn_CTRL[19:17] DMA_TX_THRESHOLD bit field 

• Program the DSS.DSI_VCn_CTRL[23:21] DMA_TX_REQ_NB bit field 

6. Program the system DMA to be ready to send data to the L4 interconnect port 

7. Enable the module by setting the DSS.DSI_CTRL[0] IF_EN bit to 1 

8. Poll the ForceTxStopMode bit to 0 in DSS.DSI_TIMING1 register. 

9. Write the header value into DSS.DSI_VCn_LONG_PACKET_HEADER register 

10. Interrupt routine: Wait for PACKET_SENT_IRQ interrupt generation by polling the 

DSS.DSI_VCn_IRQSTATUS[2] PACKET_SENT_IRQ status bit and notify the application software 

when received. 

11. Receive the packets from the peripheral 

• Start polling the DSS.DSI_VCn_CTRL[20] RX_FIFO_NOT_EMPTY status bit 

• Whenever the RX_FIFO_NOT_EMPTY bit equals to 1, read one 32-bit word in the RX FIFO 

12. Repeat the steps 7 for all long packets. 



PCLK 

SYSCLK 

PMP 

SCP 

SCPBusy 

UPDATE 

SYNC 

Registers 

Go bit 

PLL 

Reference 



7.5.5 DSI PLL Controller Basic Programming Model 


The DSI PLL control module does not have its own software reset. It is reset by the DSI protocol engine. 

Nevertheless, software users can monitor the reset status of the DSI PLL control module by reading the 

DSS.DSI_PLL_STATUS[0] DSI_PLLCTRL_RESET_DONE status bit. 

7.5.5.2 DSI PLL Programming Blocks 

Figure 7-135 shows the DSI PLL programming blocks. 

Figure 7-135. DSI PLL Programming Blocks 

Shadow registers 

DSI_PLLCTRL 

PMP 

FSM 

GO 

FSM 

CLKINP 

SYSRESETs 

Configuration 

values 

TINITZ 

etc. 



dss-181 

1735

Manual Mode 



7.5.5.3 DSI PLL Go Sequence 

In Manual Mode (DSS.DSI_PLL_CONTROL[0] DSI_PLL_AUTOMODE bit set to 0), the DPLL requires a 

sequence on TINITZ, TENABLE and TENABLEDIV to update the configuration values and start the 

locking sequence. 

Once all the configuration values have been programmed into the registers, the GO bit must be set. The 

appropriate sequence should then be sent on the TINITZ, TENABLE, and TENABLEDIV pins, respecting 

the timing requirements of the ADPLLM. The DSS.DSI_PLL_GO[0] DSI_PLL_GO bit are cleared to 0 at 

the end of the sequence. 

Because the TENABLEDIV signal is shared with the HSDIVIDER module, it is programmed at the same 

time. In this mode, software must deassert CLKINEN by unsetting the 

DSS.DSI_PLL_CONFIGURATION2[14] DSI_PHY_CLKINEN to 0 and assert HSDIVBYPASS correctly by 

setting the DSS.DSI_PLL_CONFIGURATION2[20] DSI_HSDIVBYPASS bit to 1 to prevent uncontrolled 

frequencies affecting the DSI_PHY and display subsystem during PLL locking. In manual mode the 

shadow register must be updated anyway so that valid values are present when later selecting automatic 

mode. 

Figure 7-136 shows the DSI PLL Go flow chart in manual mode (DSS.DSI_PLL_CONTROL[0] 

DSI_PLL_AUTOMODE bit set to 0). 

Figure 7-136. DSI PLL Go Sequence (Manual Mode) 

DSI_PLL_GO[0].DSI_PLL_GO bit set to 1 by software 

Generate TINITZ, etc. Sequence PLL reprogrammed 

Clear DSI_PLL_GO[0] DSI_PLL_GO bit to 0 

Completed 

NOTE: All thick-outlined blocks show operations performed by software. Other blocks show operations performed 

by hardware. 

In automatic mode (DSS.DSI_PLL_CONTROL[0] DSI_PLL_AUTOMODE bit set to 1),the TINITZ, 

TENABLE and TENABLEDIV sequence and the update of the PLL configuration from the 

DSI_PLL_CONFIGURATION2 register are deferred until the time of the front porch time signal sent by the 

DISPC module. This is intended to simplify the software to implement a configuration change (such as a 

frequency change to support a different link bandwidth). In this mode CLKINEN, HSDIVBYPASS and 

REFEN are controlled automatically and the register value is overridden. 

Figure 7-137 shows the DSI PLL Go flow chart in automatic mode (DSS.DSI_PLL_CONTROL[0] 

DSI_PLL_AUTOMODE bit set to 1). 



dss-182

Automatic mode 

DSI_PLL_CONFIGURATION[13].DSI_PLL_REFEN bit set to 1 

DSI_PLL_GO[0].DSI_PLL_GO bit set to 1 by software 

No 

No 

No 

Yes 

DISPC_UPDATE_SYNC signal 

asserted? 

Yes 

Update shadow register 

Generate TINITZ, etc. sequence 

Lock asserted ? 



Figure 7-137. DSI PLL Go Sequence (Automatic Mode) 

Clear CLKINEN to 0 

Set HSDIVBYPASS to 1 

BYPASSACKZ = 0? 

Yes 

Yes 

Set CLKINEN to 1 

Clear HSDIVBYPASS to 0 

Clear DSI_PLL_GO[0] DSI_PLL_GO bit to 0 

Synchronize to 

DISPC vertical 

blanking 

CLKIN4DDR clock stops 

HSDIVIDER bypassed 

PLL and HDIVIDER 

in bypass 

Configuration signals 

updated 

PLL reprogrammed 

Wait for PLL to relock 

CLKIN4DDR clock runs 

HSDIVIDER running 

Completed 

NOTE: All thick-outlined blocks show operations performed by software. Other blocks show operations performed 

by hardware. 

7.5.5.4 DSI PLL Clock Gating Sequence 

Clock gating can be used to reduce system power consumption when the DSI protocol engine indicates 

that it does not need the clock. If the HSDIVIDER is not used, the PLL can also be stopped (at the cost of 

additional unstarting latency). 

The DSI protocol engine can verify when the PLL has unstarted by inspecting the LOCK signal 

(DSS.DSI_PLL_STATUS[1] DSI_PLL_LOCK status bit). Because TxByteClkHS is stopped when the 

CLKIN4DDR is stopped, this should obviate the need for any explicit feedback that the clock has been 

unstarted in the other case. This flow chart should run even if the DSS.DSI_PLL_GO[0] DSI_PLL_GO bit 

has not been set. 

Figure 7-138 shows the DSI PLL gated mode sequence. 



dss-183 

1737

Yes 

DIS_PLL_GO(0)DSI_PLL_GO 

bit set to 1 by software? 

DSIStopClk signal 

asserted? 

No 

Set CLKINEN bit to 1 

No 

Yes 

No 

Yes 

No 

No 

Yes 

CLKIN4DDR runs 



Figure 7-138. Gated Mode Sequence 

Gated mode 


asserted? 

Yes 

Clear CLKINEN = 0 

HSDIVIDER used? 

(*1) 

DSI_PLL_CONTROL[2] 

DSI_PLL_HALTMODE 

bit = 1? (*1) 

Yes 


asserted? 

No 

Yes 

No 

Clear REFEN bit to 0 

Set REFEN to 1 

Lock asserted? 

NOTE: All thick-outlined blocks show operations performed by software. 

7.5.5.5 DSI PLL Lock Sequence 


idle 

CLKIN4DDR stops 

HSDIVIDER is used if 

DSS_CONTROL[0] DISPC_CLK_SWITCH = 1 

or 

DSS_CONTROL[1] DSI_CLK_SWITCH = 1 

PLL input stopped 


idle 

PLL input started 

Wait for PLL to relock 

The DSI PLL (ADPLLM) generates the CLKIN4DDR clock. The HSDIVIDER generates two clocks: 

DSI1_PLL_FCLK connected to the display controller (DISPC) and the DSI2_PLL_FCLK connected to the 

DSI protocol engine. If these two clocks are not used, the HSDIVIDER functions are not required. 

The CLKIN4DDR is twice the data rate, and is four times the DSI output clock frequency. The DSI PLL 

factors need to be calculated based on the required input and output frequencies, keeping the PLL internal 

reference frequency in the appropriate range: 



dss-184

Set 

DSI_PLL_CONFIGURATION2[12] 

DSI_PLL_HIGHFREQ bit to 0 

Set REGM3 factor such that 

CLKIN4DDR DSI _ PHY ( MHz) 

DSI1_ PLL _ FCLK( MHz) 

 

REGM 3 1 

START 

Select the pixel clock frequency 

according to panel size 

Select the DSI PLL clock source (CLKin) 

(either SYS_CLK or PCLKFREE) by setting 

the DSI_PLL_CONFIGURATION2[11] 

DSI_PLL_CLKSEL bit 

Yes No 

Clock frequency



NOTE: 

• The REGM3 and REGM4 factors must according with the following conditions: 

– The DSI1_PLL_FCLK and DSI2_PLL_FCLK frequencies must be a multiple of the 

PCLK frequency (for proper settings of PCD and LCD factors in the DISPC). 

– The DSI1_PLL_FCLK and DSI2_PLL_FCLK frequencies must be lower than 173 

MHz at nominal voltage (OPP100), and lower than 100 MHz at low voltage 

(OPP50). 

• Most of the other DSI PLL programming values are available for software flexibility but it 

is not recommended to update the values in normal use. See Section 7.5.5.7 for details 

on DSI PLL recommended values. 

DSI PLL programming examples: 

• WVGA Display on one data pair: Pixel clock (PCLK) = 30 MHz with 18-BPP pixel format 

The data rate is 30 × 18 = 540 Mbps on one data lane. Therefore, the frequency on the data lane is twice 

the data rate: 1080 MHz. 

The frequency on the clock lane is 270 MHz (1080 divided by 4). 

The SYS_CLK at 26 MHz is selected as the clock reference by setting the 

DSS.DSI_PLL_CONFIGURATION2[11] DSI_PLL_CLKSEL to 0b0. 

Set the DSS.DSI_PLL_CONFIGURATION2[12] DSI_PLL_HIGHFREQ to 0b0 as PCLK is lower than 32 

MHz. 

Set Fint to 2 MHz as PLL internal reference frequency: Set REGN to 12 (divide by 13) by setting the 

DSS.DSI_PLL_CONFIGURATION1[7:1] DSI_PLL_REGN bit field to 0xC. 

To get the CLKIN4DDR to 1080 MHz, set the REGM factor to 270 by setting the 

DSS.DSI_PLL_CONFIGURATION1[18:8] DSI_PLL_REGM to 0x10E. 

DSI_PHY = 2 x 270/13 x 26/1 = 1080 MHz 

Because DSI1_PLL_FCLK and DSI2_PLL_FCLK (REGM3 and REGM4 factors) must be multiples of 

PCLK and also lower than 173 MHz at nominal voltage (OPP100), and lower than 100 MHz at low voltage 

(OPP50), program these frequencies to 90 MHz by setting the REGM3 and REGM4 factors to 11 (divide 

by 12). This is done by setting the DSS.DSI_PLL_CONFIGURATION1[22:19] DSS_CLOCK_DIV bit field 

and DSS.DSI_PLL_CONFIGURATION1[26:23] DSIPROTO_CLOCK_DIV to 0xB: 

DSI1_PLL_FCLK = DSI2_PLL_FCLK = 1080/12 = 90 MHz 

• XGA Display on two data pairs: Pixel clock (PCLK) = 60 MHz with 16-BPP pixel format 

The data rate is (60 × 16)/2 = 480 Mbps on each data lane. Therefore, the frequency on the data lane 

is twice the data rate: 960 MHz. 

The frequency on the clock lane is 240 MHz (960 divided by 4). 

The SYS_CLK at 26 MHz is selected as the clock reference by setting the 

DSS.DSI_PLL_CONFIGURATION2[11] DSI_PLL_CLKSEL bit to 0b0. 

Set the DSS.DSI_PLL_CONFIGURATION2[12] DSI_PLL_HIGHFREQ bit to 0b0 as the source clock 

frequency (SYS_CLK in this example) is lower than 32 MHz. 

Set Fint to 2 MHz as PLL internal reference frequency: Set REGN to 12 (divide by 13) by setting the 

DSS.DSI_PLL_CONFIGURATION1[7:1] DSI_PLL_REGN bit field to 0xC. 

To get the CLKIN4DDR to 960 MHz, set the REGM factor to 240 by setting the 

DSS.DSI_PLL_CONFIGURATION1[18:8] DSI_PLL_REGM to 0x0F0. 

DSI_PHY = 2 × 240/13 × 26/1 = 960 MHz 

Because DSI1_PLL_FCLK and DSI2_PLL_FCLK (REGM3 and REGM4 factors) must be multiples of 

PCLK and also lower than 173 MHz at nominal voltage (OPP100), program these frequencies to 120 

MHz by setting the REGM3 and REGM4 factors to 7 (divide by 8). This is done by setting the 

DSS.DSI_PLL_CONFIGURATION1[22:19] DSS_CLOCK_DIV bit field and 

DSS.DSI_PLL_CONFIGURATION1[26:23] DSIPROTO_CLOCK_DIV to 0x7: 

DSI1_PLL_FCLK = DSI2_PLL_FCLK = 960/8 = 120 MHz 





7.5.5.6 DSI PLL Error Handling 

The PLL lock and recalibration signals may be monitored to detect loss of lock or requirement to 

recalibrate (due to large temperature change since the last lock request): 

• The DSS.DSI_PLL_STATUS[1] DSI_PLL_LOCK status bit gives the DSI PLL lock state. 

• The DSS.DSI_PLL_STATUS[2] DSI_PLL_RECAL status bit informs if the PLL must be uncalibrated 

These signals can also generate interrupts at DSI protocol engine level: 

• DSS.DSI_IRQSTATUS[9], PLL_RECAL_IRQ bit 

• DSS.DSI_IRQSTATUS[8] PLL_UNLOCK_IRQ 

• DSS.DSI_IRQSTATUS[7] PLL_LOCK_IRQ 

The PLL_LOCK_IRQ interrupt indicates that the DSI PLL is locked. To monitor this event, read the 

DSS.DSI_IRQSTATUS[7] PLL_LOCK_IRQ bit. Set this bit to 1 to clear the status bit. 

The PLL_UNLOCK_IRQ interrupt indicates that the DSI PLL is unlocked. To monitor this event, read the 

DSS.DSI_IRQSTATUS[8] PLL_UNLOCK_IRQ bit. Set this bit to 1 to clear the status bit. 

The PLL_RECAL_IRQ interrupt indicates that the DSI PLL must be recalibrated. To monitor this event, 

read the DSS.DSI_IRQSTATUS[9] PLL_RECAL_IRQ bit. Set this bit to 1 to clear the status bit. 

The PLL reference loss and limp status signals can also be monitored: 

• The DSS.DSI_PLL_STATUS[3] DSI_PLL_LOSSREF status bit informs if the DSI PLL has lost the 

reference. 

• The DSS.DSI_PLL_STATUS[4] DSI_PLL_LIMP status bit informs about the DSI PLL limp status. 

7.5.5.7 DSI PLL Recommended Values 

Table 7-70 shows the DSI PLL recommended values. 

Table 7-70. Recommended Programming Values 

Field Name Value Description 

DSI_HSDIV_SYSRESET 0 Allow power FSM to control 

DSI_PLL_SYSRESET 0 Allow power FSM to control 

DSI_PLL_HALTMODE - See Section 7.5.5.4 for details 

DSI_PLL_GATEMODE - See Section 7.5.5.4 for details 

DSI_PLL_AUTOMODE - See Section 7.5.5.4 for details 

DSI_PLL_GO 1-0 Write a 1 when PLL is to be (re-)locked 

with new parameters. This bit is cleared 

by hardware when the PLL request has 

completed 

DSIPROTO_CLOCK_DIV See (1) DSI protocol engine clock divider 

DSS_CLOCK_DIV See (1) DSS clock divider 

DSI_PLL_REGM See (1) Feedback clock divider 

DSI_PLL_REGN See (1) Reference clock divider 

DSI_PLL_STOPMODE 1 Required to use GATEMODE bit 

DSI_HSDIVBYPASS 0 PLL is controlling HSDIVIDER bypass 

DSI_PROTO_CLOCK_PWDN 0 If PLL/HSDIVIDER is used as the DSI 

protocol clock source 

DSI_PROTO_CLOCK_EN 1 If PLL/HSDIVIDER is used as the DSI 

protocol clock source 

DSS_CLOCK_PWDN 0 If PLL/HSDIVIDER is used as the DSS 

clock source 

DSS_CLOCK_EN 1 If PLL/HSDIVIDER is used as the DSS 

clock source 

(1) The bit field value must be set according to the desired clock frequency. 





Table 7-70. Recommended Programming Values (continued) 

Field Name Value Description 

DSI_BYPASSEN 0 To use PLL as the clock source. For 

small displays it may be possible to use 

the DSS functional clock, in which case 

this bit must be set to 1 

DSI_PHY_CLKINEN 1 Enable CLKIN4DDR 

DSI_PLL_REFEN 1 Enable PLL reference 

DSI_PLL_HIGHFREQ 0/1 Set to 1 if the clock reference is higher 

than 32 MHz (21 MHz if 

DSS.DSI_PLL_CONFIGURATION1[7:1] 

DSI_PLL_REGN = 0) 

DSI_PLL_CLKSEL 0/1 Set to 0 to use DSS2_ALWON_FCLK as 

the PLL reference or set to 1 to use 

PCLKFREE as the PLL reference, in this 

case the DISPC must be using 

DSS1_ALWON_FCLK. 

DSI_PLL_LOCKSEL 0x0 Phase lock criteria to lock the PLL 

DSI_PLL_DRIFTGUARDEN 0x0 The RECAL status/interrupt must be 

used to decide when to perform a PLL 

uncalibration No automatic uncalibration 

is performed 

DSI_PLL_TIGHTPHASELOCK 0 Normal criteria 

DSI_LOWCURRSTDBY 0/1 Set to 0 for fast PLL unlock, but higher 

standby current Set to 1 for leakage 

level standby current, but longer unlock 

time 

DSI_PLL_PLLLPMODE 0 Normal operation For smaller display 

sizes may be possible to set to 1 

DSI_PLL_IDLE 0 PLL active 

7.5.6 DSI Complex I/O Basic Programming Model 


The clock domain using the TxByteClkHS from the DSI complex I/O has a dedicated reset done 

information in the DSS.DSI_COMPLEXIO_CFG1[29] RESET_DONE bit. The DSS.DSI_SYSCONFIG[1] 

SOFT_RESET bit is used to reset the TxByteClkHS power domain. A dummy read using the SCP 

interface to any DSI_PHY register is required after DSI_PHY reset to complete the reset of the DSI 

complex I/O. 

7.5.6.2 Reset-Done Bits 

The DSI complex I/O has several clock domains. The reset status for each clock domain is provided in 

DSS.DSI_PHY_REGISTER5 register: 

• DSS.DSI_PHY_REGISTER5 [31] RESETDONETXBYTECLK bit : Reset done for the TXBYTECLK 

domain. 

• DSS.DSI_PHY_REGISTER5 [26:24] RESETDONETXCLKESCi bits: Reset done for the TXCLKESC 

domain for lane i (i between 0 and 2). 

• DSS.DSI_PHY_REGISTER5 [30] RESETDONESCPCLK bit: Reset done for the SCP clock domain. 

Software users must perform a dummy read on this bit to initiate the reset sequence of the SCP finite 

state machine. When the reset sequence is complete, the RESETDONESCPCLK signal goes high and 

software users can read again the DSS.DSI_PHY_REGISTER5 [30] RESETDONESCPCLK bit to 

ensure that the value is now 1. 

NOTE: Software must not write in the DSI_PHY_SCP registers before the 

DSS.DSI_PHY_REGISTER5 [30] RESETDONESCPCLK bit is set to 1. 



TXBYTECLKHS 

(O) 

TXREQUESTHS 

(I) 

DP/DN 

TXREADYHS 

(O) 

STOPSTATE 

(O) 

T LPX 

T CLK-PREPARE 

T CLK-ZERO 



• DSS.DSI_PHY_REGISTER5 [29] RESETDONEPWRCLK bit: Reset done for the PWR clock domain. 

The reset sequence of the PWR finite state-machine is complete when the RESETDONEPWRCLK 

signal goes high. 

7.5.6.3 Pad Configuration 

The number of lanes is configurable through the DSS.DSI_COMPLEXIO_CFG1 register. 

It is not allowed to change on the fly the position (by modifying the DATAi_POSITION with i = 1 or 2 and 

CLOCK_POSITION bit fields), P/N order (Positive/Negative order of the differential pair by modifying the 

DATAi_POL with i = 1 or 2 and CLOCK_POL) or number of active data lanes (by modifying the 

DSS.DSI_COMPLEXIO_CFG1[10:8] DATA2_POSITION bit). To add or remove the lane #2, it is required 

to be in OFF mode for the DSI complex I/O. 

The minimum requirement for the number of lanes is one clock lane and one data lane. Note that by 

default, the data lane 2 is not connected (the DSS.DSI_COMPLEXIO_CFG1[10:8] DATA2_POSITION bit 

reset value is 0). 

7.5.6.4 Display Timing Configuration 

NOTE: Copyright © 2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member 

Confidential. 

Depending on the CLKIN4DDR frequency settings programmed with the DSI PLL control module, software 

users must program accordingly the timing parameters in the DSI complex I/O registers. 

7.5.6.4.1 High-Speed Clock Transmission 

Figure 7-140 shows an example of high-speed Clock Transmission. 

Figure 7-140. High-Speed Clock Transmission 

HS CLK transmission 

TXByteClkHS is an output clock which is derived by dividing CLKIN4DDR by 16. 

T CLK-TRAIL 



T HS-EXIT 

dss-185 

1743



To begin transmission, the protocol drives TXREQUESTHS high on a rising edge of TXByteClkHS. The 

PHY detects this signal on the next rising edge, following which it initiates the LP Start of Transmission 

(SoT) procedure. 

During a high-speed Clock Transmission, these parameters are defined in multiples of CLKIN4DDR and 

programmed by the following register bit fields: 

• TLPX timing is programmed by the DSS.DSI_PHY_REGISTER1[20:16] REG_TLPXBY2 bit field. 

• THS-PREPARE timing is programmed by the DSS.DSI_PHY_REGISTER0[31:24] 

REG_THSPREPARE bit field. 

• TCLK-ZERO timing is programmed by the DSS.DSI_PHY_REGISTER1[7:0] REG_TCLKZERO bit field. 

TCLK-ZERO is extended, if required, so that the entire LP SoT procedure lasts an integer number of 

TXByteClkHS cycles. 

At the end of the SoT procedure, HS clock transmission begins. At the same time, TXREADYHS is made 

high. 

To stop clock transmission, the protocol drives TXREQUESTHS low on a rising edge of TXByteClkHS. 

The DSI_PHY detects this change in TXREQUESTHS on the next edge and stops clock transmission. 

TXREADYHS is made low. 

The DSI_PHY then goes through the LP End of Transmission (EoT) procedure. TCLK-TRAIL and 

THS-EXIT parameters are also multiples of CLKIN4DDR and programmed by the following register fields: 

• TCLK-TRAIL timing is programmed by the DSS.DSI_PHY_REGISTER1[15:8] REG_TCLKTRAIL bit 

field. 

• THS-EXIT timing is programmed by the DSS.DSI_PHY_REGISTER0[7:0] REG_THSEXIT bit field. 

The DSI_PHY completes the SoT and EoT procedures, once begun, irrespective of any change in PPI 

signals. If TXREQUESTHS goes low during the SoT procedure, the PHY start the EoT procedure 

immediately after finishing the SoT procedure and no clock is transmitted. 

STOPSTATE is high whenever the line is in LP-11 state, as determined by the outputs of the Low Power 

Receivers. This signal is not synchronized with TXByteClkHS. 

It is requires that the high speed clock be present for some time before (TCLK-PRE) and some time after 

(TCLK-POST) high speed data transmission. The protocol must ensure that these timings are met by 

asserting and deasserting TXREQUESTHS appropriately. 

The PHY ensures that the clock signal has a quadrature-phase with respect to a toggling bit sequence on 

any Data Lane, and a rising edge in the center of the first transmitted bit of every Data byte. These 

relations are not described in the timing diagram. 

CLKIN4DDR can be shut off 300ns after the clock lane goes to STOPSTATE. Alternatively, CLKIN4DDR 

can be shut down after TCLK-Trail + THS-Exit + 2 Txbyteclk periods after TxRequestHS falling edge is 

received by DSI_PHY. 

The DSI protocol engine must ensure that TXREQUESTESC, TXULPSCLK, and TURNREQUEST are low 

whenever TXREQUESTHS is asserted. 

7.5.6.4.2 High-Speed Data Transmission 

Figure 7-141 shows an example of high-speed Data Transmission. 



TXBYTECLKHS 

(O) 

TXREQUESTHS 

(I) 

DP/DN 

TXREADYHS 

(O) 

TXDATAHSB7–B0 

(I) 

STOPSTATE 

(O) 

T LPX 

T HS-PREPARE 

T HS-ZERO 



Figure 7-141. High-Speed Data Transmission 

T HS_SYNC 

HS DATA transmission 

(BYTE1, BYTE2...) 

VALID DATA 

(BYTE2, BYTE3...) 

SAMPLED BY DSI_PHY ON +VE 

EDGES OF TXBYTECLKHS 

T HS-TRAIL 

T HS-EXIT 

BYTE1 DATA HERE IS IGNORED 

TXByteClkHS is an output clock which is derived by dividing CLKIN4DDR by 16. 

To begin transmission, the protocol drives TXDATAHS with the first byte of data on a rising edge of 

TXByteClkHS. It also makes TXREQUESTHS high the same rising edge. The PHY detects 

TXREQUESTHS going high on the next rising edge of TXByteClkHS, following which it initiates the LP 

Start of Transmission (SoT) procedure. 

During a high-speed Data Transmission, these timings are multiple of CLKIN4DDR and programmed by 

the following register bit fields: 

• TLPX timing is programmed by the DSS.DSI_PHY_REGISTER1[20:16] REG_TLPXBY2 bit field. 

• THS-PREPARE + THS-ZERO timing is programmed by the DSS.DSI_PHY_REGISTER0[23:16] 

REG_THSPRPR_THSZERO bit field. 

THS-ZERO will be extended, if required, so that the entire LP SoT procedure lasts an integer number of 

TXByteClkHS cycles. THS-SYNC corresponds to the length of the sync pattern which is 8 high-speed bits, 

and can be configured through the DSI_PHY_REGISTER2[31:24] HSSYNCPATTERN bit field. 

Towards the end of the SoT procedure, the PHY makes TXREADYHS high on a positive edge of 

TXByteClkHS and then start accepting data from TXDATAHS from the next positive edge onwards. The 

protocol is expected to provide (new) valid data on TXDATAHS on every positive edge of TXByteClkHS if 

TXREADYHS is high. 

At the end of the SoT procedure, HS data transmission begins. HS Data Transmission happens LSB first. 

To stop data transmission, the protocol drives TXREQUESTHS low on a rising edge of TXByteClkHS. The 

PHY detects this change in TXREQUESTHS on the next edge and stops data transmission. TXREADYHS 

is made low and data on TXDATAHS, from that point, is ignored. 



dss-186 

1745

TXCLKESC 

TURNREQUEST 

DP/DN 

DIRECTION 



The PHY then goes through the LP End of Transmission (EoT) procedure. THS-TRAIL and THS-EXIT are 

also multiples of CLKIN4DDR and programmed by the following register bit fields: 

• THS-TRAIL timing is programmed by the DSS.DSI_PHY_REGISTER0[15:8] REG_THSTRAIL bit field. 

• THS-EXIT timing is programmed by the DSS.DSI_PHY_REGISTER0[7:0] REG_THSEXIT bit field. 

The PHY completes the SoT and EoT procedures, once begun, irrespective of any change in PPI signals. 

If TXREQUESTHS goes low during the SoT procedure, the PHY start the EoT procedure immediately 

after finishing the SoT procedure and no data is transmitted. 

STOPSTATE is high whenever the line is in LP-11 state, as determined by the outputs of the low power 

receivers. This signal is not synchronized with TXByteClkHS. 

The protocol must ensure that TXREQUESTESC, TXULPSCLK, and TURNREQUEST are low whenever 

TXREQUESTHS is asserted. 

7.5.6.4.3 Turn-Around Request in Transmit Mode 

When the DSI PHY is in transmit mode, the DSI protocol engine can request a turnaround by making the 

TurnRequest signal high for at least one clock cycle of TxClkEsc (see Section 7.4.3.7.3, TurnRequest 

FSM). 

The DSI PHY transmits the turn-around request pattern (LP 11-10-00-10-00-00-00-00) (see Figure 7-142). 

The number of 00 states in the end of the pattern is defined by T TA-GO timing parameter and is 

programmable through the DSS.DSI_PHY_REGISTER1[31:29] REG_TTAGO bit field, in number of 

TxClkEsc clocks. Following the transmission of the pattern, the DSI PHY disables its LP transmitters and 

waits for an acknowledgment from the remote device. The remote device detects the turn-around request 

and acknowledges it by driving LP-10, followed by the STOP state. When this acknowledgment is 

received, DSI PHY switches to receive mode and indicates the completion of the turn-around procedure 

by changing the direction (BTA_IRQ is asserted, as described in Section 7.4.3.8, Bus Turnaround). 

Figure 7-142. Turn-Around Request in Transmit Mode 

LP-11 LP-10 LP-00 LP-10 LP-00 LP-00 LP-00 LP-00 LP-00 

LP state driven by remote LPTX 

LP state driven by DSI PHY LPTX 

The DSI protocol engine must not stop TxClkEsc after the turn-around process completes (the 

DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE bit must be kept at 1), because TxClkEsc is also used in 

handling a turn-around request transmitted by a remote slave device (see Section 7.5.6.4.4, Turn-Around 

Request in Receive Mode). 

7.5.6.4.4 Turn-Around Request in Receive Mode 

When the DSI PHY is in receive mode, an LP pattern of 11-10-00-10-00 on DP/DN lines indicates a 

turn-around request from the remote device (see Figure 7-143). 



LP-10 

LP-11 

dss-401

DP/DN 

TXCLKESC 

DIRECTION 



Figure 7-143. Turn-Around Request in Receive Mode 

DSI PHY LPRX detects turnaround request pattern 

(11 - 10 - 00 - 10 - 00) 

2*T LPX



• DSS.DSI_COMPLEXIO_IRQSTATUS ERRCONTENTIONLP0_i_IRQ: ERRCONTENTION0LPDX 

and ERRCONTENTION0LPDY are asserted when the Lane module detects a contention situation 

on lines DX and DY respectively while trying to drive the lines low. Contention is detected only if it 

lasts at least 50ns 

• DSS.DSI_COMPLEXIO_IRQSTATUS ERRCONTENTIONLP1_i_IRQ: ERRCONTENTION1LPDX 

and ERRCONTENTION1LPDY are asserted when the Lane module detects a contention situation 

on lines DX and DY respectively while trying to drive the lines high. Contention is detected only if it 

lasts at least 50ns 

The ULPSACTIVENOT signal goes low which indicates to the protocol that the PHY has entered ULP 

state. When all the ULPSActiveNot signals are low, the DSS.DSI_COMPLEXIO_IRQSTATUS[30] 

ULPSACTIVENOT_ALL0_IRQ event is generated. When all the ULPSActiveNot signals are high, the 

DSS.DSI_COMPLEXIO_IRQSTATUS[31] ULPSACTIVENOT_ALL1_IRQ event is generated. 

When any of the events defined in DSS.DSI_COMPLEXIO_IRQSTATUS register happened, the 

DSS.DSI_IRQSTATUS[10] COMPLEXIO_ERR_IRQ bit is set to 1 at DSI protocol engine level. 

The software must take appropriate action when receiving the interrupt indicating the error from the 

complex I/O. The action can be: 

• Reset of the DSI protocol engine module 

• Reset of the peripheral though reset trigger or directly driving the hardware reset pin of the display 

module 

• Ignore the error 

7.5.7 RFBI Basic Programming Model 

The RFBI programming model must be used for LCD display support only. 

7.5.7.1 DISPC Control Registers 

The following DISPC registers are used in RFBI mode: 

• The STALL mode is selected by setting the DSS.DISPC_CONTROL[11] STALLMODE bit. The 

DSS.DISPC_CONTROL[5] GOLCD bit must not be set to 1, but the display controller configuration 

(DMA engine, pipelines associated to the LCD output,..) must be set before enabling the LCD output 

by setting the DSS.DISPC_CONTROL[0] LCDENABLE bit to 1. 

• To enable the hardware handcheck to avoid underflow, the DSS.DISPC_CONTROL[16] 

FIFOHANDCHECK must be set to 1. The reset value of this bit is 0. The handcheck applies to the 

pipelines connected to the LCD output. It must be disabled before resetting the 

DSS.DISPC_CONTROL[11] STALLMODE bit to 0. The new setting for the FIFO handcheck is used for 


NOTE: The LCD output is disabled at the end of the transfer of the frame. The software must 

reenable the LCD output to generate a new frame by setting the DSS.DISPC_CONTROL[0] 

LCDENABLE to 1. See Figure 7-144. 

7.5.7.2 RFBI Control Registers 

The following registers define the RFBI control registers: 

• DSS.RFBI_CONTROL 

• DSS.RFBI_PIXEL_CNT 

• DSS.RFBI_LINE_NUMBER 

7.5.7.2.1 High Threshold 

The DSS.RFBI_CONTROL[6:5] HIGHTHRESHOLD bit field is used to define the threshold to be used for 

the generation of the DMA request to receive data into the interconnect FIFO (24 x 32 FIFO depth) 

through the address of the register RFBI_DATA. It must be the size of the burst. The supported values are 





4x32, 8x32 and 16x32. The system DMA receives the DMA request and is in charge of providing the 

correct number of bytes. If the DSS.RFBI_CONTROL[7] DISABLE_DMA_REQ bit is reset, the DMA 

request is generated when there is enough room in the interconnect FIFO to accept the full burst. In case 

the RFBI receives writes L4 requests to the RFBI_DATA location when the interconnect FIFO is full, the 

request is not accepted. The RFBI waits for a free entry in the interconnect FIFO to accept the L4 request. 

If the DSS.RFBI_CONTROL[7] DISABLE_DMA_REQ bit is set, the DMA request is not generated. The 

threshold value is ignored. 

NOTE: Software users can access the RFBI_DATA location without using the DMA request and 

without programming the high threshold value (backward mode). 

7.5.7.2.2 Bypass Mode 

Setting the DSS.RFBI_CONTROL[1] BYPASSMODE bit directly outputs the LCD controller output to the 

LCD panel. Resetting this bit directs the MPU module to send commands/parameters and data from the 

input video port FIFO. 

7.5.7.2.3 Enable 

Setting/resetting the DSS.RFBI_CONTROL[0] ENABLE bit enables/disables the RFBI module. The 

hardware resets the enable bit after all of the pixels are sent to the panel. The 

DSS.RFBI_PIXEL_CNT[31:0] PIXELCNT bit field value defines the number of pixels to send to the LCD 

panel. When the transfer is finished, the configuration used can be modified. 

Table 7-71. RFBI Behavior 

RFBI_CONTROL[1] BYPASSMODE RFBI_CONTROL[0] ENABLE bit value RFBI Behavior 

bit value 

0 0 L4 interconnect can write 

command/param/data and read 

data/status from the Remote Frame 

Buffer (RFB). L4 interconnect access can 

only be done to the CSx actually active 

0 1 The DISPC sends pixels to the RFB. 

The stall signal is asserted when the module is disabled. Through the L4 port, pixels can be sent to the 

LCD panel only when the pixel count has reach the value 0x0 

NOTE: The LCD output is disabled at the end of the transfer of the frame. The software must 

reenable the LCD output to generate a new frame by setting the DSS.DISPC_CONTROL[0] 

LCDENABLE to 1. See Figure 7-144. 

7.5.7.2.4 Configuration Selection 

Setting the DSS.RFBI_CONTROL[3:2] CONFIGSELECT bit field selects the configuration number (1 or 0 

if bits are set or reset). The registers associated with the configuration output the data to the LCD panel. 

If both chip-selects are selected, the configuration for the first chip-select is used (except for the polarity of 

the RFBI_CS1 signal defined by the second configuration) and both devices connected to the CS signals 

are driven in parallel. In read mode, if both chip-selects are set, only RFBI_CS0 is asserted to read data 

from the device connected on RFBI_CS0. In write mode with two chip-selects selected, the RFBI can write 

to the two devices simultaneously. 



1749



7.5.7.2.5 ITE Bit 

Set the DSS.RFBI_CONTROL[4] ITE bit to start capturing the data from the display controller. This bit has 

no effect if the trigger mode is set to external. The display controller must be configured in the STALL 

mode to account for the RFBI_DISPC_STALL signal. Setting the trigger mode to external 

(DSS.RFBI_CONFIGi[3:2] TRIGGERMODE bit field set to 0x1 or 0x2) causes the 

DSS.RFBI_CONTROL[4] ITE bit to be ignored. The corresponding chip-select must be selected when this 

bit is set by users. 

The RFBI_DISPC_STALL signal is asserted when at least one of the following cases occur: 

• Default status when no data to capture from the display controller 

• High FIFO threshold reached 

• End of the transfer (number of data to output) 

• Reset of the RFBI module 

• DSS.RFBI_CONTROL[0] ENABLE bit reset to 0x0 

The RFBI_DISPC_STALL signal is deasserted when the DSS.RFBI_CONTROL[0] ENABLE bit is set to 

0x1 and at least one of the following cases occur: 

• Low FIFO threshold reached 

• External TE occurs and the DSS.RFBI_CONFIGi[3:2] TRIGGERMODE bit field is set to 0x1 or 0x2 for 

automatic external trigger (start of the transfer, the FIFO pointers are reset, the FIFO is empty). 

• DSS.RFBI_CONTROL[4] ITE bit set to 0x1 by users (start of the transfer, the FIFO pointers are reset, 

the FIFO is empty). 

7.5.7.2.6 Number of Pixels to Transfer 

Setting the DSS.RFBI_PIXEL_CNT[31:0] PIXELCNT bit field value directs the application to indicate the 

number of pixels to be transferred to the LCD panel. The value can be changed only when the 

DSS.RFBI_CONTROL[0] ENABLE is reset. 

During the transfer, the hardware decrements the register when a pixel is sent to the remote frame buffer. 

When the DSS.RFBI_CONTROL[0] ENABLE bit is set and a new value is written in the 

DSS.RFBI_PIXEL_CNT register when the current value in the register is a non-zero (the remaining 

number of pixels to transfer), the ongoing transfer is aborted. 

From the L4 interconnect side, if the DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT bit field is equal to 0x3 

and the DSS.RFBI_CONFIGi[8:7] L4FORMAT bit field is equal to 0x0, an even number of write accesses 

to the data register must be performed before accessing any other register 

(CMD/PARAM/STATUS/READ). 

When the DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT bit field is 0x3 (2 pixels are sent over 3 cycles), the 

number of pixels to be programmed in the DSS.RFBI_PIXEL_CNT[31:0] PIXELCNT bit field must be a 

multiple of 2. If another CYCLEFORMAT is used, the value for PIXELCNT can be odd or even. This 

constraint is valid for data provided on the L4 interconnect port and from the display controller. 

If the DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT bit field is equal to 0x3, the DSS.RFBI_CONFIGi[8:7] 

L4FORMAT bit field is equal to 0, and back-to-back register write is processed. The following registers 

should be written after the first data: RFBI_CMD, RFBI_PARAM, RFBI_READ, and RFBI_STATUS. The 

whole data transfer must first be performed before being able to write to any other registers (RFBI_CMD, 

RFBI_PARAM, RFBI_READ, and RFBI_STATUS). 

7.5.7.2.7 Programmable Line Number 

When the trigger mode is set to external trigger mode with HSYNC and VSYNC or the TE, hardware 

resets the line counter when the VSYNC occurs and, after a programmable number of lines (the HSYNC 

pulse occurs for every line), the transfer to the LCD panel begins. When the programmable line number is 

0, only the VSYNC pulse indicates the beginning of the transfer in both modes: HSYNC/VSYNC and TE 

(logical OR operation between HSYNC and VSYNC). 

7.5.7.3 RFBI Configuration 

The following registers define the RFBI configuration: 





• DSS.RFBI_SYSCONFIG 

• DSS.RFBI_SYSSTATUS 

• DSS.RFBI_CONFIG0 (configuration 0) and DSS.RFBI_CONFIG1 (configuration 1) 

• DSS.RFBI_VSYNC_WIDTH 

• DSS.RFBI_HSYNC_WIDTH 

The configuration register for one configuration can be accessed only when the configuration is not in use 

(based on the value of the RFBI_CONTROL[3:2] CONFIGSELECT bit field). 

7.5.7.3.1 Parallel Mode 

The DSS.RFBI_CONFIGi[1:0]PARALLELMODE bit field (where i = 0, 1) defines the width of the interface 

(8-, 9-, 12-, or 16-bit parallel). 

7.5.7.3.2 Trigger Mode 

Setting the DSS.RFBI_CONFIG[3:2]TRIGGERMODE bit field configures the trigger on the external TE 

signal (RFBI_TE_VSYNC), or external with VSYNC/HSYNC with the programmable number of HSYNCs to 

begin the transfer in both cases or the internal programmable DSS.RFBI_CONTROL[4] ITE bit. 

7.5.7.3.3 VSYNC Pulse Width (Minimum Value) 

The DSS.RFBI_VSYNC_WIDTH[15:0] MINVSYNCPULSEWIDTH bit field defines the minimum number of 

L4 clock cycles of the VSYNC pulse for detection on VSYNC. It allows differentiation between VSYNC and 

HSYNC, which are ORed on the same signal and is also used in the VSYNC/HSYNC mode on the two 

separate input lines. 

• The VSYNC pulse width must be at least equal to two L4 cycles when HSYNC is not present. 

• The VSYNC pulse width must be at least equal to four L4 cycles when HSYNC is present. 

7.5.7.3.4 HSYNC Pulse Width (Minimum Value) 

The DSS.RFBI_HSYNC_WIDTH[15:0] MINHSYNCPULSEWIDTH bit field defines the minimum number of 

L4 clock cycles of the HSYNC pulse for detection on HSYNC. It allows differentiation between VSYNC 

and HSYNC, which are ORed on the same signal, and is also used in the VSYNC/HSYNC mode on the 

separate two input lines. The HSYNC pulse width must always be at least equal to two L4 cycles to be 

detected. 

7.5.7.3.5 Cycle Format 

Setting the DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT bit field (with i = 0, 1) defines which registers are 

used to format the data in the interconnect FIFO with the appropriate number of bits (starting from the 

LSB) and with the alignment on the interface as follows: 

• DSS.RFBI_DATA_CYCLE_i (if DSS.RFBI_CONFIG[10:9] CYCLEFORMAT bit field = 00) only 

or 

• DSS.RFBI_DATA_CYCLE1_i and DSS.RFBI_DATA_CYCLE2_i (if DSS.RFBI_CONFIG[10:9] 

CYCLEFORMAT bit field = 01) 

or 

• DSS.RFBI_DATA_CYCLE1_i, DSS.RFBI_DATA_CYCLE2_i, and DSS.RFBI_DATA_CYCLE3_i (if 

DSS.RFBI_CONFIG[10:9] CYCLEFORMAT bit field = 10) 

The data from the display controller and from the L4 interconnect are formatted based on the configuration 

of the DSS.RFBI_DATA_CYCLE_i registers. 

7.5.7.3.6 Unused Bits 

Based on the configuration, the undefined bits for each cycle are defined with the previous values of the 

bits at the same position in the previous cycle, 0s, or 1s (the unused bits can be at any position). The 

DSS.RFBI_CONFIGi[12:11] UNUSEDBITS bit field (with i = 0, 1) is used. 



1751



7.5.7.3.7 RFBI Timings 

The timing registers for one configuration can be accessed only when the configuration is not in use 

(based on the value of the DSS.RFBI_CONTROL[3:2] CONFIGSELECT bit field). Granularity is defined 

using the DSS.RFBI_CONFIGi[4] TIMEGRANULARITY bit. This feature allows the extension of 

programmable ranges of timing parameters for the RFBI interface. Refer to Table 7-72 for the bits 

configuration values. 

• Chip-select assertion/deassertion time 

RFBI_A0 setup time to chip-select assertion is assured by the programmable chip-select assertion time 

from the start access time: 

DSS.RFBI_ONOFF_TIMEi[3:0] CSONTIME bit field (with i = 0, 1). 

The chip-select deassertion time from the start access time is programmable: 

DSS.RFBI_ONOFF_TIMEi[9:4] CSOFFTIME bit field (with i = 0, 1) 

CAUTION 

Configuring DSS.RFBI_ONOFF_TIMEi[3:0] CSONTIME = 

DSS.RFBI_ONOFF_TIMEi[9:4] CSOFFTIME = 0 (with i = 0, 1) is not supported 

and must be avoided. This configuration creates contention on the bus and 

progressively damages the LCD panel. 

• Chip-select pulse width 

The total chip-select pulse width is the time when write cycle time or read cycle time has completed 

and is programmable: 

DSS.RFBI_CYCLE_TIMEi[17:12] CSPULSEWIDTH bit field (with i = 0, 1) 

It applies on the read-to-write, write-to-read, read-to-read, and write-to-write access based on: 

– The DSS.RFBI_CYCLE_TIMEi [19] RRENABLE bit: Read-to-read access 

– The DSS.RFBI_CYCLE_TIMEi [20] WWENABLE bit: Write-to-write access 

– The DSS.RFBI_CYCLE_TIMEi [18] RWENABLE bit: Read-to-write access 

– The DSS.RFBI_CYCLE_TIMEi [21] WRENABLE bit: Write-to-read access 

By default, it applies to any access (read-to-read, read-to-write, write-to-read, write-to-write) when 

the chip-select changes. 

• Access time 

The total access time is the time from when A0 becomes valid until data are sampled before 

deasserting the RE signal; access time is programmable: 

DSS.RFBI_CYCLE_TIMEi[27:22] ACCESSTIME bit field (with i = 0, 1) 

When reading the data on the bus, the data are sampled at the end of the access time, which 

occurs before the end of the read off time (DSS.RFBI_ONOFF_TIMEi[29:24] REOFFTIME, with i = 

0, 1). 

• Write enable cycle time 

The total write enable cycle time is the time from when A0 becomes valid until write cycle completion; 

the write enable cycle time is programmable: 

The DSS.RFBI_CYCLE_TIMEi[5:0] WECYCLETIME bit field (with i = 0, 1) 

• Write enable assertion/deassertion time 

The WE assertion delay time from start access time is programmable: 

DSS.RFBI_ONOFF_TIMEi[13:10] WEONTIME bit field (with i = 0, 1) 

The WE deassertion delay time from the start access time is programmable: 

DSS.RFBI_ONOFF_TIMEi[19:14] WEOFFTIME bit field (with i = 0, 1) 

• Read enable cycle 

The total read enable cycle time is the time when A0 becomes valid until read cycle completion; the 

read enable cycle time is programmable: 

The DSS.RFBI_CYCLE_TIMEi[11:6] RECYCLETIME bit field (with i = 0, 1) 

• Read enable assertion/deassertion time 

The RE assertion delay time from the start access time is programmable: 





DSS.RFBI_ONOFF_TIMEi[23:20] REONTIME bit field (with i = 0, 1) 

The RE deassertion delay time from the start access time is programmable: 

DSS.RFBI_ONOFF_TIMEi[29:24] REOFFTIME bit field (with i = 0, 1) 

At cycle time completion (read access or write access) all control signals (RFBI_CSi, RFBI_WR, and 

RFBI_RD, with i = 0, 1) are deasserted regardless of their deassertion time parameter values, if they are 

not deasserted already. 

However, an exception to this forced deassertion exists when a pipelined request to the same chip-select 

or to a different chip-select is pending. Also, a control signal with deassertion time parameters equal to the 

cycle time parameter is not necessarily deasserted when a pipelined request to the same chip-select or 

different chip-select is pending. This prevents any unnecessary glitch transitions. 

If no inactive cycles are required between successive accesses to the same chip-select (the 

DSS.RFBI_CYCLE_TIMEi[17:12] CSPULSEWIDTH bit field = 0, with i = 0, 1), and if assertion time 

parameters associated with the following access equal 0, the asserted control signals (RFBI_CSi, 

RFBI_WR, and RFBI_RD, with i = 0, 1) stay asserted. This is applicable to any read/write-to-read/write 

access combination. 

Table 7-72 summarizes the configurations values for each timing bit. 

Table 7-72. RFBI Timings Configuration 

Configuration bits (1) Granularity (2) 

one two 

DSS.RFBI_ONOFF_TIMEi[3:0] CSONTIME 0 to 15 0 to 30 

DSS.RFBI_ONOFF_TIMEi[9:4] CSOFFTIME 0 to 63 0 to 126 

DSS.RFBI_CYCLE_TIMEi[17:12] CSPULSEWIDTH 0 to 63 0 to 126 

DSS.RFBI_CYCLE_TIMEi[27:22] ACCESSTIME 0 to 63 0 to 126 

DSS.RFBI_CYCLE_TIMEi[5:0] WECYCLETIME 0 to 63 0 to 126 

DSS.RFBI_ONOFF_TIMEi[13:10] WEONTIME 0 to 15 0 to 30 

DSS.RFBI_ONOFF_TIMEi[19:14] WEOFFTIME 0 to 63 0 to 126 

DSS.RFBI_CYCLE_TIMEi[11:6] RECYCLETIME 0 to 63 0 to 126 

DSS.RFBI_ONOFF_TIMEi[23:20] REONTIME 0 to 15 0 to 30 

DSS.RFBI_ONOFF_TIMEi[29:24] REOFFTIME 0 to 63 0 to 126 

(1) Where i = 0 or 1. 

(2) Number of L4Clk cycles. The granularity can be configured using the DSS.RFBI_CONFIGi[4] TIMEGRANULARITY bit. 

7.5.7.3.8 RFBI State-Machine 

Referring to Table 7-39, the signals RFBI_A0, RFBI_RD, and RFBI_WR are asserted/deasserted based 

on the register accessed (DSS.RFBI_CMD, DSS.RFBI_PARAM, DSS.RFBI_DATA, DSS.RFBI_READ, 

and DSS.RFBI_STATUS). When the DSS.RFBI_SYSSTATUS[8] BUSY bit is set by hardware, any access 

to the registers is stalled, except for the RFBI_DATA register. 

The DSS.RFBI_SYSSTATUS[9] BUSYRFBIDATA bit indicates whether there are still pending data in the 

interconnect FIFO associated with the register RFBI_DATA only. 

• Command register 

Write a command at a time by writing in the DSS.RFBI_CMD register. If the previous command is not 

processed, the DSS.RFBI_SYSSTATUS[8] BUSY bit is set by hardware and the access to writing a 

new command is stalled. 

• Parameter register 

Write a parameter at a time by writing in the DSS.RFBI_PARAM register. 

If the previous parameter is not processed, the DSS.RFBI_SYSSTATUS[8] BUSY bit is set by 

hardware and the access to writing a new parameter is stalled. 

• Data register 

Write one or two pixels at a time by writing in the RFBI_DATA register (when 

DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT = 0x3 with i = 0, 1, two pixels must be written 

contiguously, no other access to RFBI registers except DSS.RFBI_DATA is allowed). 



1753



The pixels are formatted based on the specified cycle format. If two pixels are written into the 32-data 

register, the DSS.RFBI_CONFIGi[8:7] L4FORMAT bit field indicates the number of pixels for each L4 

access to the register and the order of the pixels 

If the previous data are not processed, the DSS.RFBI_SYSSTATUS[8] BUSY bit is set by hardware 

and any access for writing new data is stalled. When the DSS.RFBI_SYSSTATUS[8] BUSY bit is reset 

by hardware, the access is not stalled. 

• Read/status register 

Send through the command and parameter registers the correct information to receive data in the data 

or status register. The read data from the LCD panel is initiated by writing into the DSS.RFBI_READ or 

DSS.RFBI_STATUS registers. In this case, the DSS.RFBI_SYSSTATUS[8] BUSY bit is set until the 

data are available in the register. 

When the DSS.RFBI_SYSSTATUS[8] BUSY bit is set by hardware, the read or write access is stalled 

until the register is updated with a new value from the LCD panel. To avoid the stall, the software can 

poll the DSS.RFBI_SYSSTATUS[8] BUSY bit until it is reset by hardware. To receive the data, send 

the appropriate command/parameters. 

7.5.7.3.9 RFBI Configuration Flow Charts 

The RFBI configuration depends on the trigger mode used by the application. The available trigger modes 

are: 

• Internal trigger mode when setting the DSS.RFBI_CONFIGi[3:2] TRIGGERMODE bit field to 0x0 

• External trigger mode: 

– TE external trigger mode when setting the DSS.RFBI_CONFIGi[3:2] TRIGGERMODE bit field to 

0x1 

– HSYNC/VSYNC external trigger mode when setting the DSS.RFBI_CONFIGi[3:2] TRIGGERMODE 

bit field to 0x2 

Figure 7-144 gives an example of how to program and use the RFBI module: 



Start 

Program the RFBI initial configuration 

Enable RFBI output 

Wait FRAMEDONE interrupt 

Internal trigger mode 

used? 

Yes 

No 

Configure the number of pixels to transfer: 

Set DSS.RFBI_PIXEL_CNT[31:0] PIXELCNT bit field 

Enable the display controller module output: 

Set DSS.DISPC_CONTROL[0] LCDENABLE bit to 1 

Enable the RFBI module output to update the remote frame buffer: 

Set DSS.RFBI_CONTROL[0] ENABLE bit to 1 


used? 

Yes 



Figure 7-144. How to Use RFBI 

Program the number of lines where to start transfer: 

Set the DSS.RFBI_LINE_NUMBER register 

No 

Enable internal software trigger 

Set DSS.RFBI_CONTROL[4] ITE bit to 1 

Figure 7-145 details how to configure the RFBI registers: 



dss-192 

1755

Start 

RFBI initial configuration 

Program the display controller to configure the graphics 

(GFX) or video (VIDn) pipeline 

Program the display controller in RFBI mode: 

Set DSS.DISPC_CONTROL[11] RFBIMODE bit to 1 

Select the RFBI data path: 

Set DSS.DISPC_CONTROL[16:15] GPOUT field to 0x1 

Disable the time division multiplexing (TDM): 

Set DSS.DISPC_CONTROL[20] TDMENABLE bit to 0 

Enable RFBI path: 

Set DSS.RFBI_CONTROL[1] BYPASSMODE bit to 0 

Disable the CS and configuration: 

Set DSS.RFBI_CONTROL[3:2] CONFIGSEI.ECT field to 0x0 

Program timings: 

Set DSS RFBI_ONOFF_TIMEi[] bits 

Set DSS RFBI_CYCLE_TIMEi[] bits 

Program signals polarity 

Set DSS.RFBI_CONFIGi[] polarity bits 


used? 

Yes 

Program parallel data widths: 

Output data width: Set DSS.RFBI_CONFIGi[1:0] PARALLELMODE 

Input data width:Set DSS.RFBI_CONFIGi[6:5] DATATYPE 

Number of cycles: Set DSS.RFBI_CONFIGi[10:9] CYCLEFORMAT 

No 

Program data format per cycle: 

Set DSS.RFBI_DATA_CYCLE1_i[ ] bits 

Set DSS.RFBI_DATA_CYCLE2_i[ ] bits (if needed) 

Set DSS.RFBI_DATA_CYCLE3_i[ ] bits (if needed) 

Selet the CS and configuration: 

Set DSS.RFBI_CONTROL[3:2] CONFIGSELECT bit 

End 

RFBI initial configuration 



Figure 7-145. RFBI Initial Configuration 

TE External trigger mode 

used? 

This enables modifying 

the configuration registers 

Yes 

No 

Program TE polarity 

Set DSS.RFBI_CONFIGi[20] TE_VSYNC_POLARITY 

Program minimum pulse width: 

Set DSS.RFBI_VSYNC_WIDTH[15:0] MINVSYNCPULSEWIDTH 

Set DSS.RFBI_HSYNC_WIDTH[15:0] MINHSYNCPULSEWIDTH 

Figure 7-146 describes how to enable the RFBI module. 

Program HSYNC and VSYNC polarity 

VSYNC: Set DSS.RFBI_CONFIGi[20] TE_VSYNC_POLARITY 

HSYNC: Set DSS.RFBI_CONFIGi[21] HSYNCPOLARITY 

Select previously programmed 

CS configuration 



dss-193

Start 

RFBI out enable 

Enable the graphics or video pipeline: 

Set DSS.DISPC_XXX_ATTRIBUTES[0] ENABLE bit to 1 (XXX=GFX or VIDn) 

Enable the display controller output: 

Set DSS.DISPC_CONTROL[0] LCDENABLE bit to1 


used? 

Yes 

No 

Disable internal software trigger 

Set DSS.RFBI_CONTROL[4] ITE bit to 0 

Configure the number of pixels to tranfer: 

Set DSS.RFBI_PIXEL_CNT[31:0] PIXELCNT bit field 

Enable the RFBI module output to update the remote frame buffer: 

Set DSS.RFBI_CONTROL[0] ENABLE bit to 1 


used? 

Yes 

Program the nuber of lines where to start transfer: 

Set the DSS.RFBI_LINE_NUMBER register 

No 

Enable internal software trigger 

Set DSS.RFBI _CONTROL[4] ITE bit to 1 

End 

RFBI output enable 



Figure 7-146. RFBI Output Enable 

7.5.8 Video Encoder Basic Programming Model 

7.5.8.1 Video Encoder Software Reset 

By setting the DSS.VENC_F_CONTROL[8] RESET bit to 1, the video encoder is reset. This bit is 

automatically cleared by hardware when the reset is done. 

NOTE: Before changing the standard (NTSC or PAL) and all the related registers, a software reset 

is required to properly initialize the VENC module. 

7.5.8.2 Video DAC Stage Settings 

The video output format can be either: 

• one composite video (CVBS) output signal with video DAC1 or 



dss-324 

1757



• two separated luma/chroma output signals with both video DAC1(luma analog signal) and DAC2 

(chroma analog signal) 

Selection is performed with DSS.DSS_CONTROL[6] VENC_OUT_SEL bit: 

• When VENC_OUT_SEL bit is set to 0 (reset value), video DAC1 is selected for composite video 

(CVBS) signal 

• When VENC_OUT_SEL bit is set to 1, video DAC1 is selected for luma signal 

One of the first VENC settings is to enable the outputs of the video DACs. This setting depends on the 

video output format: 

• CVBS video output format: Enable video DAC1 composite output by setting the 

DSS.VENC_OUTPUT_CONTROL[1] COMPOSITE_ENABLE bit to 1 

• Separated luma/chroma output format: Enable video DAC1 luma output by setting the 

DSS.VENC_OUTPUT_CONTROL[0] LUMA_ENABLE bit to 1 and enable video DAC2 chroma 

output by setting the DSS.VENC_OUTPUT_CONTROL[2] CHROMA_ENABLE bit to 1 

Table 7-73 shows different configurations for the analog TV output, along with the respective values to 

be set in the dedicated registers inside the device system control module. 

Table 7-73. Analog TV Output Modes 

Analog TV output modes 

Control Register Composite Composite S-Video DC-coupled Bypass mode, dual channels 

DC-coupled mode, AC-coupled mode, mode, high full scale 

high full scale low full scale 

CONTROL.CONTROL_ 0: Buffer Mode 0: Buffer mode 0: Buffer mode 1: Bypass mode 

DEVCONF1[18] 

TVOUTBYPASS 

CONTROL.CONTROL_ 0: DC-coupling 1: AC-coupling 0: DC-coupling 0: DC-coupling 

DEVCONF1[11] 

TVACEN 

AVDAC1 

CONTROL.CONTROL_ 0: Don't care 0: Don't care 0: Don't care 0: Don't care 

AVDAC1 [20] 

AVDAC1_COMP_EN 

CONTROL.CONTROL_ 0: Single channel 0: Single channel 1: Dual channel 1: Dual channel 

AVDAC1 [19] 


CONTROL.CONTROL_ 0: Composite 0: Composite 0: Luma 0: Luma 

AVDAC1 [18] 


CONTROL.CONTROL_ 0: Full scale (1.3V) 1: Full scale (0.88V) 0: Full scale (1.3V) 0: Full scale (1.3V) 

AVDAC1 [17] 


CONTROL.CONTROL_ 0: External current 0: External current 0: External current 0: External current reference 

AVDAC1 [16] reference reference reference 


AVDAC2 

CONTROL.CONTROL_ 0: Don't care 0: Don't care 0: Don't care 0: Don't care 

AVDAC2 [20] 


CONTROL.CONTROL_ 0: Single channel 0: Single channel 1: Dual channel 1: Dual channel 

AVDAC2 [19] 


CONTROL.CONTROL_ 1: Chroma 1: Chroma 1: Chroma 1: Chroma 

AVDAC2 [18] 


CONTROL.CONTROL_ 0: Full scale (1.3V) 0: Full scale (1.3V) 0: Full scale (1.3V) 0: Full scale (1.3V) 

AVDAC2 [17] 


CONTROL.CONTROL_ 0: External current 0: External current 0: External current 0: External current reference 

AVDAC2 [16] reference reference reference 






7.5.8.3 Video Encoder Programming Sequence 

1. Set the DSS.VENC_F_CONTROL[8] RESET bit to 1 to perform a software reset of the VENC module. 

2. Before any configuration change, save the DSS.DISPC_IRQENABLE register value (DSS interrupts 

context), and then disable the display subsystem interrupts by setting the DSS.DISPC_IRQENABLE 

register to 0x0000. 

3. Configure the video encoder registers as described in Table 7-74, depending on the video standard 

used (PAL or NTSC). The DSS.VENC_F_CONTROL and DSS.VENC_SYNC_CTRL registers must be 

the last ones to be changed by software. 

4. Set the DSS.DISPC_CONTROL[6] GODIGITAL bit and the DSS.DISPC_CONTROL[1] 

DIGITALENABLE bit to 1. 

5. Wait for the first VSYNC pulse signal. 

6. Clear the SYNCLOSTDIGITAL interrupt by setting the DSS.DISPC_IRQSTATUS[15] 


7. Set the DSS.DISPC_IRQENABLE register to the value saved in step 2 (restore the DSS interrupts 

context). 

7.5.8.4 Video Encoder Register Settings 

For video encoder programming, see Table 7-74. This table lists the register values to use in standard 

applications. These values are validated programming values only for the TV display support (NTSC 601 

and PAL 601 standards). 

Table 7-74. Video Encoder Register Programming Values 

Register Name NTSC 601 PAL 601 

VENC_F_CONTROL 0x00000000 0x00000000 

VENC_VIDOUT_CTRL 0x00000001 0x00000001 

VENC_SYNC_CTRL 0x00008040 0x00000040 

VENC_LLEN 0x00000359 0x0000035F 

VENC_FLENS 0x0000020C 0x00000270 

VENC_HFLTR_CTRL 0x00000000 0x00000000 

VENC_CC_CARR_WSS_CARR 0x043F2631 0x2F7225ED 

VENC_C_PHASE 0x00000000 0x00000000 

VENC_GAIN_U 0x00000102 0x00000111 

VENC_GAIN_V 0x0000016C 0x00000181 

VENC_GAIN_Y 0x0000012F 0x00000140 

VENC_BLACK_LEVEL 0x00000043 0x0000003B 

VENC_BLANK_LEVEL 0x00000038 0x0000003B 

VENC_X_COLOR 0x00000007 0x00000007 

VENC_M_CONTROL 0x00000001 0x00000002 

VENC_BSTAMP_WSS_DATA 0x00000038 0x0000003F 

VENC_S_CARR 0x21F07C1F 0x2A098ACB 

VENC_LINE21 0x00000000 0x00000000 

VENC_LN_SEL 0x01310011 0x01290015 

VENC_L21_WC_CTL 0x0000F003 0x0000F603 

VENC_HTRIGGER_VTRIGGER 0x00000000 0x00000000 

VENC_SAVID_EAVID 0x069300F4 0x06A70108 

VENC_FLEN_FAL 0x0016020C 0x00180270 

VENC_LAL_PHASE_RESET 0x00060107 0x00040135 

VENC_HS_INT_START_STOP_X 0x008E0350 0x00880358 

VENC_HS_EXT_START_STOP_X 0x000F0359 0x000F035F 

VENC_VS_INT_START_X 0x01A00000 0x01A70000 

VENC_VS_INT_STOP_X_VS_INT_START_Y 0x020701A0 0x000001A7 



1759



Table 7-74. Video Encoder Register Programming Values (continued) 

Register Name NTSC 601 PAL 601 

VENC_VS_INT_STOP_Y_VS_EXT_START_X 0x01AC0024 0x01AF0000 

VENC_VS_EXT_STOP_X_VS_EXT_START_Y 0x020D01AC 0x000101AF 

VENC_VS_EXT_STOP_Y 0x00000006 0x00000025 

VENC_AVID_START_STOP_X 0x03480078 0x03530083 

VENC_AVID_START_STOP_Y 0x02060024 0x026C002E 

VENC_FID_INT_START_X_FID_INT_START_Y 0x0001008A 0x0001008A 

VENC_FID_INT_OFFSET_Y_FID_EXT_START_ 0x01AC0106 0x002E0138 

X 

VENC_FID_EXT_START_Y_FID_EXT_OFFSET_ 0x01060006 0x01380001 

Y 

VENC_TVDETGP_INT_START_STOP_X 0x00140001 0x00140001 

VENC_TVDETGP_INT_START_STOP_Y 0x00010001 0x00010001 

VENC_GEN_CTRL 0x00F90000 0x00FF0000 

VENC_OUTPUT_CONTROL 0x0000000A (composite video CVBS) 0x0000000A (composite video CVBS) 

0x0000000D (split video S-video) 0x0000000D (split video S-video) 

VENC_OUTPUT_TEST 0x00000000 0x00000000 

NOTE: The following display controller registers must be programmed to the NTSC 601 video 

standard: 

DSS.DISPC_SIZE_DIG[10:0] PPL = 720 - 1 = 719 = 0x2CF 

DSS.DISPC_SIZE_DIG[26:16] LPP = (482/2) - 1 = 240 = 0xF0 

DSS.DISPC_GFX_BA0 or DSS.DISPC_VIDn_BA0 = Base address of even bit field data 

DSS.DISPC_GFX_BA1 or DSS.DISPC_VIDn_BA1 = Base address of odd bit field data 



-1 

Z Line Buffer 

-1 

Z Line Buffer 

-1 

Z Line Buffer 

Pin(n-1) 

Pin(n) 

Pin(n+1) 

1 

( ) = ∑ ( Φ) 

( ) >> 7 

 

For the 3-tap vertical up/downsampling the equation is (with the example of R component): 

i 


i = −1 

dss-E067 


www.ti.com Display Subsystem Use Cases and Tips 

7.6 Display Subsystem Use Cases and Tips 

This section gives some generic use cases and tips for setting the modules of the display subsystem. 

7.6.1 How to Configure the Scaling Unit in the DISPC Module 

This section describes the scaling capability of the display controller (DISPC). The scaling unit is a part of 

the video pipeline is used when transferring pixels from the system memory (SDRAM or on-chip SRAM) to 

the LCD panel or the TV set. The scaling unit consists of two scaling blocks: The vertical scaling block 

followed by the horizontal scaling block. The input pixel format is RGB24. In case the pixel format in 

system memory is not RGB, the color space conversion unit in front of the scaling unit converts the YUV 

pixels into RGB pixels. The two scaling units are independent: Neither of them, only one, or both can be 

used simultaneously 

7.6.1.1 Filtering 

The scaling is used to down-scale, up-scale, or process the image while keeping the same size. It is 

applied independently horizontally and vertically. The same filtering applies for each color component (R, 

G, or B). 

7.6.1.1.1 Vertical Filtering 

The vertical filtering unit is based on a poly-phase rotation architecture with eight phases and three taps. 

That means that 24 coefficients are programmable 

The vertical 3-tap filtering macro architecture is shown in Figure 7-147. 

Figure 7-147. Vertical Filtering Macro Architecture (Three Taps) 

C -1 

C 0 

C 1 

Pout(n') 



dss-112 

(14) 

1761

Pin(n-2) Pin(n-1) Pin(n) Pin(n+1) Pin(n+2) 

Z -1 

Z -1 

C 22 C -1 C 0 C 1 C 00 

i −2 

Pout(n') 

2 

( ) = ∑ ( Φ) 

( + ) 7 

i 

For the 5-tap vertical up/downsampling the equation is (with the example of R component): 


dss-E066 


Display Subsystem Use Cases and Tips www.ti.com 

Legend: 


Ci():Vertical FIR coefficients 

Rin: R component input 

The line (n+1) is older than line (n). 


picture must be a multiple of 2 pixels and more than 5 pixels. This leads to the following 

register configuration: 



The programmable three coefficients of the poly-phase filters are signed 8-bit values (except for the 

central coefficient C 0(), which is unsigned). 

The vertical filtering unit can be configured to support five taps. 

The vertical 5-tap filtering macro architecture is shown in Figure 7-148. 

Legend: 

Figure 7-148. Vertical Filtering Macro Architecture (Five Taps) 


Ci():Vertical FIR coefficients with C +2()=C 00() and C -2()=C 22() 



The programmable five coefficients of the poly-phase filters are signed 8-bit values (except for the central 

coefficient C0(), which is unsigned). 

In case of three taps, the memory lines are merged into three lines instead of six lines (one line is used as 

a cache line). 

The first line is duplicated to fill up the two first lines (3-tap configuration) and the three first lines (5-tap 

configuration). 


Z -1 


Z -1 

dss-113 

(15)

Pin(n-2) Pin(n-1) Pin(n) Pin(n+1) Pin(n+2) 

Z -1 

Z -1 

C -2 C -1 C 0 C 1 C 2 

i −3 

Pout(n') 

3 

( ) = ∑ ( Φ) 

( + ) 7 

i 

For the 5-tap horizontal up/downsampling, the equation is (with the example of R component): 


dss-E115 



The last line is duplicated if the scaling logic requires loading of more lines and the last line has been 

reached 

7.6.1.1.2 Horizontal Filtering 

The horizontal filtering unit is based on a poly-phase rotation architecture with eight phases and five taps. 

That means that 40 coefficients are programmable. 

The horizontal filtering macro architecture is shown in Figure 7-149. 

Legend: 

Figure 7-149. Horizontal Filtering Macro Architecture (Five Taps) 


Ci():Vertical FIR coefficients 



To horizontally and vertically filter the video layer, the phase is calculated separately. The programmable 

coefficients of the poly-phase filters are signed 8-bit values (except for the central coefficient C 0(), which is 

unsigned). 

The first pixel is duplicated to fill up the three first pixel-buffers (5-tap configuration). The last pixel is 

duplicated if the scaling logic requires loading of more pixels and the last pixel has been reached 

7.6.1.2 Scaling Algorithms 

The up/downsampling finite state machines (FSM) below are detailed in this section. 

Figure 7-150 presents the vertical up/downsampling FSM. 


Z -1 


Z -1 

dss-114 

(16) 

1763

WAIT 

4 

5 

INIT 

Load/duplicate 

line(s) 

Phase 

calculation 

Load 

coefficients 

Number of 

line(s) to load 

FIR 

calculation 

Accumulator 

calculation 

1 

2 

3 



Figure 7-150. Vertical Up-/Down-Sampling Algorithm 

1: New pixel on the same line 

2: New pixel on following line (no line to load) 

3: New pixel on following line (line[s] to load) 

4: End of frame 

5: Restart of a new frame 

INIT 

Phase 

calculation 

Number of 


FIR 

calculation 

Accumulator 

calculation 

Figure 7-151 presents the horizontal up/downsampling FSM. 

Initialisation of buffer with duplication, 

accu value reset with register value 

based on the field polarity if present 

Phase = accu[9:7] 

Number of element(s) = 

((accu + 512 + inc) >> 10) - 

((accu + 512) >> 10) 

 

 

( ) ( ) * ( ) 

 

 

7 

 

 

i p 

R o u t n C i R in n i 

i p 

Accu = accu + inc 



dss-116

4 

WAIT 

3 

INIT 

Load/duplicate 

pixel(s) 

Phase 

calculation 

Load 

coefficients 

Number of 

pixel(s) to load 

FIR 

calculation 

Accumulator 

calculation 

1 

2 



7.6.1.3 Scaling Settings 

NOTE: 

7.6.1.3.1 Register List 

Figure 7-151. Horizontal Up-/Down-Sampling Algorithm 

1: New pixel (no pixel to load) 

2: New pixel (pixel(s) to load) 

3: End of line 

4: Restart of a line 

INIT 

Phase 

calculation 

Number of 


FIR 

calculation 

Accumulator 

calculation 

Initialization of buffer with duplication, 

accu value reset with register value 

based on the field polarity if present 

Phase = accu[9:7] 

Number of element(s) = 

((accu + 512 + inc) >> 10) - 

((accu + 512) >> 10) 

 

 

( ) ( ) * ( ) 

 

 

7 

 

 

i p 

R o u t n C i R in n i 

i p 

Accu = accu + inc 

• In this section, the screen word refers to LCD panel or TV set. 

• n indicates pipeline 0 or 1 because there are two video pipelines in the DISPC. 

The following registers define the scaling registers for the video layer n configuration: 

• DSS.DISPC_VIDn_BAj 


• DSS.DISPC_VIDn_FIR 

• DSS.DISPC_VIDn_ACCUl 

• DSS.DISPC_VIDn_FIR_COEF_Hi 

• DSS.DISPC_VIDn_FIR_COEF_HVi 

• DSS.DISPC_VIDn_FIR_COEF_Vi 

Table 7-75 lists the registers for programming the vertical FIR coefficients (3-tap configuration). 

Table 7-75. Vertical FIR Coefficients Corresponding 

Table (3-Tap Configuration) 

C X() VidFIRVC X() 

C -1() VidFIRVC 2() 

C 0() VidFIRVC 1() 



dss-117 

1765




Table (3-Tap Configuration) (continued) 



The corresponding registers for programming the vertical FIR coefficients (3-tap configuration) are: 

• VidFIRVC 2() = DSS.DISPC_VIDn_FIR_COEF_HVi[31:24] VIDFIRVC2 



Table 7-76 lists the registers for programming the vertical FIR coefficients (5-tap configuration). 





C -1() VidFIRVC 2() 





• VidFIRVC 22() = DSS.DISPC_VIDn_FIR_COEF_Vi[15:8] VIDFIRVC22 




• VidFIRVC 00() = DSS.DISPC_VIDn_FIR_COEF_Vi[7:0] VIDFIRVC00 

Table 7-77 lists the registers for programming the horizontal FIR coefficients (5-tap configuration). 

Table 7-77. Horizontal FIR Coefficients Corresponding 


C X() VidFIRHC X() 

C -2() VidFIRHC 4() 

C -1() VidFIRHC 3() 

C 0() VidFIRHC 2() 




• VidFIRHC 4() = DSS.DISPC_VIDn_FIR_COEF_HVi[7:0] VIDFIRHC4 

• VidFIRHC 3() = DSS.DISPC_VIDn_FIR_COEF_Hi[31:24] VIDFIRHC3 




7.6.1.3.2 Enabling 

The video pipeline #n is enabled/disabled by setting/resetting the 

DSS.DISPC_VIDn_ATTRIBUTES[0].VIDENABLE bit. While the video pipeline is enabled/disabled, the 

video layer is visible/not visible on the screen (LCD panel or TV set). 

The video up/downsampling block for the video pipeline #n is programmed by setting the 

DSS.DISPC_VIDn_ATTRIBUTES[6:5] VIDRESIZEENABLE bit field: 



VIDFIRVINC[11:0] = 1024 x VIDORGSIZEY[10:0] 

The following register bit fields define the increment value of the video up/downsampling block for video 

pipeline n: 

• Vertical up/downsampling increment value (DSS.DISPC_VIDn_FIR[27:16] VIDFIRVINC bit field, with n 

= 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the 


VIDSIZEY[10:0] 

dss-E118 

(17) 

VIDFIRHINC[11:0] = 1024 x VIDORGSIZEX[10:0] 

VIDSIZEX[10:0] 

dss-E119 



• When the VIDRESIZEENABLE[1] bit is set to 1, the video vertical up/downsampling block is enabled. 

When set to 0, the vertical resize processing is disabled. 

• When the VIDRESIZEENABLE[0] bit is set to 1, the video horizontal up/downsampling block is 

enabled. When set to 0, the horizontal resize processing is disabled. 

• When the VIDRESIZEENABLE[1:0] is set to 0x3, both horizontal and vertical resize processing are 

enabled. 

NOTE: 

7.6.1.3.3 Factor 

NOTE: 

• Set a valid configuration before enabling the video up/downsampling block. 

• Vertical and horizontal downsampling are limited to a 0.25 resize factor. When 

processing a down-scaling with a vertical factor between 0.5 and 0.25, a 5-tap filter 

configuration must be used. See Section 7.6.1.3.5 for more information concerning the 

filter coefficients. 

• If the VIDFIRVINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If 

VIDSIZEY[10:0] equals 0x1, VIDSIZEY[10:0] is replaced by 0x2 in the previous 

equation. 

• The VIDORGSIZEY[10:0] and VIDSIZEY[10:0] bit field values must be programmed with 


• Horizontal up/downsampling increment value (the DSS.DISPC_VIDn_FIR[11:0] VIDFIRHINC bit field, 

with n = 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using 

the following equation: 

NOTE: 

7.6.1.3.4 Initial Phase 

• If the VIDFIRHINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If 

VIDSIZEX[10:0] equals 1, VIDSIZEX[10:0] is replaced by 2 in the previous equation. 

• The VIDORGSIZEX[10:0] and VIDSIZEX[10:0] bit field values must be programmed with 


• Vertical up/downsampling accumulator value DSS.DISPC_VIDn_ACCUl[25:16] VIDVERTICALACCU 

bit fields 

The unsigned integer value range is [0:1023]. The accumulator value indicates on which phase the 

vertical filtering starts. The value 0 indicates that the phase 0 is the first phase used by the hardware to 

generate the first data. 

• Vertical up/downsampling accumulator value DSS.DISPC_VIDn_ACCUl[9:0] VIDHORIZONTALACCU 

bit fields 

The unsigned integer value range is [0:1023]. The accumulator value indicates on which phase the 

horizontal filtering starts. The value 0 indicates that the phase 0 is the first phase used by the hardware 



(18) 

1767



to generate the first data 

Table 7-78 lists the vertical/horizontal accumulator values and phases 

Table 7-78. Vertical/Horizontal Accumulator Phase 

Accumulator Value Phases 

0 0 

128 1 

256 2 

384 3 

512 4 

640 5 

768 6 

896 7 

NOTE: For LCD output, the initial phase is always 0 (horizontal and vertical.) For TV output, the 

vertical phases (odd and even) can be nonzero values. 

7.6.1.3.5 Coefficients 

• Vertical up/downsampling coefficients (DSS.DISPC_VIDn_FIR_COEF_HVi and 

DSS.DISPC_VIDn_FIR_COEF_V) 

The 3-tap vertical up/downsampling coefficients are defined in DSS.DISPC_VIDn_FIR_COEF_HVi 

registers. There are eight registers for the eight phases with three coefficients for each of them so a 

total of 24 programmable coefficients for the vertical up/downsampling block. Each register contains 

two 8-bit signed coefficients and one 8-bit unsigned coefficient (central one). 

In addition, there are 2-tap vertical up/downsampling coefficients defined in 

DSS.DISPC_VIDn_FIR_COEF_Vi registers. There are eight registers for the eight phases with two 

coefficients for each of them so a total of 16 programmable coefficients for the vertical 

up/downsampling block used in addition of the 3-tap registers defined above. Each register contains 

two 8-bit signed coefficients (C 22() and C 00()). 

In case of 5-tap configuration, both sets of registers, DSS.DISPC_VIDn_FIR_COEF_HVi and 

DSS.DISPC_VIDn_FIR_COEF_V, are used. In case of 3-tap configuration, only one set of registers, 

DSS.DISPC_VIDn_FIR_COEF_HV, is used. 

• Horizontal up/downsampling coefficients (DSS.DISPC_VIDn_FIR_COEF_Hi and 

DSS.DISPC_VIDn_FIR_COEF_HV) 

The 5-tap horizontal up/downsampling coefficients are defined in DSS.DISPC_VIDn_FIR_COEF_Hi 

and DSS.DISPC_VIDn_FIR_COEF_HVi registers. There are eight registers for the eight phases with 

five coefficients for each register, for a total of 40 programmable coefficients for the horizontal 

up/downsampling block. 

Each DSS.DISPC_VIDn_FIR_COEF_Hi register contains three 8-bit signed coefficients and one 8-bit 

unsigned coefficient (central one), and each DSS.DISPC_VIDn_FIR_COEF_HVi contains one 8-bit 

signed coefficient. 

Table 7-79 through Table 7-84 give the programmable coefficients for the FIR up/downsampling filters 

(Max-Fauque-Berthier method). 

7.6.1.3.5.1 Up-Sampling 

Table 7-79 gives the 24 coefficients to program the vertical upsampling (3-tap configuration). 

Table 7-79. Up-Sampling Vertical Filter Coefficients (Three Taps) 

Phases VidFIRVC 2() VidFIRVC 1() VidFIRVC 0() 

0 0 128 0 

1 3 123 2 





Table 7-79. Up-Sampling Vertical Filter Coefficients (Three Taps) (continued) 


2 12 111 5 

3 32 89 7 

4 0 64 64 

5 7 89 32 

6 5 111 12 

7 2 123 3 

Table 7-80 gives the 40 coefficients to program the vertical upsampling (5-tap configuration). 

Table 7-80. Up-Sampling Vertical Filter Coefficients (Five Taps) 

Phases VidFIRVC 22() VidFIRVC 2() VidFIRVC 1() VidFIRVC 0() VidFIRVC 00() 

0 0 0 128 0 0 

1 -1 13 124 -8 0 

2 -2 30 112 -11 -1 

3 -5 51 95 -11 -2 

4 0 -9 73 73 -9 

5 -2 -11 95 51 -5 

6 -1 -11 112 30 -2 

7 0 -8 124 13 -1 

Table 7-81 gives the 40 coefficients to program the horizontal upsampling (5-tap configuration). 

Table 7-81. Up-Sampling Horizontal Filter Coefficients (Five Taps) 

Phases VidFIRHC 4() VidFIRHC 3( VidFIRHC 2() VidFIRHC 1() VidFIRHC 0() 

) 

0 0 0 128 0 0 

1 -1 13 124 -8 0 

2 -2 30 112 -11 -1 

3 -5 51 95 -11 -2 

4 0 -9 73 73 -9 

5 -2 -11 95 51 -5 

6 -1 -11 112 30 -2 

7 0 -8 124 13 -1 

The upsampling coefficients register configuration (vertical three taps and horizontal five taps) is the 

following: 

• DSS.DISPC_VIDn_FIR_COEF_H0 = 0x00800000 

• DSS.DISPC_VIDn_FIR_COEF_HV0 = 0x00800000 

• DSS.DISPC_VIDn_FIR_COEF_H1 = 0x0D7CF800 

• DSS.DISPC_VIDn_FIR_COEF_HV1 = 0x037B02FF 

• DSS.DISPC_VIDn_FIR_COEF_H2 = 0x1E70F5FF 

• DSS.DISPC_VIDn_FIR_COEF_HV2 = 0x0C6F05FE 

• DSS.DISPC_VIDn_FIR_COEF_H3 = 0x335FF5FE 

• DSS.DISPC_VIDn_FIR_COEF_HV3 = 0x205907FB 

• DSS.DISPC_VIDn_FIR_COEF_H4 = 0xF74949F7 


• DSS.DISPC_VIDn_FIR_COEF_H5 = 0xF55F33FB 

• DSS.DISPC_VIDn_FIR_COEF_HV5 = 0x075920FE 

• DSS.DISPC_VIDn_FIR_COEF_H6 = 0xF5701EFE 



1769



• DSS.DISPC_VIDn_FIR_COEF_HV6 = 0x056F0CFF 

• DSS.DISPC_VIDn_FIR_COEF_H7 = 0xF87C0DFF 

• DSS.DISPC_VIDn_FIR_COEF_HV7 = 0x027B0300 

NOTE: In this case, the DSS.DISPC_VIDn_FIR_COEF_Vi registers are not used. 

The upsampling coefficients register configuration (both vertical and horizontal five taps) is the following: 



• DSS.DISPC_VIDn_FIR_COEF_V0 = 0x00000000 

• DSS.DISPC_VIDn_FIR_COEF_H1 = 0x0D7CF800 

• DSS.DISPC_VIDn_FIR_COEF_HV1 = 0x0D7CF8FF 

• DSS.DISPC_VIDn_FIR_COEF_V1 = 0x0000FF00 

• DSS.DISPC_VIDn_FIR_COEF_H2 = 0x1E70F5FF 

• DSS.DISPC_VIDn_FIR_COEF_HV2 = 0x1E70F5FE 

• DSS.DISPC_VIDn_FIR_COEF_V2 = 0x0000FEFF 

• DSS.DISPC_VIDn_FIR_COEF_H3 = 0x335FF5FE 

• DSS.DISPC_VIDn_FIR_COEF_HV3 = 0x335FF5FB 

• DSS.DISPC_VIDn_FIR_COEF_V3 = 0x0000FBFE 

• DSS.DISPC_VIDn_FIR_COEF_H4 = 0xF74949F7 

• DSS.DISPC_VIDn_FIR_COEF_HV4 = 0xF7404000 

• DSS.DISPC_VIDn_FIR_COEF_V04 = 0x000000F7 

• DSS.DISPC_VIDn_FIR_COEF_H5 = 0xF55F33FB 

• DSS.DISPC_VIDn_FIR_COEF_HV5 = 0xF55F33FE 

• DSS.DISPC_VIDn_FIR_COEF_V5 = 0x0000FEFB 

• DSS.DISPC_VIDn_FIR_COEF_H6 = 0xF5701EFE 

• DSS.DISPC_VIDn_FIR_COEF_HV6 = 0xF5701EFF 

• DSS.DISPC_VIDn_FIR_COEF_V6 = 0x0000FFFE 

• DSS.DISPC_VIDn_FIR_COEF_H7 = 0xF87C0DFF 

• DSS.DISPC_VIDn_FIR_COEF_HV7 = 0xF87C0D00 

• DSS.DISPC_VIDn_FIR_COEF_V7 = 0x000000FF 

7.6.1.3.5.2 Down-Sampling 

Table 7-82 gives the 24 coefficients to program the vertical downsampling (3-tap configuration). 

Table 7-82. Down-Sampling Vertical Filter Coefficients (Three Taps) 


0 36 56 36 

1 40 57 31 

2 45 56 27 

3 50 55 23 

4 18 55 55 

5 23 55 50 

6 27 56 45 

7 31 57 40 

Table 7-83 gives the 40 coefficients to program the vertical downsampling (5-tap configuration). 





Table 7-83. Down-Sampling Vertical Filter Coefficients (Five Taps) 

Phases VidFIRVC 22() VidFIRVC 2() VidFIRVC 1() VidFIRVC 0() VidFIRVC 00() 

0 0 36 56 36 0 

1 4 40 55 31 -2 

2 8 44 54 27 -5 

3 -12 48 53 22 -7 

4 -9 17 52 51 17 

5 -7 22 53 48 12 

6 -5 27 54 44 8 

7 -2 31 55 40 4 

Table 7-84 gives the 40 coefficients to program the horizontal downsampling (5-tap configuration). 

Table 7-84. Down-Sampling Horizontal Filter Coefficients (Five Taps) 

Phases VidFIRHC 4() VidFIRHC 3( VidFIRHC 2() VidFIRHC 1() VidFIRHC 0() 

) 

0 0 36 56 36 0 

1 4 40 55 31 -2 

2 8 44 54 27 -5 

3 -12 48 53 22 -7 

4 -9 17 52 51 17 

5 -7 22 53 48 12 

6 -5 27 54 44 8 

7 -2 31 55 40 4 

The downsampling coefficients register configuration (vertical three taps and horizontal five taps) is the 

following: 



• DSS.DISPC_VIDn_FIR_COEF_H1 = 0x28371FFE 

• DSS.DISPC_VIDn_FIR_COEF_HV1 = 0x28391F04 

• DSS.DISPC_VIDn_FIR_COEF_H2 = 0x2C361BFB 

• DSS.DISPC_VIDn_FIR_COEF_HV2 = 0x2D381B08 

• DSS.DISPC_VIDn_FIR_COEF_H3 = 0x303516F9 

• DSS.DISPC_VIDn_FIR_COEF_HV3 = 0x3237170C 



• DSS.DISPC_VIDn_FIR_COEF_H5 = 0x1635300C 


• DSS.DISPC_VIDn_FIR_COEF_H6 = 0x1B362C08 

• DSS.DISPC_VIDn_FIR_COEF_HV6 = 0x1B382DFB 


• DSS.DISPC_VIDn_FIR_COEF_HV7 = 0x1F3928FE 

NOTE: 

• In this case, the DSS.DISPC_VIDn_FIR_COEF_Vi registers are not used. 

• In this case, the downsampling factor must be higher than 1/2. 

The downsampling coefficients register configuration (both the vertical and the horizontal five taps) is the 

following: 





1771



• DSS.DISPC_VIDn_FIR_COEF_V0 = 0x00000000 

• DSS.DISPC_VIDn_FIR_COEF_H1 = 0x28371FFE 


• DSS.DISPC_VIDn_FIR_COEF_V1 = 0x000004FE 

• DSS.DISPC_VIDn_FIR_COEF_H2 = 0x2C361BFB 

• DSS.DISPC_VIDn_FIR_COEF_HV2 = 0x2C361B08 

• DSS.DISPC_VIDn_FIR_COEF_V2 = 0x000008FB 


• DSS.DISPC_VIDn_FIR_COEF_HV3 = 0x3035160C 

• DSS.DISPC_VIDn_FIR_COEF_V3 = 0x00000CF9 



• DSS.DISPC_VIDn_FIR_COEF_V4 = 0x0000F711 

• DSS.DISPC_VIDn_FIR_COEF_H5 = 0x1635300C 


• DSS.DISPC_VIDn_FIR_COEF_V5 = 0x0000F90C 

• DSS.DISPC_VIDn_FIR_COEF_H6 = 0x1B362C08 

• DSS.DISPC_VIDn_FIR_COEF_HV6 = 0x1B362CFB 

• DSS.DISPC_VIDn_FIR_COEF_V6 = 0x0000FB08 


• DSS.DISPC_VIDn_FIR_COEF_HV7 = 0x1F3728FE 

• DSS.DISPC_VIDn_FIR_COEF_V7 = 0x0000FE04 

NOTE: This configuration must be used for vertical downsampling factors between 1/2 and 1/4 

7.6.2 Display Low-Power Refresh Settings 

This section describes the display low-power refresh application on the device. The display subsystem 

remains active while saving power by putting unused power domains and unused modules into idle mode. 

This process can be expanded to include the screen saver mode in which the MPU subsystem wakes up 

to update the frame buffer and then returns to idle mode. On the device platform, where power 

consumption is of high importance, the display modes must be configured properly to achieve optimal 

power savings 

The display low-power refresh mode can be used in the following scenarios: 

• During the period of time when there is no application running and the backlight turns off. 

• Once the backlight turns off, the LCD display can be shut off or can be refreshed showing the time and 

date. The screen saver mode can be used to update the time every minute. 

This section discusses the methodology for finding optimal power savings. These settings are detailed for 

a 16-bit, 240 x 320 pixel QVGA LCD. 

7.6.2.1 Display Low-Power Refresh Overview 

When the device is not in idle mode, meaning all clocks are on and the power is applied to all power 

domains, the following activity typically occurs with respect to the display subsystem: 

• The MPU subsystem is processing 

• The display subsystem DMA controller is moving data from the SDRAM frame buffer location to the 

display subsystem internal FIFO. 

• The LCD data is being sent from the internal FIFO to the display panel. 

When the MPU goes into idle mode, the following activity occurs: 

• The display subsystem DMA controller remains active, moving data from the SDRAM frame buffer to 

the internal FIFO. 





• The SDRAM will go in and out of self-refresh between transfers. 

• The display subsystem internal FIFO will continue to send LCD data to the display panel. 

This procedure is named as the display low-power refresh scenario. 

NOTE: In the device, the display subsystem has its own power domain (the DSS power domain). 

7.6.2.2 Display Subsystem Clock 

7.6.2.2.1 Display Subsystem Clock Configuration 

The display subsystem contains two possible functional clock sources, DSS functional clock 1 

(DSS1_ALWON_FCLK) and DSI PLL functional clock 1 (DSI1_PLL_FCLK): 

• DSS1_ALWON_FCLK is sourced from DPLL4 (DPLL4_ALWON_FCLK), with several multipliers 

available and is configured in the PRCM.CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 bit field. 

• DSI1_PLL_FCLK is one of the two output clocks from the DSI PLL. 

The pixel clock is set as either DSS1_ALWON_FCLK or DSI1_PLL_FCLK by configuring the 

DSS.DSS_CONTROL[0] DISPC_CLK_SWITCH bit 

NOTE: When the DSI PLL is in bypass mode, the DSI1_PLL_FCLK clock is the 

DSS2_ALWON_FCLK clock. This ensures the backward compatibility with OMAP2 devices. 

The LCD logic clock is determined by the DSS.DISPC_DIVISOR[23:16] LCD bit field. This divisor is used 

on the DSS functional clock that is selected in the DSS_CONTROL register (either DSS1_ALWON_FCLK 

or DSS2_ALWON_FCLK). This LCD divisor selects the logical clock frequency which is used to clock the 

logic in the display subsystem. For some applications there is a required minimum logical clock frequency. 

The lower the logical clock frequency then the lower the power consumption. 

The pixel clock is determined by setting the DSS.DISPC_DIVISOR[7:0] PCD bit field. This divisor is used 

on the LCD logic clock. 

In the following example, the DPLL4 clock (DPLL4_ALWON_FCLK) is enabled and running at 266 MHz: 

The PRCM.CM_CLKSEL2_PLL[19:8] PERIPH_DPLL_MULT bit field is set to 0x4 and the 

PRCM.CM_CLKSEL2_PLL[6:0] PERIPH_DPLL_DIV bit field is set to 0x1 (DPLL4 x 4/(1+1)): 

DPLL4_ALWON_FCLKOUT= DPLL4_ALWON_FCLK(266MHz) x 4/2 = 532 MHz 

NOTE: The DPLL4_ALWON_FCLOUT clock is an internal clock in DPLL4 module after the 

DPLL_MULT and DPLL_DIV stages. The DPLL4_M4_CLK clock is one of the DPLL4 output 

clocks and is the clock source for DSS1_ALWON_FCLK. 

The DSS.DSS_CONTROL[0] DSS_CLK_SWITCH bit is set to 0x0 to select DSS1_ALWON_FCLK as the 

display subsystem functional clock: 

DSS1_ALWON_FCLK = DPLL4_M4_CLK 

The PRCM.CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 bit field is set to 0x08: 

DPLL4_ALWON_FCLKOUT (532MHz) 

DSS1_ALWON_FCLK = = 66.5 MHz 

8 

The DSS.DISPC_DIVISOR[23:16] LCD bit field is set to 0x01: 

DSS1_ALWON_FCLK(66.5MHz) 

LogicClock = = 66.5 Mhz 

1 

dss-E121 

The DSS.DISPC_DIVISOR[6:0] PCD bit field is set to 0x0C: 



dss-E120 

(19) 

(20) 

1773

LogicClock(66.5MHz) 

PixelClock = = 5.54 Mhz 

12 

dss-E122 



7.6.2.2.1.1 Pixel Clock Frequency Settings to Reduce Power Consumption 

Power consumption is reduced when a low pixel clock frequency is used. If the clock frequency is set too 

low, however, the frames-per-second (FPS) are reduced. This can result in visible flickering on the screen 

each time the screen is refreshed. To avoid electrical polarization problems, refer to the appropriate LCD 

panel datasheet to determine the maximum range of pixel clock frequency variation. To save power, 

therefore, the pixel clock frequency during low-power mode must be set as low as possible, but high 

enough to eliminate visible flickering 

7.6.2.2.1.2 Display Subsystem Divider Settings to Reduce Power Consumption 

The pixel clock is determined by the DSS.DISPC_DIVISOR[7:0] PCD and DSS.DISPC_DIVISOR[23:16] 

LCD settings. In most cases, the LCD[7:0] bit field is set to 0x1 and the PCD[7:0] bit field is used as the 

main divider. To reduce power consumption, software users should investigate if the 

DSS.DISPC_DIVISOR[23:16] LCD bit field can be set to a value other than 0x1 and then decrease 

DSS.DISPC_DIVISOR[7:0] PCD bit field value. For example, if the desired pixel clock is 1.625 MHz with a 

13-MHz functional clock, then this pixel clock can be achieved by setting DSS.DISPC_DIVISOR[23:16] 

LCD to 0x1 and DSS.DISPC_DIVISOR[7:0] PCD to 0x8. The same pixel clock can be achieved by setting 

DSS.DISPC_DIVISOR[23:16] LCD to 0x2 and DSS.DISPC_DIVISOR[7:0] PCD to 0x4. 

7.6.2.2.2 Display Subsystem Clock Enable 

To take the DSS out of reset, all DSS-related clocks must be enabled, and the DPLL4 clock must be 

enabled. After taking the DSS out of reset, these clocks can be disabled if they are not used. The 

following clocks must be enabled before the DSS can come out of reset: 

• PRCM.CM_FCLKEN_DSS[0] EN_DSS1 = 0x1 

• PRCM.CM_FCLKEN_DSS[1] EN_DSS2 = 0x1 

• PRCM.CM_FCLKEN_DSS[2] EN_TV = 0x1 

• PRCM.CM_ICLKEN_DSS[0] EN_DSS = 0x1 

• PRCM.CM_CLKEN_PLL[18:16] EN_PERIPH_DPLL = 0x7 

Once these clocks are enabled, the display subsystem can be taken out of reset. 

The following sections explain the display low-power mode configuration options, which are determined by 

product requirements (LCD panel type). 

7.6.2.3 DPLL4 in Low-Power Mode 

For optimal power savings in low-power mode, DPLL4 can be put into low-power stop mode. Thus the 

DSS1_ALWON_FCLK clock cut when DPLL4 is in low-power stop mode. Software users must switch from 

DSS1_ALWON_FCLK to DSI1_PLL_FCLK by setting the DSS.DSS_CONTROL[0] DISPC_CLK_SWITCH 

bit to 0x1. 

NOTE: Before switching to DSI1_PLL_FCLK, the DSI PLL and the HS divider must be programmed 

and the DSI PLL must be locked. 

DPLL4 can be put in low-power stop mode in either of the following methods: 

• Manually: When setting the PRCM.CM_CLKEN_PLL[18:16] EN_PERIPH_DPLL bit to 0x1. 

• Automatically: When setting the PRCM.CM_AUTOIDLE_PLL[5:3] AUTO_PERIPH_DPLL bit field to 

0x1. DPLL4 is automatically put in low-power stop mode when none of the 96- MHz and 54- MHz 

clocks are required anymore. DPLL4 is also restarted automatically. 

Software users must remember to change the clock configuration after enabling DPLL4 when leaving 

low-power mode by setting the DSS.DSS_CONTROL[0] DISPC_CLK_SWITCH bit to 0x0. The 

DSS1_ALWON_FCLK clock will be selected. 



(21)



Lock time must be considered before disabling the DSS1_ALWON_FCLK clock. 

7.6.2.4 Autoidle and Smart Idle 

7.6.2.4.1 Autoidle 

To further save power consumption, the autoidle feature at the module can be enabled for the active 

modules. For example, the PRCM and the system control modules are active during this mode. By 

enabling the autoidle feature, the clocks at the module level are gated when they are not needed. 

The RFBI, display controller, and L4 interfaces can internally gate their clocks to decrease power 

consumption if no transaction is present on the related bus. The following bits must be set to enable this 

functionality: 

• DSS.DSS_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display subsystem 

• DSS.RFBI_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the RFBI 

• DSS.DISPC_SYSCONFIG[0] AUTOIDLE bit (1: Autoidle; 0: Clock free-running) for the display 

controller 

• DSS.DISPC_CONFIG[9] FUNCGATED bit (1: Functional clocks gated enabled, 0: Functional clocks 

gated disabled) for the display controller 

7.6.2.4.2 Smart-Idle 

The smart-idle feature can be enabled to allow the module to enter idle when the clocks are not needed. 

The smart-idle feature can be enabled for the display subsystem submodules to further save power 

consumption: 

• Display subsystem: DSS.DSS_SYSCONFIG[4:3] SIDLEMODE 

• Display controller: DSS.DISPC_SYSCONFIG[4:3] SIDLEMODE 

• RFBI: DSS.RFBI_SYSCONFIG[4:3] SIDLEMODE 

7.6.2.5 FIFO Thresholds 

The display subsystem internal FIFO is used to move data to the LCD panel. This FIFO is filled by the 

display subsystem DMA controller. The DMA controller is triggered to start and stop based on two 

thresholds: 

• DSS.DISPC_GFX_FIFO_THRESHOLD[11:0] GFXFIFOLOWTHRESHOLD 

• DSS.DISPC_GFX_FIFO_THRESHOLD[27:16] GFXFIFOHIGHTHRESHOLD 

When the level of the FIFO reaches the low threshold, the internal DMA controller begins to fill the FIFO 

With the data in the frame buffer. Once the amount of pixel data reaches the high threshold, the internal 

DMA controller stops. 

7.6.2.5.1 FIFO Threshold Settings to Reduce Power Consumption 

Power consumption is reduced by increasing the difference between the high and low FIFO threshold 

levels, thereby leaving the SDRAM in self-refresh for a longer period of time. To perform this reduction, 

consider the following: 

• The low FIFO threshold level must be as low as possible, but not low enough to cause any underflow. 

• The high FIFO threshold level must not exceed the FIFO size minus one burst. A value above this limit 

results in the DMA controller trying to fill the FIFO to a level that cannot be reached, which will increase 

power consumption. 

• The difference between high and low FIFO threshold levels must not be less than one burst size. 

These settings do not reduce power consumption because the SDRAM never goes into self-refresh, 

but they will avoid underflow. 

7.6.2.6 Vertical and Horizontal Timings 

The vertical and horizontal timings and the pixel clock speed determine the number of frames updated per 



1775

f ps = 

1 

[(Hsw + 1) + (Hf p + 1) + 240 + (Hbp + 1)] x [(Vsw + 1) + Vf p + 320 + Vbp)] x (PCLK) 

VSYNC 

HSYNC 

HSYNC 

(zoom) 

PCLK 

Vsw = 2 



second. Figure 7-152 shows the timings for a 240 x 320 pixel QVGA LCD panel. If the pulse width (also 

called blanking) and the front porch parameters are increased, more setup time is added before the data 

is transferred. This additional time is beneficial for delaying the data transfer if the data is not ready 

because of bandwidth limitations. Care must be taken to determine the fps when modifying these 

parameters. 

Use the following formula to determine the fps for a 240 x 320 QVGA LCD: 

With: 

• Hsw: DSS.DISPC_TIMING_H[7:0] HSW bit field value 

• Hfp: DSS.DISPC_TIMING_H[19:8] HFP bit field value 

• Hbp: DSS.DISPC_TIMING_H[31:20] HBP bit field value 

• Vsw: DSS.DISPC_TIMING_V[7:0] VSW bit field value 

• Vfp: DSS.DISPC_TIMING_V[19:8] VFP bit field value 

• Vbp: DSS.DISPC_TIMING_V[31:20] VBP bit field value 

• PCLK: Pixel clock period 

The horizontal (Hsw) and vertical (Vsw) pulse widths and the horizontal front (Hfp) and back (Hbp) 

porches are increased by 1 because the value is programmed as the desired value minus 1. 

Figure 7-152. QVGA LCD Timings 

1 frame 

Vfp = 9 320H 1H Vbp = 6 

………… 

Hsw = 2 Hfp = 3 240 PCLK Hbp = 1 

…….. 

16 bits of data are sent to 

the LCD every clock 

during this period. 

dss-E123 

Zoom in to view 

1 Hsync cycle 

fps = 

[(2 + 1) + 4 + 240 + 2] x [(2 + 1) + 9 + 320 + 6] x 166.67 x 10 -9 

The fps for the example of 6-MHz pixel clock with the setting shown in Figure 7-152 is as follows: 

1 

fps = 71.57Hz (23) 

dss-E125 

7.6.2.6.1 Horizontal and Vertical Timing Settings to Reduce Power Consumption 

The number of fps that the screen is refreshed is also determined by the vertical and horizontal timings. 

Consequently, longer timings between frames (blanking periods) reduce the fps and reduce average 

power consumption. Shorter blanking periods increase fps and increases power consumption. If the 

blanking between frames is too small, a FIFO underflow may occur. 



dss-124 

(22)

DSI PLL 

DSI_PLL_REFCLK 2 REGM CLKin( MHz) 

DSI _ PHY ( MHz) 

 

REGN 1 HIGHFREQ 1 

HSDIVIDER 

/REGM3 + 1 

/REGM4 + 1 

DSI1_PLL_FCLK 

DSI2_PLL_FCLK 

Equation 1 

N * T VP_CLK = T L * TTxByteClkHS 

dss-301 

Equation 2 

R = TTxByteClkHS / TVP_PCLK dss-302 



7.6.3 How to Configure the DSI PLL in Video Mode 

Figure 7-153 shows a global overview of the DSI clock tree when used in video mode. 

Figure 7-153. DSI Clock Tree in Video Mode 

CLKIN4DDR 

DISP Controller DSI protocol 

DSI_PHY 

VP_PCLK 

/LCD /PCD T 

VP_CLK 

DSIFCLK 

TxByteClkHS 

The settings of the DSI PLL registers can be summarized by the following equations. 

where 

T L = T HS + HSA DSI + T HE + HFP DSI + (WC + 6)/NDL + HBP DSI 

N is an integer 

NDL: Number of data lane 

WC: Word count or payload in bytes 

T HS and T HE are equal to 4/NDL and 0 if they are disabled. 

HSA DSI is HSA period in video mode. 

/16 /4 

T HS is the length of HSYNC start short packet in number of byte clock cycles (TxByteClkHS). 

T HE is the length of HSYNC end short packet in number of byte clock cycles (TxByteClkHS). 

HBP DSI is HBP period in video mode. 

HFP DSI is HFP period in video mode. 

NOTE: HSA DSI timing is not used and does not have to be programmed when HE short packet is 

not generated. 

To synchronize DISPC and DSI Protocol Engine, users should follow the ratio R between TxByteClkHS 

and VP_PCLK as listed in Table 7-85. 

Table 7-85. Ratio R 

Number of data lanes Pixel format Ratio R 

1 16-bits pixel 1/2 



Data Lane 

Bit Clock 

Clock Lane 



dss-300 

(24) 

(25)

All cases are covered by: 

FVP_PCLK * bits_per_pixel = FTxByteClkHS* NDL * 8 

dss-310 



Equation 3 

(HSADISPC + HFPDISPC + PPL + HBPDISPC ) * TVP_PCLK = (4/NDL + HFPDSI + (WC + 6)/NDL + HBPDSI)* TTxByteClkHS Equation 4 

HFPDSI = ((HFPDISPC * bits_per_pixel) / (NDL * 8)) - (2 / NDL) 

Example 

REGM = (REGN+1)*F CLKIN4DDR / (2 * FDSI_PLL_REFCLK) REGM = 150 

dss-318 

Table 7-85. Ratio R (continued) 

Number of data lanes Pixel format Ratio R 

The desired performances are: 

2 16-bits pixel 1 



• Clock lane at 150 MHz 

• RGB24-888 

• 1-data lane 

• LCD size 480*640 with HSA _DISP = HFP _DISP = HBP _DISP =20, VSA _DISP = VFP _DISP = VBP _DISP =2 

Step 1. Determine REGM and REGN 

To obtain correct stability, Fint must be kept between 0.032 MHz and 52 MHz . In this case, Fint is 

maintained at 2 MHz. For more information, see the DSI PLL programming model. 

REGN = (F DSI_PLL_REFCLK / F int) 

– 1 

REGN = 12 

Where DSS2_ALWON_FCLK= 26 MHz is used as a reference clock for FDSI_PLL_REFCLK Step 2. Determine VP_PCLK and TxByteClkHS clocks. 

TxByteClkHS frequency is equal to 37.5 MHz. With ratio R equal to 1/3, VP_PCLK frequency is equal 

to 12,5 MHz. The frame rate can be estimated by: 

Frame rate = F VP_PCLK / (HSA DISPC + HFP DISPC+ PPL + HBP DISPC ) * (VSA DISPC + VFP DISPC+ LPP+ VBP DISPC ) 

dss-309 

Frame rate = 12,5 MHz / (540 ) * (646 ) 

Step 3. Determine LCD, PCD and REGM3 

T CLKIN4DDR = T TxByteClkHS / 16 = T VP_PCLK / ((REGM3 + 1) * LCD * PCD) 

((REGM3 + 1) * LCD * PCD) = 16 * 3 

Frame rate = 35,83 frame/sec dss-323 

dss-315 

If LCD and PCD are set to 1 and 3 respectively, REGM3 is equal to 15. 

Step 4. Verify N as integer 

Firstly, TL must be determined 

(HSADISPC + HFPDISPC + PPL + HBPDISPC ) * TVP_PCLK / TTxByteClkHS = TL= 1620 

From Equation 1, 



dss-316 

dss-303 

(26) 

(27)

N is an integer. 

Step 5. Determine HFP and HBP of the DSI protocol engine 


(HSA DISPC + HFP DISPC + PPL + HBP DISPC ) * TVP_PCLK 

/ T TxByteClkHS) - (4/NDL + (WC + 6)/NDL) = HFP DSI + HBPDSI 

HFP + HBP = 170 

DSI DSI 


HFP DSI= ((HFP DISPC* 

bits_per_pixel) / NDL* 8)) - (2 / NDL) 

HFP = 58 

DSI 

HBP = 170 - 58 = 112 

DSI 



N * T VP_CLK = T L * T TxByteClkHS 

N = T TxByteclkHS * T L/T VP_CLK = T L/(R*PCD) 

N = 14580 

7.6.4 DSI Video Mode Using the DISPC Video Port 

This section details the basic programming model of video mode using the DISPC video port. 

The DSI interface is connected to an external MIPI display controller and the following parameters are 

used: 

• 1 data lane: NDL = 1 

• Clock lane at 150 MHz (DSI_DDR_CLK) 

• LCD size is 640 x 480: 

dss-321 

– 480 pixels per line (PPL) 

– 680 lines per panel (LPP) 

• Display controller input format: YUV 

• Display controller output format: RGB888, that is 24 bits per pixel (BPP) 

• Word Count: WC = 3 x PPL 

• DSS2_ALWON_FLCK=26 MHz is used as a reference clock for DSI PLL 

• Virtual channel 0 (VC0) is used for video mode. 

• Interleaving is not used. 

• It is assumed that all modules used in these programming models are in after-POR state. 

Figure 7-154 is an overview of the connections in the display subsystem. 



dss-317 

1779



PRCM 

DSS_L3_ICLK 

DSS_L4_ICLK 



MPU subsystem 


M_IRQ_25 



IVA2_IRQ[13] 

STANDBY/WAIT 

handshake 

DSS_L3_ICLK 

DSS_L4_ICLK 



DSI1_PLL_FCLK 

DSI2_PLL_FCLK 

DSS_IRQ 


controller 


Data 

Syncs 



Figure 7-154. Overview 

DSI 

protocol 

engine 

DSI 

PLL 

controller 

Controls 

Data 

Status 

PLL control 

The steps listed in Table 7-86 are described in the following sections. 

Steps Section 

Table 7-86. Main Steps 

DSI 

complex I/O 

DSI PLL 

HS divider 

Device 

GPIO87 Reset 

dsi_dx0 

dsi_dy0 

dsi_dx1 

dsi_dy1 

Configure DSS clocks Section 7.6.4.1, Display Subsystem Clock Configuration 

Configure the DSI and DSI PLL Section 7.6.4.2, Configure DSI, DSI PLL and Complex I/O 

Configure the external MIPI display controller Section 7.6.4.3, Initialization of the External MIPI Display Controller 

Configure the DISPC Section 7.6.4.4, Configure the DISPC 

Enable video mode using the DISPC video port Section 7.6.4.5, Enable Video Mode Using the DISPC Video Port 

The programming model must be followed in the order of the following sections. 

7.6.4.1 Display Subsystem Clock Configuration 

Table 7-87 lists the steps required to enable the clocks. 

LCD 

External 

display 

controller 



dss-330



Table 7-87. PRCM Registers 

Steps Registers Value 

Set the divided DPLL value for DSS1. CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 0x9 

Disable autoidle mode. CM_AUTOIDLE_DSS[31:0] 0x0 

Domain sleep is disabled. CM_SLEEPDEP_DSS[31:0] 0x0 

Automatic transition between active and inactive are disabled. CM_CLKSTCTRL_DSS[31:0] 0x0 

Enable DSS1, DSS2 and TV clock (DSS1_ALWON_FCLK, 

DSS2_ALWON_FCLK and TV_CLK). TV_CLK is only need for correct CM_FCLKEN_DSS[31:0] 0x7 

Reset. 

Enable the subsystem interface clock (DSS_L3_ICLK and DSS_L4_ICLK). CM_ICLKEN_DSS[31:0] 0x1 

7.6.4.2 Configure DSI, DSI PLL and Complex I/O 

7.6.4.2.1 Reset DSI Modules 

Table 7-88 lists the steps required to reset the DSI modules. 

Table 7-88. Resets 


Reset IRQ status. DSI_IRQSTATUS[31:0] 0x0 

OCP and functional clock are maintained during wakeup, smart idle, and 

reset DSI. 

DSI_SYSCONFIG[31:0] 0x312 

Wait until RESET_DONE ≠ 0. DSI_SYSSTATUS[0] RESET_DONE Read 0x1 

7.6.4.2.2 Set Up DSI DPLL 

Table 7-89 lists the steps required to configure DSI PLL. 

Table 7-89. DSI PLL Configuration Registers 


Turn on PLL and HSDIVIDER. DSI_CLK_CTRL[31:30] PLL_PWR_CTRL 0x2 

Wait until PLL_PWR_STATUS = 0x2. DSI_CLK_CTRL[29:28] PLL_PWR_STATUS Read 0x2 

DSI_PLL_CONFIGURATION1[26:23] 

See the calculation following this table. 5 

DSIPROTO_CLK_DIV 



DSS_CLOCK_DIV 



DSI_PLL_REGM 


See calculation following this table. 12 

DSI_PLL_REGN 

Enable PLLStopMode. DSI_PLL_CONFIGURATION1[0] 0x1 

The DSI protocol engine clock divider, DSS clock divider, 

CLKIN4DDR, and PLL reference clock are enabled. PLL 

internal reference frequency is between 0.032 MHz and 52 

MHz. 

DSI_PLL_CONFIGURATION2[31:0] 0x5600E 

Manual mode DSI_PLL_CONTROL[31:0] 0x0 

Request PLL locking sequence. DSI_PLL_GO[0] DSI_PLL_GO 0x1 

Read until DSI_PLL_GO = 0 DSI_PLL_GO[0] DSI_PLL_GO Read 0x0 

PLL is locked. DSI_PLL_STATUS[1] DSI_PLL_LOCK Read 0x1 

Turn on PLL and HSDIVIDER; the DSI functional clock 30-MHz 

sync is rising/rising; the DSIStopClk signal is automatically 

asserted/deasserted; the L3_ICLK clock to the DSI complex I/O 

is not gated; and LPCLKDIVISOR = 8 

DSI_CLK_CTRL[31:0] 0x8024 4008 



RegM4 = 5 

2. Determine LCD, PCD, and REGM3: 

Calculate the divider value for DSS clock source: Same as Step 3. 

RegM3 ((BPP 2)/(DISPC _LCD DISPC _PCD NDL)) 1 

RegM3 15 

3. Calculate N Divider for PLL: 

FCLKIN4DDR FCLKIN 4 

RegN (FDSI_PLL _REFCLK /F INt) 1 

FDSI_PLL _REFCLK 26 MHz (system clock) 

Fint 2 MHz (reduce PLL lock time) 

RegN 12 

dss-E128 

dss-E127 

4. Calculate M divider for PLL: 

RegM ((RegN 1) (FCLKIN4DDR /(2 FDSI_PLL 

_REFCLK))) 

FCLKIN4DDR 4 150 

MHz 

RegM 150 



1. Calculate the divider value for the DSI protocol engine clock source: 

RegM4 = FCLKIN4DDR/DSI2_PLL_FCLK – 1 

FCLKIN4DDR = 4 x FCLKIN 

7.6.4.2.3 Switch to DSI PLL Clock Source 

Select the DSI_PLL1 clock as the DISPC functional clock, and select the DSI_PLL2 clock as the DSI 

functional clock: Set DSS_CONTROL to 0x3. 

7.6.4.2.4 Set Up DSI Protocol Engine 

7.6.4.2.4.1 Set Up DSI Control Registers 

Table 7-90 lists the steps to set up the DSI control registers. Table 7-91 lists the steps to set up the DSI 

complex I/O registers. 

dss-E129 

Table 7-90. DSI Control Registers 


Enable SYNCLOST event. DSI_IRQENABLE[31:0] 0x4 0000 

Set PACKET_SENT_IRQ_EN. DSI_VC0_IRQENABLE[31:0] 0x4 

While the HSYNC START pulse is detected, the associated short 

packet HSYNC START is generated. 

While the VSYNC START pulse is detected, the associated short 

packet VSYNC START is generated. 

DSI_CTRL[17] VP_HSYNC_START 0x1 

DSI_CTRL[15] VP_VSYNC_START 0x1 

Set the trigger reset mode to immediate. DSI_CTRL[14] TRIGGER_RESET_MODE 0x1 

Activate two line buffers. DSI_CTRL[13:12] LINE_BUFFER 0x2 

HSYNC signal on the video port is active high. DSI_CTRL[10] VP_HSYNC_POL 0x1 

VSYNC on the video port is active high. DSI_CTRL[11] VP_VSYNC_POL 0x1 

Set the Data Enable signal on the video port as active high. DSI_CTRL[9] VP_DE_POL 0x1 

Set the size of the video port data bus for the RGB format: 0x2 

for RGB 888. 

VP_CLK_RATIO is not used if video port is used to provide data 

in video mode 

DSI_CTRL[7:6] VP_DATA_BUS_WIDTH 0x2 

DSI_CTRL[4] VP_CLK_RATIO 0x0 





Table 7-90. DSI Control Registers (continued) 


Set the arbitration scheme for granting the VC pending ready 

requests in the TX FIFO as Sequential Scheme. 

DSI_CTRL[3] TX_FIFO_ARBITRATION 0x1 

Enable the ECC check for the received header. DSI_CTRL[2] ECC_RX_EN 0x1 

Table 7-91. DSI Complex I/O Registers 


GOBIT, complex I/O power ON, select data, and clock position DSI_COMPLEXIO_CFG1 0x4800 0032 

Clear Reg DSI_COMPLEXIO_IRQSTATUS 0xC3F39CE7 

Disable IRQ DSI_COMPLEXIO_IRQENABLE 0x0 

Enable I/F DSI_CTRL[0] IF_EN 0x1 

Disable I/F DSI_CTRL[0] IF_EN 0x0 

Wait until IF_EN = 0 DSI_CTRL[0] IF_EN Read 0x0 

Enable Low Power clock DSI_CLK_CTRL[20] LP_CLK_ENABLE 0x1 

Reset is done. DSI_COMPLEXIO_CFG1[29] RESET_DONE Read 0x1 

Power control is on. DSI_COMPLEXIO_CFG1[26:25] PWR_STATUS Read 0x1 

Reset is complete. DSI_SYSSTATUS[0] RESETDONE Read 0x1 

7.6.4.2.4.2 Configure DSI Timing and Virtual Channels 

Table 7-92 lists the steps to configure DSI timing and the virtual channels. 

Table 7-92. DSI Timing Registers 


STOP_STATE_COUNTER_IO = 0x999 DSI_TIMING1[31:0] 0x0000 0999 

HS_TX_TO_X8, HS_TX_TO_COUNTER = 0x0FD2, 

LP_RX_TO_X16, LP_RX_TO_COUNTER = 0x00CD 

DSI_TIMING2[31:0] 0x2FD2 40CD 

(HSA24)|(HFP12)|HBP DSI_VM_TIMING1[31:0] 0x0000 700A 

(WINDOW_SYNC24)|(VSA16)|(DSI_VFP8)|VBP DSI_VM_TIMING2[31:0] 0x0401 0101 

(TL16)|DSI_VACT DSI_VM_TIMING3[31:0] 0x05BB 0280 

(ENTER_HS_MODE_LATENCY16)|EXIT_HS_MODE_LATENCY DSI_VM_TIMING7[31:0] 

0x0000 

C000A 

DDR_CLK_PRE8|DDR_CLK_POST DSI_CLK_TIMING[31:0] 0x0000 0F0B 

HS speed, ECC generation for the Transmit, Enable CheckSum 

generation for the Payload. 

• Freq TxByteClkHS: 

FHSB = FCLKIN4DDR/16 

FVPP = FCLKIN4DDR/((RegM3 + 1) × DISPC_LCD * DISPC_PCD) 

DSI_VC0_CTRL[31:0] 0x2080 0390 

FVP = FCLKIN4DDR/(RegM3 + 1) (28) 



1783



• Length of the line in video mode in Nb of byte clock cycles (TxByteClkHS): 

TL = FHSB/FVPP × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP) 

TL1f = (BPP/(8 × NDL)) × (DISPC_HSA + DISPC_HFP + PPL +DISPC_HBP) (29) 

• Blanking periods (HBP + HFP) in DSI are calculated based on the following formula: 

(DISPC_HSA + DISPC_HBP + PPL + DISPC_HFP) × Fppi = (HS + HBP + ((WC + 6)/NDL) +HFP) × 

Fvp 

HBP + HFP = (TVPP/THSB) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP – (HS + (WC + 

6)/NDL)) 

HBPplusHFP = (FHSB/FVPP) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP) – (HS + WC + 

6)/NDL) 

HBPplusHFPf = ((FHSB/FVPP) × (DISPC_HSA + DISPC_HFP + PPL + DISPC_HBP)) – ((HS + WC + 

6)/NDL) 

HFP = (DISCP_HFP × BPP)/(NDL × 8) – (2/NDL) 

HBP = HBPplusHFP – HFP (30) 

7.6.4.2.5 Configure DSI_PHY 

Calculate the timing in the functions of DDR_CLK_P (see Table 7-93). In the example, DDR_CLK_P = 

1000/DSI_DDR_CLK. See Section 7.4.3.2, Clock Requirements, for details on timing calculation. 

Table 7-93. Calculate DSI_PHY Timing 


Refer to Section 7.4.3.2 DSI_PHY_REGISTER0[31:24] REG_THSPREPARE CEIL(70 ns/DDR clock period) + 2 


REG_THSPRPR_THSZERO 

ceil(175 ns/DDR clock period) + 2 

DSI_PHY_REGISTER0[7:0] REG_THSEXIT ceil(145 ns/DDR clock period) 

DSI_PHY_REGISTER0[15:8] REG_THSTRAIL ceil(60 ns/DDR clock period) + 5 

DSI_PHY_REGISTER2[7:0] REG_TCLKPREPARE ceil(65 ns/DDR clock period) 

DSI_PHY_REGISTER1[7:0] REG_TCLKZERO ceil(265 ns/DDR clock period) 

DSI_PHY_REGISTER1[15:8] REG_TCLKTRAIL ceil(60 ns/DDR clock period) + 2 

DSI_PHY_REGISTER1[20:16] REG_TLPXBY2 ceil(25ns/DDR clock period) 

NOTE: Keep Reserved bits at reset value in the DSI_PHY_REGISTER1 and 

DSI_PHY_REGISTER2 registers. 

7.6.4.2.6 Drive Stop State 

Table 7-94 lists the steps to Drive Stop State. 

Table 7-94. Drive Stop State 


Force TX stop mode DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO 0x1 

Wait until FORCE_TX_STOP_MODE_IO = 0 DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO Read 0x0 

7.6.4.3 Initialization of the External MIPI Display Controller 

1. Wait for the external MIPI display controller initialization after power up. 

In this example, the external MIPI display controller is reset using GPIO 87. 

2. Configure the external MIPI display controller. 





7.6.4.4 Configure the DISPC 

7.6.4.4.1 Reset DISPC 

Table 7-95 lists the step sequence to reset the DISPC. 

Table 7-95. Reset DISPC 


Reset the DISPC. DISPC_SYSCONFIG[1] SOFTRESET 0x1 

DISPC is reset. DISPC_SYSCONFIG[0] RESETDONE Read 0x1 

No standby: MStandby is never asserted. DISPC_SYSCONFIG [13:12] MIDLEMODE 0x1 

Disable idle mode. DISPC_SYSCONFIG [4:3] SIDLEMODE 0x1 

Disable all interrupts. DISPC_IRQENABLE[31:0] 0x0 

7.6.4.4.2 Configure DISPC Timing, Window, and Color 

Table 7-96 lists the steps to configure the DISPC registers. Table 7-97 lists the steps to configure the 

color space coefficient registers. 

Table 7-98 lists the steps to configure DISPC_CONTROL. 

Table 7-96. Configure DISPC Registers 


Set horizontal timings. DISPC_TIMING_H (HBP – 120)|(HFP – 18)|HSA – 1 

Set vertical timing. DISPC_TIMING_V (HBP – 120)|(HFP – 18)|HSA – 1 

Set LCD – PCD display controller and pixel 

clock divisor. 

DISPC_DIVISOR LDC = %1 PXLCLK = %4 

Set the size of the LCD – 1. DISPC_SIZE_LCD (LPP – 1 + DSI_VFP)16|(PPL – 1) 

Set default RGB value when there is no 

data. 

DISPC_DEFAULT_COLOR0 0XFF 

Set video FIFO height and low threshold. DISPC_VID1_FIFO_THRESHOLD 0xfc00c0 

Set the X Y location of the upper left pixel (0 

= 0) to the upper left corner. 

DISPC_VID1_POSITION 0x0 

Set size of the window. DISPC_VID1_SIZE (LPP – 1) 16|(PPL – 1) 

Set the size of the picture. DISPC_VID1_PICTURE_SIZE (LPP – 1) 16|(PPL – 1) 

Set the input address picture. DISPC_VID1_BA0 0x– 

Table 7-97. Configure Color Space Coefficient Registers 

Comments Registers Value 

RCR and RY coefficients DISPC_VID1_CONV_COEF0 0X0199012A 

GY and RCB coefficients DISPC_VID1_CONV_COEF1 0X012A0000 

GCB and GCR coefficients DISPC_VID1_CONV_COEF2 0X079C0730 

BCR and BY coefficients DISPC_VID1_CONV_COEF3 0X0000012A 

BCB coefficient DISPC_VID1_CONV_COEF4 0X00000205 

Table 7-98. Configure DISPC_CONTROL 


Enable pixel clock free-running. DISPC_CONTROL[27] PCLKFREEENABLE 0x1 

I/O pad mode selection: Bypass DISPC_CONTROL[16] GPOUT1 0x1 

I/O pad mode selection: Bypass DISPC_CONTROL[15] GPOUT0 0x1 

Normal mode selected DISPC_CONTROL[11] STALLMODE 0x0 

3 for RGB888 DISPC_CONTROL[9:8] TFTDATALINES 0x3 





Table 7-98. Configure DISPC_CONTROL (continued) 


The hardware has finished updating the internal shadow 

registers of the pipeline(s) connected to the LCD output using 

the user values. The hardware resets the bit when the update 

completes. 

DISPC_CONTROL[5] GOLCD 0x0 

Active matrix display operation mode DISPC_CONTROL[3] STNTFT 0x1 

LCD interface is disabled. DISPC_CONTROL[0] LCDENABLE 0x0 

The input image is converted from UYVY into RGB (see Table 7-99) : 

Table 7-99. Configure DISPC_VID1_ATTRIBUTES 


Row of VIDn will not be read twice. DISPC_VID1_ATTRIBUTES[18] VIDROWREPEATENABLE 0x0 

8 x 32-bit bursts DISPC_VID1_ATTRIBUTES[15:14] VIDBURSTSIZE 0x1 

Full range selected: Y is not modified before the 

color space conversion. 

DISPC_VID1_ATTRIBUTES[11] VIDFULLRANGE 0x1 

Enable color space conversion CbYCr to RGB. DISPC_VID1_ATTRIBUTES[9] VIDCOLORCONVENABLE 0x1 

UYVY DISPC_VID1_ATTRIBUTES[4:1] VIDFORMAT 0xB 

Video disabled DISPC_VID1_ATTRIBUTES[0] VIDENABLE 0x0 

7.6.4.5 Enable Video Mode Using the DISPC Video Port 

Table 7-100 lists the steps to enable DISPC to send frames continuously. 

Table 7-100. Enable DISPC 


Set up long packet header DSI_VC0_LONG_PACKET_HEADER[31:0] 0x0005 A03E 

Enable VC0. DSI_VC0_CTRL[1] VC_EN 0x1 

Enable IF. DSI_CTRL[0] IF_EN 0x1 

Wait until IF_EN ≠ 0. DSI_CTRL[0] IF_EN Read 0x0 

Enable VID1. DISPC_VID1_ATTRIBUTES[0] VIDENABLE 0x1 

Enable LCD interface. DISPC_CONTROL[0] LCDENABLE 0x1 

Enable GOLCD. DISPC_CONTROL[5] GOLCD 0x1 

Wait until GOLCD = 0. DISPC_CONTROL[5] GOLCD Read 0x0 

7.6.5 DSI Command Mode Using the DISPC Video Port 

This section presents some generic use cases and tips for setting the modules of the display subsystem. 

7.6.5.1 Display Subsystem Use Cases and Tips 

This section explains the basic programming model of command mode using the DISPC video port. 

The DSI interface is connected to an external MIPI DISPC using the following parameters: 

• One data lane: NDL = 1 

• Clock lane at 150 MHz (DSI_DDR_CLK) 

• LCD size is 640 x 480: 

– 480 PPL 

– 680 LPP 

• DISPC input format: YUV 

• DISPC output format: RGB888 (24 BPP) 

• Word Count: WC = 3 x PPL 

• DSS2_ALWON_FLCK = 26 MHz used as a reference clock for DSI PLL 





PRCM 

DSS_L3_ICLK 

DSS_L4_ICLK 



MPU subsystem 


M_IRQ_25 



IVA2_IRQ[13] 

STANDBY/WAIT 

handshake 

DSS_L3_ICLK 

DSS_L4_ICLK 



DSI1_PLL_FCLK 

DSI2_PLL_FCLK 

DSS_IRQ 


controller 


Data 

Syncs 



• Virtual channel 1 (VC1) used for command mode to configure the eternal DISPC, and virtual channel 0 

(VC0) used to send data 

• Automatic TE used for synchronization 

• Interleaving not used 

• It is assumed that all modules used in these programming models are in after-POR state. 

Figure 7-155 is an overview of the connections in the display subsystem. 

Figure 7-155. Overview 

DSI 

protocol 

engine 

DSI 

PLL 

controller 

Controls 

Data 

Status 

PLL control 

DSI 

complex I/O 

DSI PLL 

HS divider 

Device 

GPIO87 Reset 

dsi_dx0 

dsi_dy0 

dsi_dx1 

dsi_dy1 

Table 7-101 lists the steps of the main sequence and the sections that describe them. 

Table 7-101. Main Sequence 

Steps Register/Bit Field/Programming Model 

Configure DSS clocks. Section 7.6.5.1.1, Configure DSS Clocks at the PRCM Module 

LCD 

External 

display 

controller 

Configure the DSI protocol engine and DSI PLL. Section 7.6.5.1.2, Configure DSI Protocol Engine, DSI PLL, and Complex I/O 

Configure the external MIPI display controller. Section 7.6.5.1.3, Initialization of the External MIPI Display Controller 



dss-330



Table 7-101. Main Sequence (continued) 


Configure the DISPC. Section 7.6.5.1.4, Configure the DISPC 

Enable command mode using the DISPC video 

port. 

Section 7.6.5.1.5, Enable Command Mode Using the DISPC Video Port 

Send a frame data to LCD panel using automatic Section 7.6.5.1.6, Send Frame Data to LCD Panel Using Automatic TE 

TE. 

The programming model must follow the step sequence. 

7.6.5.1.1 Configure DSS Clocks at the PRCM Module 

Table 7-102 lists the steps required to enable the clocks. 

Table 7-102. Configure DSS Clocks at the PRCM Module 

Steps Register/Bit Field/Programming Model Value 

Set the divided DPLL value for 

DSS1. 

CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 0x9 

Disable autoidle mode. CM_AUTOIDLE_DSS[0] AUTO_DSS 0x0 

CM_SLEEPDEP_DSS[2:0] EN_IVA2, EN_MPU, 

Domain sleep is disabled. 0x0 

EN_CORE 

Disable automatic transition. CM_CLKSTCTRL_DSS[1:0] CLKTRCTRL_DSS 0x0 

Enable the 

DSS1_ALWON_FCLK, 

DSS2_ALWON_FCLK, and 

TV_CLK functional clocks. (1) 

Enable the DSS_L3_ICLK and 

DSS_L4_ICLK interface clocks. 

(1) TV_CLK is required only for a correct reset. 

CM_FCLKEN_DSS[2:0] EN_TV, EN_DSS2, EN_DSS1 0x7 

CM_ICLKEN_DSS[0] EN_DSS 0x1 

7.6.5.1.2 Configure DSI Protocol Engine, DSI PLL, and Complex I/O 

Table 7-103 lists the steps to configure the DSI protocol engine, DSI PLL, and complex I/O and the 

sections that describe the sequence. 

Table 7-103. Configure DSI Protocol Engine, DSI PLL, and Complex I/O 


Reset DSI modules. Section 7.6.5.1.2.1, Reset DSI Modules 

Configure DSI DPLL. Section 7.6.5.1.2.2, Configure DSI PLL 

Switch to DSI PLL clock source. Section 7.6.5.1.2.3, Switch to DSI PLL Clock Source 

Configure DSI protocol engine. Section 7.6.5.1.2.4, Configure DSI Protocol Engine 

Configure DSI_PHY. Section 7.6.5.1.2.5, Configure DSI_PHY 

Drive stop state. Section 7.6.5.1.2.6, Drive Stop State 

7.6.5.1.2.1 Reset DSI Modules 

Table 7-104 lists the steps required to reset the DSI modules. 

Table 7-104. Reset DSI Modules 

Steps Register/Bit Field/Programming Value 

Clear DSI IRQ status. DSI_IRQSTATUS[31:0] 0x0 

Maintain interface and functional clock during 

wakeup. 

DSI_SYSCONFIG[9:8] CLOCKACTIVITY 0x3 

Enable smart-idle for power management. DSI_SYSCONFIG[4:3] SIDLEMODE 0x2 

Set DSI reset. DSI_SYSCONFIG[1] SOFT_RESET 0x1 



(1) Calculate the divider value for the DSI protocol engine clock source: 

RegM4 FCLKIN4DDR /FDSI_PLL _REFCLK 1 

FCLKIN4DDR 4 FCLKIN 

RegM4 5 

dss-E126 

(2) Determine LCD, PCD, and REGM3: 

Calculate the divider value for the DSS clock source: Same as Step 3. 

RegM3 ((BPP 2)/(DISPC _LCD DISPC _PCD NDL)) 1 

RegM3 15 



Table 7-104. Reset DSI Modules (continued) 


Wait until RESET_DONE = 1. DSI_SYSSTATUS[0] RESET_DONE 

7.6.5.1.2.2 Configure DSI PLL 

Table 7-105 lists the steps required to configure the DSI PLL. 

Table 7-105. Configure DSI PLL 


Enable PLL and HSDIVIDER. DSI_CLK_CTRL[31:30] PLL_PWR_CMD 0x2 

Wait until PLL_PWR_STATUS = 0x2. DSI_CLK_CTRL[29:28] PLL_PWR_STATUS 

Set the REGM4 value (see (1)). DSI_PLL_CONFIGURATION1[26:23] DSIPROTO_CLK_DIV 5 

Set the REGM3 value (see (2)). DSI_PLL_CONFIGURATION1[22:19] DSS_CLOCK_DIV 15 

Set the REGN value (see (3)). DSI_PLL_CONFIGURATION1[7:1] DSI_PLL_REGN 12 

Set the REGM value (see (4)). DSI_PLL_CONFIGURATION1[18:8] DSI_PLL_REGM 150 

Enable PLL STOPMODE. DSI_PLL_CONFIGURATION1[0] DSI_PLL_STOPMODE 0x1 

Enable PLL reference clock control. DSI_PLL_CONFIGURATION2[13] DSI_PLL_REFEN 0x1 

Enable CLKIN4DDR control. DSI_PLL_CONFIGURATION2[14] DSI_PHY_CLKINEN 0x1 

Enable DSS clock divider. DSI_PLL_CONFIGURATION2[16] DSS_CLOCK_EN 0x1 

DSI_PLL_CONFIGURATION2[18] 

Enable DSI protocol engine clock divider. 0x1 

DSI_PROTO_CLOCK_EN 

Enable DSI configuration update with 

DISPC_UPDATE_SYNC. 

DSI_PLL_CONTROL[0] DSI_PLL_AUTOMODE 0x0 

Start PLL locking sequence. DSI_PLL_GO[0] DSI_PLL_GO 0x1 

Wait until DSI_PLL_GO = 0. DSI_PLL_GO[0] DSI_PLL_GO 

Check whether PLL is locked. DSI_PLL_STATUS[1] DSI_PLL_LOCK 0x1 

Set the LP mode clock ratio. DSI_CLK_CTRL[12:0] LP_CLK_DIVISOR 0x8 

Set L3_ICLK clock to the DSI complex I/O to not 

gated. 

DSI_CLK_CTRL[14] CIO_CLK_ICG 0x1 

Enable the automatic assertion/deassertion of the DSI_CLK_CTRL[18] HS_AUTO_STOP_ENABLE 0x1 

DSIStopClk signal. 

Specify that the DSI functional clock is higher 

than 30 MHz with a synchronization rising/rising. 

DSI_CLK_CTRL[21] LP_RX_SYNCHRO_ENABLE 0x1 

Turn on PLL and HSDIVIDER. DSI_CLK_CTRL[31:30] PLL_PWR_CMD 0x2 

(3) Calculate N divider for PLL: 


dss-E127 


1789

FCLKIN4DDR FCLKIN 4 

RegN (FDSI_PLL _REFCLK /F INt) 1 

FDSI_PLL _REFCLK 26 MHz (system clock) 

Fint 2 MHz (reduce PLL lock time) 

RegN 12 

dss-E128 

(4) Calculate M divider for PLL: 

RegM ((RegN 1) (FCLKIN4DDR /(2 FDSI_PLL 

_REFCLK))) 

FCLKIN4DDR 4 150 

MHz 

RegM 150 



7.6.5.1.2.3 Switch to DSI PLL Clock Source 

Table 7-106 lists the sequence to switch the DSI and DISPC module clocks to DSI PLL clock source. 

dss-E129 

Table 7-106. Switch to DSI PLL Clock Source 


Switch DISPC clock to DSI1_PLL_FCLK. DSS_CONTROL[0] DISPC_CLK_SWITCH 0x1 

Switch DSI clock to DSI2_PLL_FCLK. DSS_CONTROL[1] DSI_CLK_SWITCH 0x1 

7.6.5.1.2.4 Configure DSI Protocol Engine 

7.6.5.1.2.4.1 Set Up DSI Control Registers 

Table 7-107 lists the steps required to set up the DSI control registers. Table 7-108 lists the steps to set 

up the DSI complex I/O registers. 

Table 7-107. DSI Control Registers 


Enable SYNCLOST event. DSI_IRQENABLE[18] SYNC_LOST_IRQ_EN 0x1 

Enable IRQ to indicate that packet has been 

sent on VC1. 

Enable IRQ to indicate that packet has been 

sent on VC0. 

DSI_VC1_IRQENABLE[2] PACKET_SENT_IRQ 0x1 

DSI_VC0_IRQENABLE[2] PACKET_SENT_IRQ 0x1 

Set the trigger reset mode to immediate. DSI_CTRL[14] TRIGGER_RESET_MODE 0x1 

Activate the two line buffers. DSI_CTRL[13:12] LINE_BUFFER 0x2 

Set the size of the video port data bus to 24 

bits (RGB 888). 

Define the ratio between VP_CLK and 

VP_PCLK. 

DSI_CTRL[7:6] VP_DATA_BUS_WIDTH 0x2 

DSI_CTRL[4] VP_CLK_RATIO 0x1 

Set the arbitration scheme for granting the VC 

pending ready requests in the TX FIFO as DSI_CTRL[3] TX_FIFO_ARBITRATION 0x1 

sequential scheme. 

Enable the ECC check for the received header. DSI_CTRL[2] ECC_RX_EN 0x1 

Table 7-108. DSI Complex I/O Registers 


Determine the position of the clock lane. DSI_COMPLEXIO_CFG1[2:0] CLOCK_POSITION 0x2 

Determine the position of data 1 lane. DSI_COMPLEXIO_CFG1[6:4] DATA1_POSITION 0x3 

Turn on COMPLEXIO. DSI_COMPLEXIO_CFG1[28:27] PWR_CMD 0x1 

Enable the synchronization of the shadow 

registers with DISPC_UPDATE_SYNC. 

DSI_COMPLEXIO_CFG1[30] GOBIT 0x1 





Table 7-108. DSI Complex I/O Registers (continued) 


Clear all COMPLEXIO IRQ status. DSI_COMPLEXIO_IRQSTATUS 0xC3F39CE7 

Disable all COMPLEXIO IRQs. DSI_COMPLEXIO_IRQENABLE 0x0 

Enable interface. DSI_CTRL[0] IF_EN 0x1 

Disable interface. DSI_CTRL[0] IF_EN 0x0 

Wait until IF_EN = 0. DSI_CTRL[0] IF_EN 

Enable the LP clock. DSI_CLK_CTRL[20] LP_CLK_ENABLE 0x1 

Check whether reset is complete. DSI_COMPLEXIO_CFG1[29] RESET_DONE 0x1 

Check whether power control is on. DSI_COMPLEXIO_CFG1[26:25] PWR_STATUS 0x1 

Check whether reset is complete. DSI_SYSSTATUS[0] RESETDONE 0x1 

7.6.5.1.2.4.2 Configure DSI Timing and Virtual Channels 

Table 7-109 lists the steps to configure DSI timing and the virtual channels. 

Table 7-109. DSI Timing Registers 


Determine the number of DSI_FCLK clock DSI_TIMING1[12:0] 

cycles for the STOP-STATE counter. STOP_STATE_COUNTER_IO 

Disable the multiplication factor of 4 for the 

number of DSI_FCLK clock cycles for the DSI_TIMING1[13] STOP_STATE_X4_IO 0x0 

STOP-STATE counter. 


number of DSI_FCLK clock cycles for the DSI_TIMING1[14] STOP_STATE_X16_IO 0x0 

STOP-STATE counter. 

0x999 

Clear turn-around timer settings. DSI_TIMING1[30:16] 0x0000 

Determine the number of DSI_FCLK clock 

cycles for the LP RX timer. 

DSI_TIMING2[12:0] LP_RX_TO_COUNTER 0x0CD 


number of DSI_FCLK clock cycles for the LP DSI_TIMING2[13] LP_RX_TO_X4 0x0 

RX timer. 

Enable the multiplication factor of 16 for the 

number of DSI_FCLK clock cycles for the LP DSI_TIMING2[14] LP_RX_TO_X16 0x1 

RX timer. 

Determine the number of TxByteClkHS clock 

cycles for the HS RX timer. 

DSI_TIMING2[12:0] HS_TX_TO_COUNTER 0xFD2 


number of TxByteClkHS clock cycles for the DSI_TIMING2[13] HS_TX_TO_X8 0x0 

HS TX timer. 

Enable the multiplication factor of 16 for the 

number of TxByteClkHS clock cycles for the DSI_TIMING2[14] HS_TX_TO_X16 0x1 

HS TX timer. 

DDR_CLK_PRE8|DDR_CLK_POST DSI_CLK_TIMING[31:0] 0x0000 0F0B 

Configuration of VC1 

Enable the checksum generation for the 

transmit payload. 

Enable the ECC generation for the transmit 

header. 

DSI_VC1_CTRL[7] CS_TX_EN 0x1 

DSI_VC1_CTRL[8] ECC_TX_EN 0x1 

Disable DMA request for TX FIFO. DSI_VC1_CTRL[23:21] DMA_TX_REQ_NB 0x4 

Disable DMA request for RX FIFO. DSI_VC1_CTRL[29:27] DMA_RX_REQ_NB 0x4 

Configuration of VC0 

Selects source of data and enable VP_STALL. DSI_VC0_CTRL[1] SOURCE 0x1 

Enable the checksum generation for the 

transmit payload. 

DSI_VC0_CTRL[7] CS_TX_EN 0x1 



• Freq TxByteClkHS: 

FHSB FCLKIN4DDR /16 

FVPP FCLKIN4DDR /((RegM3 1) DISPC 

_LCD * DISPC _PCD) 

FVP FCLKIN4DDR /(RegM3 1) 

dss-E130 

• Length of the line in video mode in number of byte clock cycles (TxByteClkHS): 

TL FHSB /FVPP (DISPC _HSA DISPC _HFP PPL DISPC _HBP) 

TL1f (BPP /(8 NDL)) (DISPC _HSA DISPC _HFP PPL DISPC _HBP) 

• Blanking periods (HBP + HFP) in DSI are calculated based on the following formula: 

(DISPC _HSA DISPC _HBP PPL DISPC _HFP) Fppi (HS HBP ((WC 6)/NDL) HFP) 

Fvp 

dss-E131 

HBP HFP (TVPP / THSB) (DISPC _HSA DISPC _HFP PPL DISPC _HBP) (HS 

(WC 6)/NDL)) 

HBPplusHFP (FHSB /FVPP) (DISPC _HSA DISPC _HFP PPL DISPC _HBP) (HS WC 

6)/NDL 

HBPplusHFPf ((FHSB /FVPP) (DISPC _HSA DISPC _HFP PPL DISPC _HBP)) ((HS WC 

6)/NDL) 

HFP (DISPC _HFP BPP)/(NDL 8) (2/NDL) 

HBP HBPplusHFP HFP 



Table 7-109. DSI Timing Registers (continued) 


Enable the ECC generation for the transmit 

header. 

Enable high-speed mode to send short and 

long packets to the peripheral. 

DSI_VC0_CTRL[8] ECC_TX_EN 0x1 

DSI_VC0_CTRL[9] MODE_SPEED 0x1 

Disable DMA request for TX FIFO. DSI_VC0_CTRL[23:21] DMA_TX_REQ_NB 0x4 

Disable DMA request for RX FIFO. DSI_VC0_CTRL[29:27] DMA_RX_REQ_NB 0x4 

Configuration TX and RX FIFO 

Set size of the RX FIFO allocated for VC1 to DSI_RX_FIFO_VC_SIZE[15:12] 

32 x 33 bits. VC1_FIFO_SIZE 

Set size of the TX and TX FIFO allocated for DSI_TX_FIFO_VC_SIZE[15:12] 

VC1 to 96 x 33 bits. VC1_FIFO_SIZE 

7.6.5.1.2.5 Configure DSI_PHY Timing 

Table 7-110 summarizes DSI_PHY timing in the functions of DDR_CLK_P with DDR_CLK_P = 

1000/DSI_DDR_CLK. For more details on timing calculation, see Section 7.4.3.2, Clock Requirements. 

Table 7-110. Configure DSI_PHY Timing 


Settings of the DSI protocol timing. For a 

complete description of timing 

specifications, see Section 7.4.3.2, Clock 

Requirements. 

DSI_PHY_REGISTER0[31:24] REG_THSPREPARE 

CEIL(70 ns/DDR clock period) 

+ 2 

DSI_PHY_REGISTER0[23:16] ceil(175 ns/DDR clock period) 

REG_THSPRPR_THSZERO + 2 

DSI_PHY_REGISTER0[7:0] REG_THSEXIT ceil(145 ns/DDR clock period) 

DSI_PHY_REGISTER0[15:8] REG_THSTRAIL 

0x1 

0x3 

dss-E132 

ceil(60 ns/DDR clock period) + 

5 





Table 7-110. Configure DSI_PHY Timing (continued) 


DSI_PHY_REGISTER2[7:0] REG_TCLKPREPARE ceil(65 ns/DDR clock period) 

DSI_PHY_REGISTER1[7:0] REG_TCLKZERO ceil(265 ns/DDR clock period) 

DSI_PHY_REGISTER1[15:8] REG_TCLKTRAIL 

ceil(60 ns/DDR clock period) + 

2 

DSI_PHY_REGISTER1[20:16] REG_TLPXBY2 ceil(25ns/DDR clock period) 

NOTE: Keep Reserved bits at reset value in the DSI_PHY_REGISTER1 and 

DSI_PHY_REGISTER2 registers. 

7.6.5.1.2.6 Drive Stop State 

Table 7-111 lists the steps to drive the stop state. 

Table 7-111. Drive Stop State 


Force TX stop mode. DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO 0x1 

Wait until FORCE_TX_STOP_MODE_IO = DSI_TIMING1[15] FORCE_TX_STOP_MODE_IO 

0. 

7.6.5.1.3 Initialization of the External MIPI LCD Controller 

Table 7-112 lists the steps to initialize the external MIPI LCD controller. 

Table 7-112. Initialization of the External MIPI LCD Controller 


Reset the MIPI LCD controller using 

GPIO87. 

Wait until initialization of the external MIPI 

LCD controller is finished after power up. 

– 0x1 

– – 

Configure the external MIPI LCD controller. – – 

7.6.5.1.4 Configure the DISPC 

7.6.5.1.4.1 Reset DISPC 

Table 7-113 lists the steps to reset the DISPC. 

Table 7-113. Reset DISPC 


Reset the DISPC. DISPC_SYSCONFIG[1] SOFTRESET 0x1 

Wait until RESETDONE = 1. DISPC_SYSCONFIG[0] RESETDONE 

Disable master interface power 

management. 

DISPC_SYSCONFIG [13:12] MIDLEMODE 0x1 

Disable slave interface power management. DISPC_SYSCONFIG [4:3] SIDLEMODE 0x1 

Disable all DISPC interrupts. DISPC_IRQENABLE[31:0] 0x0 

7.6.5.1.4.2 Configure DISPC Timing, Window, and Color 

Table 7-114 lists the steps to configure the DISPC registers. Table 7-97 lists the steps to configure the 

color space coefficient registers. 

Table 7-115 lists the steps to configure DISPC_CONTROL. 



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Table 7-114. Configure DISPC Registers 


Configure LCD output 

Set the logic clock divisor (LCD). DISPC_DIVISOR[23:16] LCD 0x1 

Set the pixel clock divisor (PCD). DISPC_DIVISOR[7:0] PCD 0x4 

Set the number of lines on the LCD panel. DISPC_SIZE_LCD[26:16] LPP 0x2A7 

Set the number of PPL on the LCD panel. DISPC_SIZE_LCD[10:0] PPL 0x1DF 

Set solid background color. DISPC_DEFAULT_COLOR0 0XFF 

Configure VIDEO pipeline VID1. 

DISPC_VID1_FIFO_THRESHOLD[11:0] 

Set VID1 FIFO low threshold. 0x0C0 

VIDFIFOLOWTHRESHOLD 

DISPC_VID1_FIFO_THRESHOLD[27:16] 

Set VID1 FIFO high threshold. 0xFC0 

VIDFIFOHIGHTHRESHOLD 

Set the X position of the VID1 window. DISPC_VID1_POSITION[10:0] VIDPOSX 0x0 

Set the Y position of the VID1 window. DISPC_VID1_POSITION[26:16] VIDPOSY 0x0 

Set the number of lines of the VID1 window. DISPC_VID1_SIZE[26:16] VIDSIZEY 0x2A7 

Set the number of pixels of the VID1 

window. 

Define the base address of the VID1 frame 

buffer. 

DISPC_VID1_SIZE[10:0] VIDSIZEX 0x1DF 

DISPC_VID1_BA0 0x– 

Table 7-115. Configure DISPC_CONTROL 

Comments Register/Bit Field/Programming Value 

Enable pixel clock free-running. DISPC_CONTROL[27] PCLKFREEENABLE 0x1 

Disable RFBI. 

DISPC_CONTROL[16] GPOUT1 0x1 

DISPC_CONTROL[15] GPOUT0 0x1 

Enable the stall mode. DISPC_CONTROL[11] STALLMODE 0x1 

Select size of DATALINES. DISPC_CONTROL[9:8] TFTDATALINES 0x3 

Select active matrix display operation mode. DISPC_CONTROL[3] STNTFT 0x1 

Disable LCD output interface. DISPC_CONTROL[0] LCDENABLE 0x0 

Update the internal DISPC registers. DISPC_CONTROL[5] GOLCD 0x1 

7.6.5.1.5 Enable Command Mode Using DISPC Video Port 

Table 7-116 lists the steps to enable DISPC to send frames continuously. Two bus turnarounds (BTA) 

must be generated: 

• The first BTA gives bus possession to the display module. 

• The second BTA obtains the TE trigger. 

Table 7-116. Enable Command Mode and Automatic TE 


Insert DCS write memory continue code. DSI_CTRL[25] DCS_CMD_CODE 0x0 

Enable automatic insertion of DCS 

command codes when data is sourced by DSI_CTRL[24] DCS_CMD_ENABLE 0x1 

the video port. 



Enable the interface. DSI_CTRL[0] IF_EN 0x1 

Wait until IF_EN = 1. DSI_CTRL[0] IF_EN 

Send the sequence to receive the TE 

trigger from the peripheral. In this use case, DSI_VC1_SHORT_PACKET_HEADER[31:0] HEADER 0x0000 3515 

code 0x35 + 1 parameter VC = 0, data type 

= 0x15, DCS write + 1 parameter. 




www.ti.com Display Subsystem Register Manual 

Table 7-116. Enable Command Mode and Automatic TE (continued) 


Wait until PACKET_SENT_IRQ = 1. DSI_VC1_IRQSTATUS[2] PACKET_SENT_IRQ 

Write 1 to clear PACKET_SENT_IRQ. DSI_VC1_IRQSTATUS[2] PACKET_SENT_IRQ 0x1 

7.6.5.1.6 Send Frame Data to LCD Panel Using Automatic TE 

Table 7-117 summarizes the steps to send a frame data to the LCD panel using automatic TE. 

Table 7-117. Send Frame Data to LCD Panel Using Automatic TE 


Enable the transfer between DISPC and 

DSI. Reset after the transfer is done. 

DISPC_CONTROL[0] LCDENABLE 0x1 

Specify the number of bytes to send. When 

DCS insertions is used, word count (WC) DSI_VC0_TE[23:0] TE_SIZE (WC+1)*LPP 

must include this one DCS byte. 

Set up long packet header. Send 0x39 

DCS long write/write_LUT command 

packet used to send larger blocks of data DSI_VC0_LONG_PACKET_HEADER[31:0] HEADER (WC+1) 8 + 0x39 

to a display module that implements a 

DCS. 

Enable TE control. DSI_VC0_TE[30] TE_EN 0x1 

Wait until RX FIFO is empty, 

RX_FIFO_NOT_EMPTY = 0. 

Wait until TX FIFO is not full. 

TX_FIFO_FULL = 0. 

DSI_VC1_CTRL[20] RX_FIFO_NOT_EMPTY 0x0 

DSI_VC1_CTRL[16] TX_FIFO_FULL 0x0 

Enable first BTA to give bus possession to DSI_VC1_CTRL[6] BTA_EN 0x1 

the display module. 

Wait until BTA IRQ. DSI_VC1_IRQSTATUS[5] BTA_IRQ 0x1 

Write 1 to clear BTA IRQ. DSI_VC1_IRQSTATUS[5] BTA_IRQ 0x1 

Enable second BTA to get the TE trigger. DSI_VC1_CTRL[6] BTA_EN 0x1 

Wait until BTA IRQ. DSI_VC1_IRQSTATUS[5] BTA_IRQ 0x1 

Write 1 to clear BTA IRQ. DSI_VC1_IRQSTATUS[5] BTA_IRQ 0x1 

Wait until transfer is complete. DSI_VC0_TE[30] TE_EN Read 0x0 

7.7 Display Subsystem Register Manual 

CAUTION 

• The DISS, DISPC, RFBI, and VENC registers have no register data width 

access restriction and can be accessed in 8-bit, 16-bit and 32-bit access. 

• The DSI complex I/O and DSI PLL control module registers are limited to 

32-bit data access; 16-bit and 8-bit data accesses are not allowed and can 

corrupt register content. 

• The DSI protocol engine DSS.DSI_VCn_LONG_PACKET_HEADER and 

DSS.DSI_VCn_SHORT_PACKET_HEADER registers are limited to 32-bit 

data access; 16-bit and 8-bit data accesses are not allowed and can corrupt 

register content. 

• The DSI protocol engine DSS.DSI_VCn_LONG_PACKET_PAYLOAD 

register is limited to 32-bit and 16-bit data access; 8-bit data accesses are 

not allowed and can corrupt register content. 

• All other DSI protocol engine registers have no register data width access 

restriction and can be accessed in 8-bit, 16-bit and 32-bit access. 



1795


Display Subsystem Register Manual www.ti.com 

Table 7-118 summarizes the display subsystem instance. 

Table 7-118. Display Subsystem Instance Summary 

Module Name Base Address Size 

DSI Protocol Engine 0x4804 FC00 512 bytes 

DSI_PHY 0x4804 FE00 64 bytes 

DSI PLL Controller 0x4804 FF00 32 bytes 

Display Subsystem 0x4805 0000 512 bytes 

Display Controller 0x4805 0400 1KB 

Display Controller VID1 0x4805 0400 1KB 

Display Controller VID2 0x4805 0400 1KB 

RFBI 0x4805 0800 256 bytes 

Video Encoder 0x4805 0C00 256 bytes 

7.7.1 Display Subsystem Register Mapping Summary 

7.7.1.1 Display Subsystem Register Mapping Summary 

Table 7-119. Display Subsystem Register Mapping Summary 

Register Name Type Register Width Address Offset Physical Address 

(Bits) 

DSS_REVISIONNUMBER R 32 0x000 0x4805 0000 

DSS_SYSCONFIG RW 32 0x010 0x4805 0010 

DSS_SYSSTATUS R 32 0x014 0x4805 0014 

DSS_IRQSTATUS R 32 0x018 0x4805 0018 

DSS_CONTROL RW 32 0x040 0x4805 0040 

DSS_CLK_STATUS R 32 0x05C 0x4805 005C 

7.7.1.2 Display Controller Register Mapping Summary 

Table 7-120. Display Controller Register Mapping Summary 


(Bits) 

DISPC_REVISION R 32 0x000 0x4805 0400 

DISPC_SYSCONFIG RW 32 0x010 0x4805 0410 

DISPC_SYSSTATUS R 32 0x014 0x4805 0414 

DISPC_IRQSTATUS RW 32 0x018 0x4805 0418 

DISPC_IRQENABLE RW 32 0x01C 0x4805 041C 

DISPC_CONTROL RW 32 0x040 0x4805 0440 

DISPC_CONFIG RW 32 0x044 0x4805 0444 

DISPC_DEFAULT_COLOR_m RW 32 0x04C+(m * 0x04) (1) 0x4805 044C+(m * 

0x04) (1) 

DISPC_TRANS_COLOR_m RW 32 0x054+(m * 0x04) (1) 0x4805 0454+(m * 

0x04) (1) 

DISPC_LINE_STATUS R 32 0x05C 0x4805 045C 

DISPC_LINE_NUMBER RW 32 0x060 0x4805 0460 

DISPC_TIMING_H RW 32 0x064 0x4805 0464 

DISPC_TIMING_V RW 32 0x068 0x4805 0468 

DISPC_POL_FREQ RW 32 0x06C 0x4805 046C 

DISPC_DIVISOR RW 32 0x070 0x4805 0470 

(1) m = 0 to 1 





Table 7-120. Display Controller Register Mapping Summary (continued) 


(Bits) 

DISPC_GLOBAL_ALPHA RW 32 0x074 0x4805 0474 

DISPC_SIZE_DIG RW 32 0x078 0x4805 0478 

DISPC_SIZE_LCD RW 32 0x07C 0x4805 047C 

DISPC_GFX_BAj RW 32 0x080+(j * 0x04) (2) 

0x4805 0480+(j * 0x04) (2) 

DISPC_GFX_POSITION RW 32 0x088 0x4805 0488 

DISPC_GFX_SIZE RW 32 0x08C 0x4805 048C 

DISPC_GFX_ATTRIBUTES RW 32 0x0A0 0x4805 04A0 

DISPC_GFX_FIFO_THRESHOLD RW 32 0x0A4 0x4805 04A4 

DISPC_GFX_FIFO_SIZE_STATUS R 32 0x0A8 0x4805 04A8 

DISPC_GFX_ROW_INC RW 32 0x0AC 0x4805 04AC 

DISPC_GFX_PIXEL_INC RW 32 0x0B0 0x4805 04B0 

DISPC_GFX_WINDOW_SKIP RW 32 0x0B4 0x4805 04B4 

DISPC_GFX_TABLE_BA RW 32 0x0B8 0x4805 04B8 

DISPC_DATA_CYCLEk RW 32 0x1D4+(k * 0x04) (3) 0x4805 05D4+(k * 

0x04) (3) 

DISPC_CPR_COEF_R RW 32 0x220 0x4805 0620 

DISPC_CPR_COEF_G RW 32 0x224 0x4805 0624 

DISPC_CPR_COEF_B RW 32 0x228 0x4805 0628 

DISPC_GFX_PRELOAD RW 32 0x22C 0x4805 062C 

(2) j = 0 to 1 

(3) k = 0 to 2 

7.7.1.3 Display Controller VID1 Register Mapping Summary 

Table 7-121. Display Controller VID1 Register Mapping Summary 

Register Name (n=1 for VID1) Type Register Width Address Offset Display controller VID1 

(Bits) Physical 

Address 

DISPC_VIDn_BAj RW 32 0x0BC+((n–1)* 0x90) + 0x4805 04BC + (j 

(j * 0x04) (1) *0x04) (1) 

DISPC_VIDn_POSITION RW 32 0x0C4+((n–1)* 0x90) 0x4805 04C4 

DISPC_VIDn_SIZE RW 32 0x0C8+((n–1)* 0x90) 0x4805 04C8 

DISPC_VIDn_ATTRIBUTES RW 32 0x0CC+((n–1)* 0x90) 0x4805 04CC 

DISPC_VIDn_FIFO_THRESHOLD RW 32 0x0D0+((n–1)* 0x90) 0x4805 04D0 

DISPC_VIDn_FIFO_SIZE_STATUS R 32 0x0D4+((n–1)* 0x90) 0x4805 04D4 

DISPC_VIDn_ROW_INC RW 32 0x0D8+((n–1)* 0x90) 0x4805 04D8 

DISPC_VIDn_PIXEL_INC RW 32 0x0DC+((n–1)* 0x90) 0x4805 04DC 

DISPC_VIDn_FIR RW 32 0x0E0+((n–1)* 0x90) 0x4805 04E0 

DISPC_VIDn_PICTURE_SIZE RW 32 0x0E4+((n–1)* 0x90) 0x4805 04E4 

DISPC_VIDn_ACCUl RW 32 0x0E8 + ((n–1)* 0x90) 0x4805 04E8 + (l* 0x04) (2) 

+ (l* 0x04) (2) 

DISPC_VIDn_FIR_COEF_Hi RW 32 0x0F0+ ((n–1)* 0x90) + 0x4805 04F0+ (i* 0x08) (3) 

(i* 0x08) (3) 

DISPC_VIDn_FIR_COEF_HVi RW 32 0x0F4+ ((n–1)* 0x90) + 0x4805 04F4 + (i*0x08) (3) 

(i* 0x08) (3) 

DISPC_VIDn_CONV_COEF0 RW 32 0x130+((n–1)* 0x90) 0x4805 0530 


(1) 

(2) 

(3) 

j = 0 to 1 

l = 0 to 1 

i = 0 to 7 





Table 7-121. Display Controller VID1 Register Mapping Summary (continued) 



Address 


DISPC_VIDn_CONV_COEF3 RW 32 0x13C+((n–1)* 0x90) 0x4805 053C 


DISPC_VIDn_FIR_COEF_Vi RW 32 0x1E0+ ((n–1)*0x20) + 0x4805 05E0 + (i* 0x04) (3) 

(i* 0x04) (3) 

DISPC_VIDn_PRELOAD RW 32 0x230+((n–1)* 0x04) 0x4805 0630 

7.7.1.4 Display Controller VID2 Register Mapping Summary 

Table 7-122. Display Controller VID2 Register Mapping Summary 



Address 

DISPC_VIDn_BAj RW 32 0x0BC+((n–1)* 0x90) + 0x4805 054C+ (j *0x04) (1) 

(j * 0x04) (1) 

DISPC_VIDn_POSITION RW 32 0x0C4+((n–1)* 0x90) 0x4805 0554 

DISPC_VIDn_SIZE RW 32 0x0C8+((n–1)* 0x90) 0x4805 0558 

DISPC_VIDn_ATTRIBUTES RW 32 0x0CC+((n–1)* 0x90) 0x4805 055C 

DISPC_VIDn_FIFO_THRESHOLD RW 32 0x0D0+((n–1)* 0x90) 0x4805 0560 

DISPC_VIDn_FIFO_SIZE_STATUS R 32 0x0D4+((n–1)* 0x90) 0x4805 0564 

DISPC_VIDn_ROW_INC RW 32 0x0D8+((n–1)* 0x90) 0x4805 0568 

DISPC_VIDn_PIXEL_INC RW 32 0x0DC+((n–1)* 0x90) 0x4805 056C 

DISPC_VIDn_FIR RW 32 0x0E0+((n–1)* 0x90) 0x4805 0570 

DISPC_VIDn_PICTURE_SIZE RW 32 0x0E4+((n–1)* 0x90) 0x4805 0574 

DISPC_VIDn_ACCUl RW 32 0x0E8 + ((n–1)* 0x90) 0x4805 0578 + (l* 0x04) (2) 

+ (l* 0x04) (2) 

DISPC_VIDn_FIR_COEF_Hi RW 32 0x0F0+ ((n–1)* 0x90) + 0x4805 0580 + (i* 0x08) (3) 

(i* 0x08) (3) 

DISPC_VIDn_FIR_COEF_HVi RW 32 0x0F4+ ((n–1)* 0x90) + 0x4805 0584 + (i*0x08) (3) 

(i* 0x08) (3) 

DISPC_VIDn_CONV_COEF0 RW 32 0x130+((n–1)* 0x90) 0x4805 05C0 



DISPC_VIDn_CONV_COEF3 RW 32 0x13C+((n–1)* 0x90) 0x4805 05CC 

DISPC_VIDn_CONV_COEF4 RW 32 0x140+((n–1)* 0x90) 0x4805 05D0 

DISPC_VIDn_FIR_COEF_Vi RW 32 0x1E0+ ((n–1)*0x20) + 0x4805 0670 + (i* 0x04) (3) 

(i* 0x04) (3) 

DISPC_VIDn_PRELOAD RW 32 0x230+((n–1)* 0x04) 0x4805 0634 

(1) j = 0 to 1 

(2) l = 0 to 1 

(3) i = 0 to 7 

7.7.1.5 RFBI Register Mapping Summary 

Table 7-123. RFBI Register Mapping Summary 


(Bits) 

RFBI_REVISION R 32 0x00 0x4805 0800 

RFBI_SYSCONFIG RW 32 0x10 0x4805 0810 





Table 7-123. RFBI Register Mapping Summary (continued) 


(Bits) 

RFBI_SYSSTATUS R 32 0x14 0x4805 0814 

RFBI_CONTROL RW 32 0x40 0x4805 0840 

RFBI_PIXEL_CNT RW 32 0x44 0x4805 0844 

RFBI_LINE_NUMBER RW 32 0x48 0x4805 0848 

RFBI_CMD W 32 0x4C 0x4805 084C 

RFBI_PARAM W 32 0x50 0x4805 0850 

RFBI_DATA W 32 0x54 0x4805 0854 

RFBI_READ RW 32 0x58 0x4805 0858 

RFBI_STATUS RW 32 0x5C 0x4805 085C 

RFBI_CONFIGi RW 32 0x60+ (i* 0x18) (1) 

RFBI_ONOFF_TIMEi RW 32 0x64+ (i* 0x18) (1) 

RFBI_CYCLE_TIMEi RW 32 0x68+ (i* 0x18) (1) 

0x4805 0860+ (i* 0x18) (1) 

0x4805 0864+ (i* 0x18) (1) 

0x4805 0868+ (i* 0x18) (1) 

RFBI_DATA_CYCLE1_i RW 32 0x6C+ (i* 0x18) (2) 0x4805 086C+ (i* 0x18) (2) 

RFBI_DATA_CYCLE2_i RW 32 0x70+ (i* 0x18) (2) 0x4805 0870+ (i* 0x18) (2) 

RFBI_DATA_CYCLE3_i RW 32 0x74+ (i* 0x18) (2) 0x4805 0874+ (i* 0x18) (2) 

RFBI_VSYNC_WIDTH RW 32 0x90 0x4805 0890 

RFBI_HSYNC_WIDTH RW 32 0x94 0x4805 0894 

(1) i = 0 to 1 

(2) i = 0 to 1 

7.7.1.6 Video Encoder Register Mapping Summary 

Table 7-124. Video Encoder Register Mapping Summary 


(Bits) 

VENC_REV_ID R 32 0x00 0x4805 0C00 

VENC_STATUS R 32 0x04 0x4805 0C04 

VENC_F_CONTROL RW 32 0x08 0x4805 0C08 

VENC_VIDOUT_CTRL RW 32 0x10 0x4805 0C10 

VENC_SYNC_CTRL RW 32 0x14 0x4805 0C14 

VENC_LLEN RW 32 0x1C 0x4805 0C1C 

VENC_FLENS RW 32 0x20 0x4805 0C20 

VENC_HFLTR_CTRL RW 32 0x24 0x4805 0C24 

VENC_CC_CARR_WSS_CARR RW 32 0x28 0x4805 0C28 

VENC_C_PHASE RW 32 0x2C 0x4805 0C2C 

VENC_GAIN_U RW 32 0x30 0x4805 0C30 

VENC_GAIN_V RW 32 0x34 0x4805 0C34 

VENC_GAIN_Y RW 32 0x38 0x4805 0C38 

VENC_BLACK_LEVEL RW 32 0x3C 0x4805 0C3C 

VENC_BLANK_LEVEL RW 32 0x40 0x4805 0C40 

VENC_X_COLOR RW 32 0x44 0x4805 0C44 

VENC_M_CONTROL RW 32 0x48 0x4805 0C48 

VENC_BSTAMP_WSS_DATA RW 32 0x4C 0x4805 0C4C 

VENC_S_CARR RW 32 0x50 0x4805 0C50 

VENC_LINE21 RW 32 0x54 0x4805 0C54 

VENC_LN_SEL RW 32 0x58 0x4805 0C58 

VENC_L21_WC_CTL RW 32 0x5C 0x4805 0C5C 





Table 7-124. Video Encoder Register Mapping Summary (continued) 


(Bits) 

VENC_HTRIGGER_VTRIGGER RW 32 0x60 0x4805 0C60 

VENC_SAVID_EAVID RW 32 0x64 0x4805 0C64 

VENC_FLEN_FAL RW 32 0x68 0x4805 0C68 

VENC_LAL_PHASE_RESET RW 32 0x6C 0x4805 0C6C 

VENC_HS_INT_START_STOP_X RW 32 0x70 0x4805 0C70 

VENC_HS_EXT_START_STOP_X RW 32 0x74 0x4805 0C74 

VENC_VS_INT_START_X RW 32 0x78 0x4805 0C78 

VENC_VS_INT_STOP_X_VS_INT_START_Y RW 32 0x7C 0x4805 0C7C 

VENC_VS_INT_STOP_Y_VS_EXT_START_X RW 32 0x80 0x4805 0C80 

VENC_VS_EXT_STOP_X_VS_EXT_START_Y RW 32 0x84 0x4805 0C84 

VENC_VS_EXT_STOP_Y RW 32 0x88 0x4805 0C88 

VENC_AVID_START_STOP_X RW 32 0x90 0x4805 0C90 

VENC_AVID_START_STOP_Y RW 32 0x94 0x4805 0C94 

VENC_FID_INT_START_X_FID_INT_START_Y RW 32 0xA0 0x4805 0CA0 

VENC_FID_INT_OFFSET_Y_FID_EXT_START_ RW 32 0xA4 0x4805 0CA4 

X 

VENC_FID_EXT_START_Y_FID_EXT_OFFSET RW 32 0xA8 0x4805 0CA8 

_Y 

VENC_TVDETGP_INT_START_STOP_X RW 32 0xB0 0x4805 0CB0 

VENC_TVDETGP_INT_START_STOP_Y RW 32 0xB4 0x4805 0CB4 

VENC_GEN_CTRL RW 32 0xB8 0x4805 0CB8 

VENC_OUTPUT_CONTROL RW 32 0xC4 0x4805 0CC4 

VENC_OUTPUT_TEST RW 32 0xC8 0x4805 0CC8 

7.7.1.7 DSI Protocol Engine Register Mapping Summary 

Table 7-125. DSI Protocol Engine Register Mapping Summary 

Register Name Type Register Width (Bits) Address Offset Physical Address 

DSI_REVISION R 32 0x000 0x4804 FC00 

DSI_SYSCONFIG RW 32 0x010 0x4804 FC10 

DSI_SYSSTATUS R 32 0x014 0x4804 FC14 

DSI_IRQSTATUS RW 32 0x018 0x4804 FC18 

DSI_IRQENABLE RW 32 0x01C 0x4804 FC1C 

DSI_CTRL RW 32 0x040 0x4804 FC40 

DSI_COMPLEXIO_CFG RW 32 0x048 0x4804 FC48 

1 

DSI_COMPLEXIO_IRQ RW 32 0x04C 0x4804 FC4C 

STATUS 

DSI_COMPLEXIO_IRQ RW 32 0x050 0x4804 FC50 

ENABLE 

DSI_CLK_CTRL RW 32 0x054 0x4804 FC54 

DSI_TIMING1 RW 32 0x058 0x4804 FC58 

DSI_TIMING2 RW 32 0x05C 0x4804 FC5C 

DSI_VM_TIMING1 RW 32 0x060 0x4804 FC60 



DSI_CLK_TIMING RW 32 0x06C 0x4804 FC6C 

DSI_TX_FIFO_VC_SIZE RW 32 0x070 0x4804 FC70 





Table 7-125. DSI Protocol Engine Register Mapping Summary (continued) 


DSI_RX_FIFO_VC_SIZ RW 32 0x074 0x4804 FC74 

E 

DSI_COMPLEXIO_CFG RW 32 0x078 0x4804 FC78 

2 

DSI_RX_FIFO_VC_FUL R 32 0x07C 0x4804 FC7C 

LNESS 


DSI_TX_FIFO_VC_EMP R 32 0x084 0x4804 FC84 

TINESS 


DSI_VM_TIMING6 RW 32 0x08C 0x4804 FC8C 


DSI_STOPCLK_TIMING RW 32 0x094 0x4804 FC94 

DSI_VCn_CTRL RW 32 0x100+ (n* 0x20) (1) 

0x4804 FD00+ (n* 

0x20) (1) 

DSI_VCn_TE RW 32 0x104+ (n* 0x20) (1) 0x4804 FD04+ (n* 

0x20) (1) 

DSI_VCn_LONG_PACK W 32 0x108+ (n* 0x20) (1) 0x4804 FD08+ (n* 

ET_HEADER 0x20) (1) 

DSI_VCn_LONG_PACK W 32 0x10C+ (n* 0x20) (1) 0x4804 FD0C+ (n* 

ET_PAYLOAD 0x20) (1) 

DSI_VCn_SHORT_PAC RW 32 0x110+ (n* 0x20) (1) 0x4804 FD10+ (n* 

KET_HEADER 0x20) (1) 

DSI_VCn_IRQSTATUS RW 32 0x118+ (n* 0x20) (1) 0x4804 FD18+ (n* 

0x20) (1) 

DSI_VCn_IRQENABLE RW 32 0x11C+ (n* 0x20) (1) 0x4804 FD1C+ (n* 

0x20) (1) 

(1) n = 0 to 3 

7.7.1.8 DSI_PHY Register Mapping Summary 

Table 7-126. DSI_PHY Register Mapping Summary 


DSI_PHY_REGISTER0 RW 32 0x0000 0000 0x4804 FE00 



DSI_PHY_REGISTER3 RW 32 0x0000 000C 0x4804 FE0C 


DSI_PHY_REGISTER5 R 32 0x0000 0014 0x4804 FE14 

7.7.1.9 DSI PLL Controller Register Mapping Summary 

Table 7-127. DSI PLL Controller Register Mapping Summary 


DSI_PLL_CONTROL RW 32 0x0000 0000 0x4804 FF00 

DSI_PLL_STATUS R 32 0x0000 0004 0x4804 FF04 

DSI_PLL_GO RW 32 0x0000 0008 0x4804 FF08 

DSI_PLL_CONFIGURA RW 32 0x0000 000C 0x4804 FF0C 

TION1 

DSI_PLL_CONFIGURA RW 32 0x0000 0010 0x4804 FF10 

TION2 





7.7.2 Display Subsystem Register Descriptions 

7.7.2.1 Display Subsystem Registers 

Address Offset 0x000 

Table 7-128. DSS_REVISIONNUMBER 

Physical address 0x4805 0000 Instance DISS 

Description This register contains the display subsystem revision number. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved REV 

Bits Field Name Description Type Reset 

31:8 Reserved Read returns 0. R 0x000000 

7:0 REV Revision number R TI internal data 

[7:4] Major revision 

[3:0] Minor revision 

Table 7-129. Register Call Summary for Register DSS_REVISIONNUMBER 

Display Subsystem Register Manual 

• Display Subsystem Register Mapping Summary: [0] 


Table 7-130. DSS_SYSCONFIG 


Description This register controls the various parameters of the interconnect interface. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 


31:5 Reserved Write 0s for future compatibility. Reads return zero. RW 0x00000000 

4:3 Reserved Reserved. Keep at reset value. RW 0x0 

2 Reserved Write 0s for future compatibility . Reads return zero. RW 0 

1 SOFTRESET Software reset. Set this bit to 1 to trigger a module reset. The bit is RW 0 

automatically reset by the hardware. During reads, it always returns 

0. 

0x0: Normal mode 

0x1: The module is reset 

0 AUTOIDLE Enable power management capability RW 1 

0x0: OCP clock is free-running 

0x1: Automatic OCP clock gating strategy is applied based on 

the OCP interface activity 



Reserved 

Reserved 

SOFTRESET 

AUTOIDLE



Display Subsystem Integration 

• Software Reset: [0] 

• Autoidle Mode: [1] 

• DISPC Interrupt Request: [2] 

Table 7-131. Register Call Summary for Register DSS_SYSCONFIG 

Display Subsystem Basic Programming Model 

• Display Subsystem Reset: [3] 

Display Subsystem Use Cases and Tips 

• Autoidle: [4] 

• Smart-Idle: [5] 




Table 7-132. DSS_SYSSTATUS 


Description This register provides status information about the module. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 



0 RESETDONE Internal reset monitoring R 1 



Read 0x0: Internal module reset is ongoing. 

Read 0x1: Reset completed 

Table 7-133. Register Call Summary for Register DSS_SYSSTATUS 





Address Offset 0x0000 0018 

Table 7-134. DSS_IRQSTATUS 

Physical Address 0x4805 0018 Instance DSS 

Description The register indicates the source of the interrupt and the status of the interrupt line. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 



DSI_IRQ 

RESETDONE 

DISPC_IRQ 

1803




31:2 RESERVED Reads returns 0. R 0x00000000 

1 DSI_IRQ DSI interrupt status (related to DSI_IRQSTATUS) R 0x0 

0x0: DSI interrupt inactive 

0x1: DSI interrupt active 

0 DISPC_IRQ DISPC interrupt status (related to DISPC_IRQSTATUS) R 0x0 

0x0: DISPC interrupt inactive 

0x1: DISPC interrupt active 

Table 7-135. Register Call Summary for Register DSS_IRQSTATUS 




Table 7-136. DSS_CONTROL 


Description This register contains the display subsystem control bits. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 


31:7 Reserved Reserved for future DAC use RW 0x0000000 

6 VENC_OUT_SEL Video DAC1 input selection: RW 0 

0x0: CVBS VENC output selected for composite video 

mode 

0x1: Luminance VENC output selected for s-video mode 

5 DAC_POWERDN_BGZ DAC Power-Down Control RW 0 

0x0: DAC Power-Down Band Gap powered down 

0x1: DAC Power-Down Band Gap powered up 

4 DAC_DEMEN DAC dynamic element matching enable RW 0 

0x0: DAC Dynamic Element Matching Disabled 

0x1: DAC Dynamic Element Matching Enabled 

3 VENC_CLOCK_4X_ VENC clock 4x enable RW 0 

ENABLE 0x0: Disable 

0x1: Enable 

2 VENC_CLOCK_MODE VENC clock mode. See Table 7-20, Possible Digital RW 0 

Clock Division for the Video Encoder. 

0x0: Mode 0. All three balanced clocks, derived from the 

DSS_TV_CLK clock, are provided to the VENC, if the 

VENC_CLOCK_4X_ENABLE bit [3] is set to 1 by 

software. 

0x1: Mode 1. The VENC_CLOCK_4X_ENABLE bit [3] is 

used to control clock gating. 



VENC_OUT_SEL 

DAC_POWERDN_BGZ 

DAC_DEMEN 

VENC_CLOCK_4X_ ENABLE 

VENC_CLOCK_MODE 

DSI_CLK_SWITCH 

DISPC_CLK_SWITCH




1 DSI_CLK_SWITCH Selects the clock source for the DSI functional clock RW 0 

0x0: DSS1_ALWON_FCLK clock is selected (from 

PRCM) 

0x1: DSI2_PLL_FCLK clock is selected (from DSI PLL) 

0 DISPC_CLK_SWITCH Selects the clock source for the DISPC functional clock RW 0 

0x0: DSS1_ALWON_FCLK clock is selected (from 

PRCM) 

0x1: DSI1_PLL_FCLK clock is selected (from DSI PLL) 

Display Subsystem Environment 

• TV Display Support: [0] 

• Digital-to-Analog Converters: [1] 


• Clocks: [2] [3] [4] [5] [6] [7] 

Table 7-137. Register Call Summary for Register DSS_CONTROL 

Display Subsystem Functional Description 

• Video Encoder Functionalities: [8] 

• Video DAC Stage Power Management: [9] [10] 


• Display Subsystem Configuration Phase: [11] [12] [13] [14] 

• Video DAC Stage Settings: [15] 


• Display Subsystem Clock Configuration: [16] [17] [18] 

• DPLL4 in Low-Power Mode: [19] [20] 

• Switch to DSI PLL Clock Source: [21] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [22] [23] 



Address Offset 0x05C 

Table 7-138. DSS_CLK_STATUS 

Physical address 0x4805 005C Instance DISS 

Description This register contains the display subsystem register. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED RESERVED 


31:9 RESERVED RESERVED R 0x0000000 

8 DSI_PLL_CLK2_ DSI2_PLL_FCLK clock selection status (DSI mux) Indicates if R 0 

STATUS the DSI protocol engine is running from the DSI2_PLL_FCLK 

clock 

Read 0: DSI2_PLL_FCLK is not selected (unused by DSI). 

Read 1: DSI2_PLL_FCLK is selected (used by DSI). 



DSI_PLL_CLK2_STATUS 

DSS_DSI_CLK1_STATUS 

DSI_PLL_CLK1_STATUS 

DSS_DISPC_CLK1_STATUS 

1805




7 DSS_DSI_CLK1_ DSS1_ALWON_FCLK clock selection status (DSI mux) R 0 

STATUS Indicates if the DSI protocol engine is running from the 

DSS1_ALWON_FCLK clock 

Read 0: DSS1_ALWON_FCLK is not selected (unused by DSI). 

Read 1: DSS1_ALWON_FCLK is selected (used by DSI). 

6:2 RESERVED RESERVED R 0 

1 DSI_PLL_CLK1_ DSI1_PLL_FCLK clock selection status (DISPC mux) Indicates if R 0 

STATUS the display controller is running from the DSI1_PLL_FCLK clock 

Read 0: DSI1_PLL_FCLK is not selected (unused by DISPC). 

Read 1: DSI1_PLL_FCLK is selected (used by DISPC). 

0 DSS_DISPC_CLK1_ DSS1_ALWON_FCLK clock selection status (DISPC mux) R 1 

STATUS Indicates if the display controller is running from the 

DSS1_ALWON_FCLK clock 

Read 0: DSS1_ALWON_FCLK is not selected (unused by 

DISPC). 

Read 1: DSS1_ALWON_FCLK is selected (used by DISPC). 

Table 7-139. Register Call Summary for Register DSS_CLK_STATUS 



7.7.2.2 Display Controller Registers 


Table 7-140. DISPC_REVISION 

Physical address 0x4805 0400 Instance DISC 

Description This register contains the IP revision code. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved REV 


31:8 Reserved Write 0s for future compatibility. Read returns 0. R 0x000000 

7:0 REV IP revision R TI internal data 



Table 7-141. Register Call Summary for Register DISPC_REVISION 


• Display Controller Register Mapping Summary: [0] 


Table 7-142. DISPC_SYSCONFIG 


Description This register allows the control of various parameters of the interconnect interface. 

Type RW 





31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved Reserved 


31:14 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00000 

13:12 MIDLEMODE Master interface power management, standby/waitcontrol RW 0x0 

MIDLEMODE 

Reserved 

CLOCKACTIVITY 

0x0: Force standby. MStandby is asserted only when the 

module is disabled. 

0x1: No standby: MStandby is never asserted. 

0x2: Smart Standby. MStandby is asserted based on the 

internal activity of the module. 

0x3: Reserved 


9:8 CLOCKACTIVITY Clock activity during wakeup mode period RW 0x0 

0x0: interface and functional clocks can be switched off. 

0x1: Functional clocks can be switched off and interface 

clocks are maintained during wakeup period. 

0x2: Interface clocks can be switched off and functional clocks 

are maintained during wakeup period. 

0x3: Interface and functional clocks are maintained during 

wakeup period. 


4:3 SIDLEMODE Slave interface power management, idle req/ack control RW 0x0 

0x0: Force idle. An idle request is acknowledged 

unconditionally. 

0x1: No idle. An idle request is never acknowledged. 

0x2: Smart idle. Idle request is acknowledged based on the 

internal activity of the module. 

0x3: Reserved 

2 ENWAKEUP Wakeup feature control RW 0 

0x0: Wakeup is disabled. 

0x1: Wakeup is enabled. 

1 SOFTRESET Software reset. Set this bit to 1 to trigger a module reset. The bit is RW 0 

automatically reset by the hardware. During reads, it always returns 

0. 

0x0: Normal mode 

0x1: The module is reset. 

0 AUTOIDLE Internal interface clock gating strategy RW 1 

0x0: Interface clock is free-running. 

0x1: Automatic L3 and L4 interface clock gating strategy is 

applied based on interface activity. 



SIDLEMODE 

ENWAKEUP 

SOFTRESET 

AUTOIDLE 




Table 7-143. Register Call Summary for Register DISPC_SYSCONFIG 



• Clock Activity Mode: [1] [2] [3] [4] [5] 


• Idle Mode: [7] [8] [9] 

• Wake-Up Mode: [10] 

• Standby Mode: [11] 


• Display Controller Configuration: [12] 




• Reset DISPC: [15] [16] [17] [18] 

• Configure the DISPC: [19] [20] [21] [22] 




Table 7-144. DISPC_SYSSTATUS 


Description This register provides status information about the module, excluding interrupt status information. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 




7:1 Reserved Reserved. Read returns 0. R 0x00 


Read 0x0: Internal module reset is ongoing. 

Read 0x1: Reset complete 

Table 7-145. Register Call Summary for Register DISPC_SYSSTATUS 







RESETDONE




Table 7-146. DISPC_IRQSTATUS 


Description This register regroups all the status of module internal events that generate an interrupt. A write of 1 to a given bit 

resets the bit. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

WAKEUP 


31:17 Reserved Write 0s for future compatibility. RW 0x0000 

Read returns 0 

16 WAKEUP Wakeup RW 0 

SYNCLOSTDIGITAL 

Read 0x0: Wakeup is false. 

SYNCLOST 

VID2ENDWINDOW 

VID2FIFOUNDERFLOW 

Write 0x0: Wakeup status bit unchanged 

Read 0x1: Wakeup is true (pending). 

Write 0x1: Wakeup status bit reset 

15 SYNCLOSTDIGITAL SyncLostDigital RW 0 

Read 0x0: SyncLostDigital is false. 

VID1ENDWINDOW 


Write 0x0: SyncLostDigital status bit unchanged 

Read 0x1: SyncLostDigital is true (pending). 

Write 0x1: SyncLostDigital status bit reset 

14 SYNCLOST SyncLost RW 0 

Read 0x0: SyncLost is false. 

Write 0x0: SyncLost status bit unchanged 

Read 0x1: SyncLost is true (pending). 

Write 0x1: SyncLost status bit reset 

13 VID2ENDWINDOW Vid2EndWindow RW 0 

Read 0x0: Vid2EndWindow is false. 

Write 0x0: Vid2EndWindow status bit unchanged 

Read 0x1: Vid2EndWindow is true (pending). 

Write 0x1: Vid2EndWindow status bit reset 

12 VID2FIFOUNDERFLOW Vid2FIFOUnderflow RW 0 

Read 0x0: Vid2FIFOUnderflow is false. 

OCPERROR 

Write 0x0: Vid2FIFOUnderflow status bit unchanged 

Read 0x1: Vid2FIFOUnderflow is true (pending). 

Write 0x1: Vid2FIFOUnderflow status bit reset 


Read 0x0: Vid1EndWindow is false. 

Write 0x0: Vid1EndWindow status bit unchanged 

Read 0x1: Vid1EndWindow is true (pending). 



PALETTEGAMMALOADING 

GFXENDWINDOW 

GFXFIFOUNDERFLOW 

PROGRAMMEDLINENUMBER 

ACBIASCOUNTSTATUS 

EVSYNC_ODD 

EVSYNC_EVEN 

VSYNC 

FRAMEDONE 

1809




Write 0x1: Vid1EndWindow status bit reset 


Read 0x0: Vid1FIFOUnderflow is false. 

Write 0x0: Vid1FIFOUnderflow status bit unchanged 

Read 0x1: Vid1FIFOUnderflow is true (pending). 

Write 0x1: Vid1FIFOUnderflow status bit reset 

9 OCPERROR OCPError RW 0 

Read 0x0: OCPError is false. 

Write 0x0: OCPError status bit unchanged 

Read 0x1: OCPError is true (pending). 

Write 0x1: OCPError status bit reset 

8 PALETTEGAMMA PaletteGammaLoading RW 0 

LOADING 

Read 0x0: PaletteGammaLoading is false. 

Write 0x0: PaletteGammaLoading status bit unchanged 

Read 0x1: PaletteGammaLoading is true (pending). 

Write 0x1: PaletteGammaLoading status bit reset 

7 GFXENDWINDOW GfxEndWindow RW 0 

Read 0x0: GfxEndWindow is false. 

Write 0x0: GfxEndWindow status bit unchanged 

Read 0x1: GfxEndWindow is true (pending). 

Write 0x1: GfxEndWindow status bit reset 

6 GFXFIFOUNDERFLOW GfxFIFOUnderflow RW 0 

Read 0x0: GfxFIFOUnderflow is false. 

Write 0x0: GfxFIFOUnderflow status bit unchanged 

Read 0x1: GfxFIFOUnderflow is true (pending). 

Write 0x1: GfxFIFOUnderflow status bit reset 

5 PROGRAMMEDLINE ProgrammedLineNumber RW 0 

NUMBER 

Read 0x0: ProgrammedLineNumber is false. 

Write 0x0: ProgrammedLineNumber status bit unchanged 

Read 0x1: ProgrammedLineNumber is true (pending). 

Write 0x1: ProgrammedLineNumber status bit reset 

4 ACBIASCOUNTSTATUS ACBiasCountStatus RW 0 

Read 0x0: ACBiasCountStatus is false. 

Write 0x0: ACBiasCountStatus status bit unchanged 

Read 0x1: ACBiasCountStatus is true (pending). 

Write 0x1: ACBiasCountStatus status bit reset 

3 EVSYNC_ODD EVSYNC_ODD RW 0 

Read 0x0: EVSYNC_ODD is false. 

Write 0x0: EVSYNC_ODD status bit unchanged 

Read 0x1: EVSYNC_ODD is true (pending). 

Write 0x1: EVSYNC_ODD status bit reset 

2 EVSYNC_EVEN EVSYNC_EVEN RW 0 

Read 0x0: EVSYNC_EVEN is false. 

Write 0x0: EVSYNC_EVEN status bit unchanged 

Read 0x1: EVSYNC_EVEN is true (pending). 

Write 0x1: EVSYNC_EVEN status bit reset 

1 VSYNC VSYNC RW 0 

Read 0x0: VSYNC is false. 






Write 0x0: VSYNC status bit unchanged 

Read 0x1: VSYNC is true (pending). 

Write 0x1: VSYNC status bit reset 

0 FRAMEDONE FrameDone RW 0 


• DISPC Interrupt Request: [0] [1] 

Read 0x0: FrameDone is false. 

Write 0x0: FrameDone status bit unchanged 

Read 0x1: FrameDone is true (pending). 

Write 0x1: FrameDone status bit reset 

Table 7-147. Register Call Summary for Register DISPC_IRQSTATUS 


• Display Subsystem Reset: [2] [3] 


• TV Set-Specific Control Registers: [5] 

• Video Encoder Programming Sequence: [6] 



• Display Subsystem Registers: [8] 


Table 7-148. DISPC_IRQENABLE 

Physical address 0x4805 041C Instance DISC 

Description This register allows the masking/unmasking of module internal interrupt sources, on an event-by-event basis. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

WAKEUP 



16 WAKEUP Wakeup mask RW 0 

SYNCLOSTDIGITAL 

0x0: Wakeup is masked. 

SYNCLOST 

VID2ENDWINDOW 


ENDVID1WINDOW 


0x1: Wakeup generates an interrupt when it occurs. 

15 SYNCLOSTDIGITAL SyncLostDigital RW 0 

0x0: SyncLostDigital is masked. 

OCPERROR 

PALETTEGAMMAMASK 

0x1: SyncLostDigital generates an interrupt when it occurs. 

14 SYNCLOST SyncLost RW 0 

0x0: SyncLost is masked. 

0x1: SyncLost generates an interrupt when it occurs. 



GFXENDWINDOW 

GFXFIFOUNDERFLOW 

PROGRAMMEDLINENUMBER 

ACBIASCOUNTSTATUS 

EVSYNC_ODD 

EVSYNC_EVEN 

VSYNC 

FRAMEMASK 

1811





0x0: Vid2EndWindow is masked. 

0x1: Vid2EndWindow generates an interrupt when it occurs. 


0x0: Vid2FIFOUnderflow is masked. 

0x1: Vid2FIFOUnderflow generates an interrupt when it 

occurs. 

11 ENDVID1WINDOW EndVid1Window RW 0 

0x0: EndVid1Window is masked. 

0x1: EndVid1Window generates an interrupt when it occurs. 


0x0: Vid1FIFOUnderflow is masked. 

0x1: Vid1FIFOUnderflow generates an interrupt when it 

occurs. 

9 OCPERROR OCPError RW 0 

0x0: OCPError is masked. 

0x1: OCPError generates an interrupt when it occurs. 

8 PALETTEGAMMAMASK PaletteGammaMask RW 0 

0x0: PaletteGammaMask is masked. 

0x1: PaletteGammaMask generates an interrupt when it 

occurs. 

7 GFXENDWINDOW GfxEndWindow RW 0 

0x0: GfxEndWindow is masked. 

0x1: GfxEndWindow generates an interrupt when it occurs. 

6 GFXFIFOUNDERFLOW GfxFIFOUnderflow RW 0 

0x0: GfxFIFOUnderflow is masked. 

0x1: GfxFIFOUnderflow generates an interrupt when it 

occurs. 

5 PROGRAMMEDLINE ProgrammedLineNumber RW 0 

NUMBER 

0x0: ProgrammedLineNumber is masked. 

0x1: ProgrammedLineNumber generates an interrupt when it 

occurs. 

4 ACBIASCOUNTSTATUS ACBiasCountStatus RW 0 

0x0: ACBiasCountStatus is masked. 

0x1: ACBiasCountStatus generates an interrupt when it 

occurs. 

3 EVSYNC_ODD EVSYNC_ODD RW 0 

0x0: EVSYNC_ODD is masked. 

0x1: EVSYNC_ODD generates an interrupt when it occurs. 

2 EVSYNC_EVEN EVSYNC_EVEN RW 0 

0x0: EVSYNC_EVEN is masked. 

0x1: EVSYNC_EVEN generates an interrupt when it occurs. 

1 VSYNC VSYNC RW 0 

0x0: VSYNC is masked. 

0x1: VSYNC generates an interrupt when it occurs. 

0 FRAMEMASK FrameMask RW 0 

0x0: FrameMask is masked. 

0x1: FrameMask generates an interrupt when it occurs. 







Table 7-149. Register Call Summary for Register DISPC_IRQENABLE 




• Video Encoder Programming Sequence: [4] [5] [6] 


• Reset DISPC: [7] 

• Configure the DISPC: [8] 




Table 7-150. DISPC_CONTROL 


Description The control register configures the display controller module. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

SPATIALTEMPORALDITHERINGFRAMES 

LCDENABLEPOL 

LCDENABLESIGNAL 

PCKFREEENABLE 

TDMUNUSEDBITS 

TDMCYCLEFORMAT 

TDMPARALLELMODE 

TDMENABLE 

HT 

GPOUT1 


31:30 SPATIALTEMPORAL Spatial/Temporal dithering number of frames RW 0x0 

DITHERINGFRAMES wr: VFP 

0x0: Spatial only 

GPOUT0 

GPIN1 

GPIN0 

OVERLAYOPTIMIZATION 

0x1: Spatial and temporal over two frames 

STALLMODE 

0x2: Spatial and temporal over four frames 

0x3: Reserved 

29 LCDENABLEPOL LCD Enable Signal Polarity RW 0 

0x0: Active low 

0x1: Active high 

28 LCDENABLESIGNAL LCD Enable Signal: LCD interface active/inactive RW 0 

0x0: Signal disabled 

0x1: Signal enabled 

27 PCKFREEENABLE Pixel clock free-running enabled/disabled RW 0 

0x0: Clock disabled 

0x1: Clock enabled 

26:25 TDMUNUSEDBITS State of unused bits (TDM mode only) RW 0x0 

WR: VFP 


Reserved 


TFTDATALINES 

STDITHERENABLE 

GODIGITAL 

GOLCD 

M8B 

STNTFT 

MONOCOLOR 

DIGITALENABLE 

LCDENABLE 

1813




0x0: Low level (0) 

0x1: High level (1) 

0x2: Unchanged from previous state 

0x3: Reserved 

24:23 TDMCYCLEFORMAT Cycle format (TDM mode only) RW 0x0 

WR: VFP 

0x0: 1 cycle for 1 pixel 

0x1: 2 cycles for 1 pixel 

0x2: 3 cycles for 1 pixel 

0x3: 3 cycles for 2 pixels 

22:21 TDMPARALLELMODE Output Interface width (TDM mode only) RW 0x0 

WR: VFP 

0x0: 8-bit parallel output interface selected 




20 TDMENABLE Enable the multiple cycle format (TDM mode used only for Active RW 0 

Matrix mode with the RFBI enable bit off). 

WR: VFP 

0x0: TDM disabled 

0x1: TDM enabled 

19:17 HT Hold Time for digital output RW 0x0 

WR: EVSYNC 

Encoded value (from 0 to 7) holds time for digital output. The data 

will be held for (HT + 1) external digital clock periods. 

16 GPOUT1 General Purpose Output Signal RW 0 

0x0: The GPout1 is reset. 

0x1: The GPout1 is set. 

15 GPOUT0 General Purpose Output Signal RW 0 

0x0: The GPout0 is reset. 

0x1: The GPout0 is set. 

14 GPIN1 General Purpose Input Signal R 0 

WR: VFP 

Read The GPin1 has been reset. 

0x0: 

Read The GPin1 has been set. 

0x1: 

13 GPIN0 General Purpose Input Signal R 0 

WR: VFP 

Read The GPin0 has been reset. 

0x0: 

Read The GPin0 has been set. 

0x1: 

12 OVERLAYOPTIMI Overlay Optimization (available when graphics format is NOT is RW 0 

ZATION 1-, 2, and 4-BPP) 

WR: VFP or EVSYNC 

0x0: Graphics data below video1 window fetched from 

memory or no overlap between graphics and video1 

windows. 

0x1: Graphics data below video1 window not fetched from 

memory. 

11 STALLMODE Stall mode for the LCD output RW 0 

wr: VFP 

0x0: Normal mode selected 






0x1: Stall mode selected. The Display Controller sends the 

data without considering the VSYNC/HSYNC. The LCD 

output is disabled at the end of the transfer of the 

frame. The S/W has to re-enable the LCD output to 

generate a new frame. The stall mode is used in RFBI 

and DSI command modes. 

10 Reserved Reserved for non-GP devices RW 0 

9:8 TFTDATALINES Number of lines of the LCD interface RW 0x0 

WR: VFP 

0x0: 12-bit output aligned on the LSB of the pixel data 

interface 


interface 


interface 


interface 

7 STDITHERENABLE Spatial temporal dithering enable RW 0 

WR: VFP 

0x0: Spatial/temporal dithering logic disabled 

0x1: Spatial/temporal dithering logic enabled 

6 GODIGITAL Digital GO Command RW 0 

0x0: The hardware has finished updating the internal shadow 

registers of the pipeline(s) associated with the digital 

output using the user values. The hardware resets the 

bit when the update is completed. 

0x1: Users have finished programming the shadow registers 

of the pipeline(s) associated with the digital output and 

the hardware can update the internal registers at the 

external VSYNC. 

5 GOLCD LCD GO Command RW 0 

0x0: The hardware has finished updating the internal shadow 

registers of the pipeline(s) connected to the LCD output 

using the user values. The hardware resets the bit when 

the update is completed. 

0x1: Users have finished programming the shadow registers 

of the pipeline(s) associated with the LCD output and 

the hardware can update the internal registers at the 

VFP start period. 

4 M8B Mono 8-bit mode RW 0 

WR: VFP 

0x0: Pixel data [3:0] is used to output four pixel values to the 

panel at each pixel clock transition (only in Passive 

Mono 8-bit mode). 

0x1: Pixel data [7:0] is used to output eight pixel values to 

the panel each pixel clock transition (only in Passive 

Mono 8-bit mode). 

3 STNTFT LCD display type RW 0 

WR: VFP 

0x0: Passive or Passive Matrix display operation enabled. 

Passive Matrix dither logic enabled. 

0x1: Active Matrix display operation enabled. Passive Matrix 

Dither logic and output FIFO bypassed. 

2 MONOCOLOR Monochrome/Color RW 0 

WR: VFP 

0x0: Color operation enabled (Passive Matrix mode only) 

0x1: Monochrome operation enabled (Passive Matrix mode 

only) 

1 DIGITALENABLE Digital enable RW 0 



1815




0x0: Digital output disabled (at the end of the current field if 

interlace output when the bit is reset) 

0x1: Digital output enabled 

0 LCDENABLE LCD enable RW 0 

0x0: LCD output disabled (at the end of the frame when the 

bit is reset) 

0x1: LCD output enabled 

Table 7-151. Register Call Summary for Register DISPC_CONTROL 


• Parallel Interface: [0] [1] [2] 

• Transaction Timing Diagrams: [3] 

• Video Port Used on Command Mode: [4] 


• Clocks: [5] 



• Overlay Support: [8] 

• Multiple Cycle Output Format: [9] 

• Command Mode: [10] 



• Display Controller Basic Programming Model: [12] [13] [14] [15] [16] [17] [18] 

• Graphics DMA Registers: [19] 

• Graphics Layer Configuration Registers: [20] [21] 

• Graphics Window Attributes: [22] 

• Video DMA Registers: [23] 

• Video Configuration Register: [24] [25] 

• Video Up-/Down-Sampling Configuration: [26] [27] 

• Image Data from On-Chip SRAM: [28] 

• LCD-Specific Control Registers: [29] [30] 

• LCD Attributes: [31] [32] [33] [34] 

• LCD Timings: [35] [36] [37] 

• LCD Overlay: [38] [39] [40] 

• LCD TDM: [41] [42] [43] [44] [45] [46] [47] 

• LCD Spatial/Temporal Dithering: [48] [49] [50] [51] [52] 

• LCD Color Phase Rotation: [53] [54] [55] 

• TV Set-Specific Control Registers: [56] [57] [58] [59] 

• Digital Timings: [60] 

• Digital Overlay: [61] [62] [63] 

• Video Mode Transfer: [64] 

• Command Mode Transfer Example 1: [65] 


• DISPC Control Registers: [67] [68] [69] [70] [71] [72] 

• Enable: [73] 

• Video Encoder Programming Sequence: [74] [75] 


• Configure DISPC Timing, Window, and Color: [76] [77] [78] [79] [80] [81] [82] [83] [84] 

• Enable Video Mode Using the DISPC Video Port: [85] [86] [87] 

• Configure the DISPC: [88] [89] [90] [91] [92] [93] [94] [95] [96] 

• Send Frame Data to LCD Panel Using Automatic TE: [97] 



• Display Controller Registers: [99] 






Table 7-152. DISPC_CONFIG 


Description This control register configures the display controller module. 

Shadow register, updated on VFP start period or EVSYNC 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 

TVALPHABLENDERENABLE 

LCDALPHABLENDERENABLE 

FIFOFILLING 

FIFOHANDCHECK 


31: 20 Reserved Write 0s for future compatibility. Read returns 0 RW 0x00000 

19 TVALPHABLENDER Selects the alpha blender (TV output) RW 0 

ENABLE 

CPR 

FIFOMERGE 

0x0: Alpha blender is disabled. 

TCKDIGSELECTION 

0x1: The alpha blender is enabled. 

18 LCDALPHABLENDER Selects the alpha blender (LCD output) RW 0 

ENABLE 

0x0: Alpha blender is disabled. 

0x1: The alpha blender is enabled. 

17 FIFOFILLING Controls if the FIFO are refilled only when the LOW threshold is RW 0 

reached or if all FIFO are refilled when at least one of them 

reaches the LOW threshold. 

0x0: Each FIFO is refilled when it reaches LOW threshold. 

0x1: All FIFOs are refilled up to high threshold when at least 

one of them reaches the LOW threshold. (only active 

FIFOs should be considered and when reaching the end 

of the frame the FIFO goes to empty condition so no 

need to fill it again). 

16 FIFOHANDCHECK Controls the handshake between FIFO and RFBI STALL to RW 0 

prevent from underflow. The bit should be set to 0 when the 

module is not in STALL mode. 

0x0: Only the STALL signal from RFBI is used regardless of 

the FIFO fullness information to provide data to the 

RFBI module. 

0x1: The STALL signal from RFBI is used in combination 

with the FIFO fullness information to provide data to the 

RFBI module only when it does not generated FIFO 

underflow. 

15 CPR Color phase rotation control wr: VFP RW 0 

0x0: Color phase rotation disabled 

0x1: Color phase rotation enabled 

14 FIFOMERGE FIFO merge control RW 0 

wr: EVSYNC or VFP 

TCKDIGENABLE 

TCKLCDSELECTION 

0x0: FIFO merge disabled 

Each FIFO is dedicated to one pipeline. 


TCKLCDENABLE 


FUNCGATED 

ACBIASGATED 

VSYNCGATED 

HSYNCGATED 

PIXELCLOCKGATED 

PIXELDATAGATED 

PALETTEGAMMATABLE 

LOADMODE 

PIXELGATED 

1817




0x1: FIFO merge enabled 

All the FIFOS are merged into a single one to be used 

by the single active pipeline. 

13 TCKDIGSELECTION Transparency color key selection (digital output) RW 0 

wr: EVSYNC 

0x0: Graphics destination transparency color key selected in 

normal mode or graphics source transparency color key 

selected in alpha mode 

0x1: Video source transparency color key selected in normal 

mode 

12 TCKDIGENABLE Transparency color key enabled (digital output) RW 0 

wr: EVSYNC 

0x0: Disable the transparency color key for digital output 

0x1: Enable the transparency color key for digital output 

11 TCKLCDSELECTION Transparency color key selection (LCD output) RW 0 

WR: VFP 

0x0: Graphics destination transparency color key selected in 

normal mode or graphics source transparency color key 

selected in alpha mode 

0x1: Video source transparency color key selected in normal 

mode 

10 TCKLCDENABLE Transparency color key enabled (LCD output) RW 0 

WR: VFP * 

0x0: Disable the transparency color key for the LCD 

0x1: Enable the transparency color key for the LCD 

9 FUNCGATED Functional clocks gated enabled RW 0 

WR: immediate 

0x0: Functional clocks gated disabled 

0x1: Functional clocks gated enabled 

8 ACBIASGATED ACBias Gated Enabled RW 0 

WR: VFP 

0x0: AcBias Gated Disabled 

0x1: AcBias Gated Enabled 

7 VSYNCGATED VSYNC Gated Enabled RW 0 

WR: VFP 

0x0: VSYNC Gated Disabled 

0x1: VSYNC Gated Enabled 

6 HSYNCGATED HSYNC Gated Enabled RW 0 

WR: VFP 

0x0: HSYNC Gated Disabled 

0x1: HSYNC Gated Enabled 

5 PIXELCLOCKGATED Pixel Clock Gated Enabled RW 0 

WR: VFP 

0x0: Pixel Clock Gated Disabled 

0x1: Pixel Clock Gated Enabled 

4 PIXELDATAGATED Pixel Data Gated Enabled RW 0 

WR: VFP 

0x0: Pixel Data Gated Disabled 

0x1: Pixel Data Gated Enabled 

3 PALETTEGAMMATABLE Palette/Gamma Table selection RW 0 

WR: EVSYNC or VFP 

0x0: LUT used as palette (only if graphics format is 

BITMAP1, 2, 4, and 8) 

0x1: LUT used as gamma table (only if graphics format is 

NOT BITMAP1, 2, 4, and 8 or no graphics window 

present) 






2:1 LOADMODE Loading Mode for the Palette/Gamma Table RW 0x0 

WR: EVSYNC or VFP 

0x0: Palette/Gamma Table and data are loaded every frame. 

0x1: Palette/Gamma Table to be loaded. Users set the bit 

when the palette/gamma table has to be loaded. H/W 

resets the bit when table has been loaded. 

(DISPC_GFX_ATTRIBUTES. GfxEnable has to be set 

to 1). 

0x2: Frame data only loaded every frame 

0x3: Palette/Gamma Table and frame data loaded on first 

frame then switch to 10 (H/W). 

0 PIXELGATED Pixel Gated Enable (only for Active Matrix Display) RW 0 

WR: VFP 


• Transaction Timing Diagrams: [0] 



• Wake-Up Mode: [2] 

0x0: Pixel clock always toggles (only in Active Matrix mode) 

0x1: Pixel clock only toggles when there is valid data to 

display. (only in Active Matrix mode) 

Table 7-153. Register Call Summary for Register DISPC_CONFIG 


• Transparency Color Keys: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] 


• Display Controller Basic Programming Model: [15] 

• Graphics DMA Registers: [16] [17] [18] 

• Graphics Layer Configuration Registers: [19] 

• Video DMA Registers: [20] [21] 

• Video Configuration Register: [22] 

• LCD-Specific Control Registers: [23] 

• LCD Timings: [24] [25] [26] [27] [28] 

• LCD Overlay: [29] [30] [31] 

• LCD Color Phase Rotation: [32] 


• Digital Overlay: [34] [35] [36] 







1819



Table 7-154. DISPC_DEFAULT_COLOR_m 

Address Offset 0x04C + m * 0x04 Indexm m = 0 to 1 

Physical address 0x4805 044C + m * 0x04 Instance DISPC 

Description The control register allows to configure the default solid background color for the LCD 

(DISPC_DEFAULT_COLOR_0) and for 24-bit digital output (DISPC_DEFAULT_COLOR_1). 

Shadow register, updated on VFP start period for DISPC_DEFAULT_COLOR_0 and EVSYNC for 

DISPC_DEFAULT_COLOR_1 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved DEFAULTCOLOR 




23:0 DEFAULTCOLOR 24-bit RGB color value to specify the default solid color to display RW 0x000000 

when there is no data from the overlays. 

Table 7-155. Register Call Summary for Register DISPC_DEFAULT_COLOR_m 


• Display Controller Basic Programming Model: [0] [1] 


• LCD Overlay: [3] 


• Digital Overlay: [5] 



Table 7-156. DISPC_TRANS_COLOR_m 

Address Offset 0x054 + m * 0x04 Index m = 0 to 1 

Physical address 0x4805 0454 + m * 0x04 Instance DISPC 

Description The register sets the transparency color value for the video/graphics overlays for the LCD output 

(DISPC_TRANS_COLOR_0) for 24-bit digital output(DISPC_TRANS_COLOR_1). 

Shadow register, updated on VFP start period for DISPC_TRANS_COLOR_0 and EVSYNC for 

DISPC_TRANS_COLOR_1 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved TRANSCOLORKEY 




23:0 TRANSCOLORKEY Transparency Color Key Value in RGB format RW 0x000000 

[0] BITMAP 1 (CLUT), [23,1] set to 0s 

[1:0] BITMAP 2 (CLUT), [23,2] set to 0s 



[11:0] RGB 12, [23,12] set to 0s 

[15:0] RGB 16, [23,16] set to 0s 

[23:0] RGB 24 





Table 7-157. Register Call Summary for Register DISPC_TRANS_COLOR_m 


• Display Controller Basic Programming Model: [0] [1] 



• Digital Overlay: [4] 




Table 7-158. DISPC_LINE_STATUS 


Description The control register indicates the current LCD panel display line number. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved LINENUMBER 


31:11 Reserved Write 0s for future compatibility. R 0x000000 


10:0 LINENUMBER Current LCD panel line number R 0x7FF 

Current display line number. The first active line has the value 0. 

During blanking lines the line number is not incremented. 

Table 7-159. Register Call Summary for Register DISPC_LINE_STATUS 




Table 7-160. DISPC_LINE_NUMBER 


Description The control register indicates the LCD panel display line number for the interrupt and the DMA request. 

Shadow register, updated on VFP start period. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 





10:0 LINENUMBER LCD panel line number programming RW 0x000 

LCD line number defines the line on which the programmable 

interrupt is generated and the DMA request occurs. 

Table 7-161. Register Call Summary for Register DISPC_LINE_NUMBER 


• Display Controller DMA Request (Line Trigger): [0] 







Table 7-161. Register Call Summary for Register DISPC_LINE_NUMBER (continued) 




Table 7-162. DISPC_TIMING_H 


Description The register configures the timing logic for the HSYNC signal. 

Shadow register, updated on VFP start period 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HBP HFP HSW 


31:20 HBP Horizontal Back Porch. RW 0x00 

Encoded value (from 1 to 4096) to specify the number of pixel clock 

periods to add to the beginning of a line transmission before the first set 

of pixels is output to the display (program to value minus 1). 

19:8 HFP Horizontal front porch. RW 0x00 


periods to add to the end of a line transmission before line clock is 

asserted (program to value minus 1). 

7:0 HSW Horizontal synchronization pulse width RW 0x00 


periods to pulse the line clock at the end of each line (program to value 

minus 1). 

Table 7-163. Register Call Summary for Register DISPC_TIMING_H 


• Transaction Timing Diagrams: [0] [1] [2] 




• LCD Timings: [5] [6] [7] [8] [9] [10] 


• Vertical and Horizontal Timings: [11] [12] [13] 

• Configure DISPC Timing, Window, and Color: [14] 




Table 7-164. DISPC_TIMING_V 


Description The register configures the timing logic for the VSYNC signal. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VBP VFP VSW 






31:20 VBP Vertical back porch RW 0x00 

Encoded value (from 0 to 4095) to specify the number of line clock 

periods to add to the beginning of a frame before the first set of pixels is 

output to the display. 

19:8 VFP Vertical front porch RW 0x00 

Encoded value (from 0 to 4095) to specify the number of line clock 

periods to add to the end of each frame. 

7:0 VSW Vertical synchronization pulse width RW 0x00 

In active mode, encoded value (from 1 to 256) to specify the number of 

line clock periods (program to value minus one) to pulse the frame clock 

(VSYNC) pin at the end of each frame after the end of frame wait (VFP) 

period elapses. Frame clock uses as VSYNC signal in active mode. 

In passive mode, encoded value (from 1 to 256) to specify the number of 

extra line clock periods (program to value minus one) to insert after the 

vertical front porch (VFP) period has elapsed. 

Table 7-165. Register Call Summary for Register DISPC_TIMING_V 






• LCD Timings: [5] [6] [7] [8] [9] [10] 


• Vertical and Horizontal Timings: [11] [12] [13] 





Table 7-166. DISPC_POL_FREQ 


Description The register configures the signal configuration. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

ONOFF 

Reserved ACBI ACB 

RF 




17 ONOFF HSYNC/VSYNC Pixel clock Control On/Off RW 0 

IEO 

0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock 

than pixel data 

IPC 

IHS 

IVS 

0x1: HSYNC and VSYNC are driven according to bit 16 

16 RF Program HSYNC/VSYNC Rise or Fall RW 0 

0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if 

bit 17 set to 1) 

0x1: HSYNC and VSYNC are driven on the rising edge of pixel clock 

(if bit 17 set to 1) 

15 IEO Invert output enable RW 0 

0x0: Ac-bias is active high (active display mode) 



1823




0x1: Ac-bias is active low (active display mode) 

14 IPC Invert pixel clock RW 0 

0x0: Data is driven on the LCD data lines on the rising-edge of the 

pixel clock 

0x1: Data is driven on the LCD data lines on the falling-edge of the 

pixel clock 

13 IHS Invert HSYNC RW 0 

0x0: Line clock pin is active high and inactive low 

0x1: Line clock pin is active low and inactive high 

12 IVS Invert VSYNC RW 0 

0x0: Frame clock pin is active high and inactive low 

0x1: Frame clock pin is active low and inactive high 

11:8 ACBI AC-bias pin transitions per interrupt RW 0x0 

Value (from 0 to 15) used to specify the number of AC Bias pin transitions 

7:0 ACB AC-bias pin frequency RW 0x00 

Value (from 0 to 255) used to specify the number of line clocks to count 

before transitioning the ac-bias pin. This pin is used to periodically invert 

the polarity of the power supply to prevent DC charge build-up within the 

display. 

Table 7-167. Register Call Summary for Register DISPC_POL_FREQ 


• Transaction Timing Diagrams: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] 

[24] [25] [26] [27] [28] [29] 

• Video Port (VP) Interface: [30] 




• LCD Timings: [33] [34] [35] [36] [37] [38] [39] [40] 



Address Offset 0x070 

Table 7-168. DISPC_DIVISOR 


Description The register configures the divisors. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved LCD Reserved PCD 




23:16 LCD Display Controller Logic Clock Divisor RW 0x01 

Value (from 1 to 255) to specify the frequency of the display controller 

logic clock based on the function clock. The value 0 is invalid. 



7:0 PCD Pixel Clock Divisor RW 0x02 

Value (from 1 to 255) to specify the frequency of the pixel clock based on 

the Logic clock which is the functional clock divided by LCD. The values 0 

and 1 are invalid. 





Table 7-169. Register Call Summary for Register DISPC_DIVISOR 


• Video Port (VP) Interface: [0] 

• Video Port Used on Command Mode: [1] 




• LCD Timings: [4] [5] [6] 

• Digital Timings: [7] [8] 


• Display Subsystem Clock Configuration: [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] 


• Configure the DISPC: [22] [23] 



Address Offset 0x0000 0074 

Table 7-170. DISPC_GLOBAL_ALPHA 

Physical Address 0x4805 0474 Instance DISC 

Description The register defines the global alpha value for the graphics and video 2 pipelines. Shadow 

register, updated on VFP start period or EVSYNC for each bit field depending on the association 

of the each pipeline with the LCD or TV output. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED VID2GLOBALALPHA RESERVED GFXGLOBALALPHA 


31:24 RESERVED Write 0s for future compatibility. RW 0x00 

Reads return 0 

23:16 VID2GLOBALALPHA Global alpha value from 0 to 255. 0 corresponds to fully transparent RW 0x00 

and 255 to fully opaque. 


Reads return 0 

7:0 GFXGLOBALALPHA Global alpha value from 0 to 255. 0 corresponds to fully transparent RW 0x00 

and 255 to fully opaque. 

Table 7-171. Register Call Summary for Register DISPC_GLOBAL_ALPHA 


• LCD Overlay: [0] [1] 

• Digital Overlay: [2] [3] 





1825



Address Offset 0x078 

Table 7-172. DISPC_SIZE_DIG 


Description The register configures the size of the digital output field (interlace), frame (progressive) (horizontal and vertical). 

Shadow register, updated on EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved LPP Reserved PPL 




26:16 LPP Lines per panel RW 0x000 

Encoded value (from 1 to 2048) to specify the number of lines per panel 

(program to value minus one). 



10:0 PPL Pixels per line RW 0x000 

Encoded value (from 1 to 2048) to specify the number of pixels contained 

within each line on the display (program to value minus one) 


• Up-/Down-Sampling: [0] 

Table 7-173. Register Call Summary for Register DISPC_SIZE_DIG 




• Digital Frame/Field Size: [3] [4] 

• Video Encoder Register Settings: [5] [6] 



Address Offset 0x07C 

Table 7-174. DISPC_SIZE_LCD 


Description The register configures the panel size (horizontal and vertical). 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved LPP Reserved PPL 




26:16 LPP Lines per panel RW 0x000 

Encoded value (from 1 to 2048) to specify the number of lines per panel 

(program to value minus one). 








10:0 PPL Pixels per line RW 0x000 

Encoded value (from 1 to 2048) to specify the number of pixels contains 

within each line on the display (program to value minus one). When 

running in normal mode (stall mode is bypassed by setting 

DSS.DISPC_CONTROL[11] STALLMODE =0) the line width must be set 

to a value multiple of 8 pixels (ex: PPL=0x7) 


• Transaction Timing Diagrams: [0] [1] 



Table 7-175. Register Call Summary for Register DISPC_SIZE_LCD 




• LCD Attributes: [5] [6] 

• LCD Timings: [7] [8] 



• Configure the DISPC: [10] [11] 



Table 7-176. DISPC_GFX_BAj 

Address Offset 0x080 + j * 0x04 Index j = 0 to 1 

Physical address 0x4805 0480+ j * 0x04 Instance DISC 

Description The register configures the base address of the graphics buffer displayed in the graphics window (0 1 :for 

ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the 

LCD output and 0 1 when on the 24-bit digital output). 

Shadow register, updated on VFP start period or EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

GFXBA 


31:0 GFXBA Graphics base address RW 0x00000000 

Base address of the graphics buffer (aligned on pixel size boundary) 

(in case 1-, 2-, and 4-BPP, byte alignment is required) 

Table 7-177. Register Call Summary for Register DISPC_GFX_BAj 



• Graphics DMA Registers: [1] [2] 






1827




Table 7-178. DISPC_GFX_POSITION 


Description The register configures the position of the graphics window. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GFXPOSY Reserved GFXPOSX 




26:16 GFXPOSY Y position of the graphics window. RW 0x000 

Encoded value (from 0 to 2047) to specify the Y position of the graphics 

window on the screen. The line at the top has the Y-position 0. 



10:0 GFXPOSX X position of the graphics window. RW 0x000 

Encoded value (from 0 to 2047) to specify the X position of the graphics 

window on the screen. The first pixel on the left of the screen has the 

X-position 0. 

Table 7-179. Register Call Summary for Register DISPC_GFX_POSITION 




• Graphics Window Attributes: [2] [3] 





Table 7-180. DISPC_GFX_SIZE 


Description The register configures the size of the graphics window. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GFXSIZEY Reserved GFXSIZEX 



26:16 GFXSIZEY Number of lines of the graphics window. RW 0x000 

Encoded value (from 1 to 2048) to specify the number of lines of the 

graphics window (program to value minus one). 


10:0 GFXSIZEX Number of pixels of the graphics window. RW 0x000 

Encoded value (from 1 to 2048) to specify the number of pixels per line 

of the graphics window (program to value minus one). 





Table 7-181. Register Call Summary for Register DISPC_GFX_SIZE 








Address Offset 0x0A0 

Table 7-182. DISPC_GFX_ATTRIBUTES 

Physical address 0x4805 04A0 Instance DISC 

Description The register configures the graphics attributes. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


RESERVED GFXFORMAT 



Read returns 0. 

28 PREMULTIPLYALPHA The field configures the DISPC GFX to process incoming data as RW 0 

pre-multiplied alpha data or non premultiplied alpha data. 

Default setting is non pre-multiplied alpha data. 

0x0: Non pre-multiplyalpha data color component 

0x1: Pre-multiplyalpha data color component 

GFXSELFREFRESH 

GFXARBITRATION 

GFXROTATION 

GFXFIFOPRELOAD 

NOTE: The pre-multiplied alpha option is 

only valid when bit field [4:1] 

GFXFORMAT is set to ARGB or 

RGBA formats. Otherwise, the 

PREMULTIPLYALPHA bit field is 

ignored by the hardware. 



15 GFXSELFREFRESH Enables the self refresh of the graphics window from its own FIFO RW 0 

only. 

0x0: The graphics pipeline accesses the interconnect to fetch 

data from the system memory 

0x1: The graphics pipeline does not need anymore to fetch 

data from memory. Only the graphics FIFO is used. It 

takes effect after the frame has been loaded in the FIFO 

14 GFXARBITRATION Determines the priority of the graphics pipeline. The graphics RW 0 

pipeline is one of the high priority pipeline. The arbitration wheel 

gives always the priority first to the high priority pipelines using 

round-robin between them. When there is only normal priority 

pipelines sending requests, the round-robin applies between them. 


GFXENDIANNESS 


GFXNIBBLEMODE 

GFXCHANNELOUT 

GFXBURSTSIZE 

GFXREPLICATIONENABLE 

GFXENABLE 

1829




0x0: The graphics pipeline is one of the normal priority 

pipeline. 

0x1: The graphics pipeline is one of the high priority pipeline. 

13:12 GFXROTATION Graphics rotation flag (used only in case of RGB24 packed format) RW 0x0 

0x0: No rotation 

0x1: Rotation by 90 degrees 



11 GFXFIFOPRELOAD Graphics preload value RW 0 

0x0: H/W prefetches pixels up to the preload value defined in 

the preload register. 

0x1: H/W prefetches pixels up to high threshold value. 

10 GFXENDIANNESS Graphics endianness RW 0 

0x0: Little endian operation is selected. 

0x1: Big endian operation is selected. 

9 GFXNIBBLEMODE Graphics Nibble Mode (only for 1-, 2- and 4-BPP) RW 0 

0x0: Nibble mode is disabled 

0x1: Nibble mode is enabled 

8 GFXCHANNELOUT Graphics Channel Out configuration RW 0 

wr: immediate 

0x0: LCD output selected 

0x1: 24-bit output selected 

7:6 GFXBURSTSIZE Graphics DMA Burst Size RW 0x0 

0x0: 4x32bit bursts 



0x3: Reserved 

5 GFXREPLICATION GfxReplicationEnable RW 0 

ENABLE 

0x0: Disable Graphics replication logic 

0x1: Enable Graphics replication logic 

4:1 GFXFORMAT Graphics format; Other enums: Reserved (0x7, 0xA, 0xB and 0xF) RW 0x0 

0x0: BITMAP 1 (CLUT) 




0x4: RGB 12 (un-packed in 16-bit container) 

0x5: ARGB16 

0x6: RGB 16 


0x9: RGB 24 (packed in 24-bit container) 

0xC: ARGB32 

0xD: RGBA32 

0xE: RGBx 32 (24-bit RGB aligned on MSB of the 32-bit 

container) 

0 GFXENABLE GfxEnable RW 0 

0x0: Graphics disabled (graphics pipeline inactive and 

graphics window not present) 

0x1: Graphics enabled (graphics pipeline active and graphics 

window present on the screen) 





Table 7-183. Register Call Summary for Register DISPC_GFX_ATTRIBUTES 


• Priority Rule: [0] [1] 



• Graphics DMA Registers: [3] [4] [5] [6] [7] [8] [9] 

• Graphics Layer Configuration Registers: [10] [11] 

• Graphics Window Attributes: [12] [13] [14] [15] [16] 






Table 7-184. DISPC_GFX_FIFO_THRESHOLD 


Description The register configures the graphics FIFO. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GFXFIFOHIGHTHRESHOLD Reserved GFXFIFOLOWTHRESHOLD 



27:16 GFXFIFOHIGH Graphics FIFO High Threshold RW 0x3FF 

THRESHOLD Number of bytes defining the threshold value. 

15:12 Reserved Write 0s for future compatibility. Read returns 0 RW 0x00 

11:0 GFXFIFOLOW Graphics FIFO Low Threshold RW 0x3C0 

THRESHOLD Number of bytes defining the threshold value 

Table 7-185. Register Call Summary for Register DISPC_GFX_FIFO_THRESHOLD 



• Graphics DMA Registers: [1] [2] [3] [4] [5] [6] 

• Image Data from On-Chip SRAM: [7] [8] [9] 


• FIFO Thresholds: [10] [11] 




Table 7-186. DISPC_GFX_FIFO_SIZE_STATUS 


Description This register defines the graphics FIFO size. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GFXFIFOSIZE 



1831




31:11 Reserved Write 0s for future compatibility. R 0x000000 


10:0 GFXFIFOSIZE Graphics FIFO Size R 0x400 

Number of bytes defining the FIFO value. 

Table 7-187. Register Call Summary for Register DISPC_GFX_FIFO_SIZE_STATUS 



Address Offset 0x0AC 

Table 7-188. DISPC_GFX_ROW_INC 

Physical address 0x4805 04AC Instance DISC 

Description The register configures the number of bytes to increment at the end of the row. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

GFXROWINC 


31:0 GFXROWINC Number of bytes to increment at the end of the row RW 0x00000001 

Encoded signed value (from -2 31 - 1 to 2 31 ) to specify the number of 

bytes to increment at the end of the row in the graphics buffer. 

The value 0 is invalid. The value 1 means next pixel. The value 

1+n*BPP means increment of n pixels. The value 1- (n+1)*BPP 

means decrement of n pixels. 

Table 7-189. Register Call Summary for Register DISPC_GFX_ROW_INC 








Address Offset 0x0B0 

Table 7-190. DISPC_GFX_PIXEL_INC 

Physical address 0x4805 04B0 Instance DISC 

Description The register configures the number of bytes to increment between two pixels. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GFXPIXELINC 








15:0 GFXPIXELINC Number of bytes to increment between two pixels RW 0x0001 


bytes between two pixels in the graphics buffer. 



means decrement of n pixels. 

Table 7-191. Register Call Summary for Register DISPC_GFX_PIXEL_INC 








Table 7-192. DISPC_GFX_WINDOW_SKIP 


Description The register configures the number of bytes to skip during video window display. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

GFXWINDOWSKIP 


31:0 GFXWINDOWSKIP Number of bytes to skip during video window #1. RW 0x00000000 

Encoded signed value (from -2 31 -1 to 2 31 ) to specify the number of 

bytes to skip in the graphics buffer when video window #1 is 

displayed on top of the graphics and no transparency color is 

enabled. 

Table 7-193. Register Call Summary for Register DISPC_GFX_WINDOW_SKIP 





• Graphics Window Attributes: [2] [3] [4] [5] 





1833




Table 7-194. DISPC_GFX_TABLE_BA 


Description The register configures the base address of the palette buffer or the gamma table buffer. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

GFXTABLEBA 


31:0 GFXTABLEBA Base address of the palette/gamma table buffer (24-bit entries in RW 0x00000000 

32-bit containers, aligned on 32-bit boundary). 

Table 7-195. Register Call Summary for Register DISPC_GFX_TABLE_BA 



• Graphics DMA Registers: [1] [2] 



Table 7-196. DISPC_VIDn_BAj 

Address Offset 0x0BC + ((n–1)* 0x90) + (j* 0x04) Index n = 1 for VID1 or 2 for VID2 

j = 0 to 1 

Physical address 0x4805 04BC + (j *0x04) Instance Display Controller 

0x4805 04BC + (j *0x04) Display Controller VID1 

0x4805 054C+ (j *0x04) Display Controller 

0x4805 054C+ (j *0x04) Display Controller VID2 

Description The register configures the base address of the video buffer for video window #n(#j for ping-pong mechanism with 

external trigger, based on the field polarity: 0 for even field and 1 for odd field). 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VIDBA 


31:0 VIDBA Video base address RW 0x00000000 

Base address of the video buffer (aligned on pixel size boundary) 

Table 7-197. Register Call Summary for Register DISPC_VIDn_BAj 



• Video DMA Registers: [1] [2] 



• Register List: [6] 


• Display Controller VID1 Register Mapping Summary: [7] 






Table 7-198. DISPC_VIDn_POSITION 

Address Offset 0x0C4 + ((–1) *0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04C4 Instance Display Controller 

0x4805 04C4 Display Controller VID1 

0x4805 0554 Display Controller 

0x4805 0554 Display Controller VID2 

Description The register configures the position of video window #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDPOSY Reserved VIDPOSX 




26:16 VIDPOSY Y position of video window #n RW 0x000 

Encoded value (from 0 to 2047) to specify the Y position of video 

window #n. The line at the top has the Y-position 0. 



10:0 VIDPOSX X position of video window #n RW 0x000 

Encoded value (from 0 to 2047) to specify the X position of video 

window #n. The first pixel on the left of the display screen has the 

X-position 0. 

Table 7-199. Register Call Summary for Register DISPC_VIDn_POSITION 




• Video Window Attributes: [2] [3] 





Table 7-200. DISPC_VIDn_SIZE 

Address Offset 0x0C8+((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04C8 Instance Display Controller 




Description The register configures the size of video window #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDSIZEY Reserved VIDSIZEX 




26:16 VIDSIZEY Number of lines of video #n RW 0x000 

Encoded value (from 1 to 2048) to specify the number of lines of 

video window #n (program to value minus one). 



1835






10:0 VIDSIZEX Number of pixels of video window #n RW 0x000 

Encoded value (from 1 to 2048) to specify the number of pixels of 

video window #n (program to value minus one). 

Table 7-201. Register Call Summary for Register DISPC_VIDn_SIZE 









Table 7-202. DISPC_VIDn_ATTRIBUTES 

Address Offset 0x0CC+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04CC Instance Display Controller 

0x4805 04CC Display Controller VID1 

0x4805 055C Display Controller 

0x4805 055C Display Controller VID2 

Description The register configures the attributes of video window #n such as format, resizeenable, shadow register, updated 

on VFP start period, or EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


RESERVED 

VIDSELFREFRESH 

VIDARBITRATION 

VIDLINEBUFFERSPLIT 

VIDVERTICALTAPS 

VIDDMAOPTIMIZATION 

VIDFIFOPRELOAD 

VIDROWREPEATENABLE 

VIDENDIANNESS 

VIDCHANNELOUT 

VIDBURSTSIZE 

VIDROTATION 

VIDFULLRANGE 

VIDVRESIZECONF 

VIDHRESIZECONF 

VIDRESIZEENABLE 

VIDFORMAT 


31: 29 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0000 

28 PREMULTIPLYALPHA The field configures the DISPC VID2 to process incoming data as RW 0 

pre-multiplied alpha data or non pre-multiplied alpha data. 

Default setting is non pre-multiplied alpha data. 

0x0: Non pre-multiplyalpha data color component 

0x1: Premultiplyalpha data color component 

NOTE: The pre-multiplied alpha control is 

supported only on VID2. 

For VID1 this bitfield is 

RESERVED. 

The pre-multiplied alpha option is 

only valid when bit field [4:1] 

VIDFORMAT is set to ARGB or 

RGBA formats. Otherwise, the 

PREMULTIPLYALPHA bit field is 

ignored by the hardware. 


VIDREPLICATIONENABLE 


VIDCOLORCONVENABLE 

VIDENABLE




27: 25 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0000 

24 VIDSELFREFRESH Enables the self refresh of the video window from its own FIFO RW 0 

only. 

0x0: The video pipeline accesses the interconnect to fetch data 

from the system memory 

0x1: The video pipeline does not need anymore to fetch data 

from memory. Only the video FIFO is used. It takes effect 

after the frame has been loaded in the FIFO 

23 VIDARBITRATION Determines the priority of the video pipeline. The video pipeline is RW 0 

one of the high priority pipeline. The arbitration wheel gives always 

the priority first to the high priority pipelines using round-robin 

between them. When there is only normal priority pipelines sending 

requests, the round-robin applies between them. 

0x0: The video pipeline is one of the normal priority pipeline. 

0x1: The video pipeline is one of the high priority pipeline. 

22 VIDLINEBUFFER Video vertical line buffer split RW 0 

SPLIT 

0x0: Vertical line buffers are not split. 

0x1: Vertical line buffers are split into two. 

21 VIDVERTICALTAPS Video vertical resize tap number RW 0 

0x0: Three taps are used for the vertical filtering logic. The 

other two taps are not used. 

0x1: Five taps are used for the vertical filtering logic. 

20 VIDDMAOPTI Video optimization in case of RW 0 

MIZATION 

0x0: The DMA engine fetches one pixel for each 32-bit OCP 

request (RGB16 and YUV422) while doing 90- and 

270-degree rotation (accessing on-chip memory and 

off-chip memory). 

0x1: The DMA engine fetches two pixels for each 32-bit OCP 

request (RGB16 and YUV422) while doing 90- and 

270-degree rotation (accessing on-chip memory and 

off-chip memory). 

The bit field [21] VIDVERTICALTAPS shall be set to 0x1, 

bit field [22] VIDLINEBUFFERSPLIT to 0x1, and all scaler 

registers shall be configured even for 1:1 ratio. 

Even width is required for the input picture when 5 taps are 

used. 

19 VIDFIFOPRELOAD Video preload value RW 0 

0x0: H/W prefetches pixels up to the preload value defined in 

the preload register. 

0x1: H/W prefetches pixels up to the high threshold value. 

18 VIDROWREPEAT Video Row Repeat (YUV case only when rotating 90 or RW 0 

ENABLE 270-degree) 

0x0: Row of VIDn won't be read twice. 

0x1: The Row data are fetched twice to extract both the Y 

components 

17 VIDENDIANNESS Video Endianness RW 0 

0x0: Little endian operation is selected. 

0x1: Big endian operation is selected. 

16 VIDCHANNELOUT Video Channel Out configuration RW 0 

wr: Immediate 

0x0: LCD output selected 

0x1: 24 bit output selected 

15:14 VIDBURSTSIZE Video DMA Burst Size RW 0x0 





1837





0x3: Reserved 

13:12 VIDROTATION Video Rotation Flag RW 0x0 

0x0: No rotation or VidFormat is RGB 




11 VIDFULLRANGE VidFullRange RW 0 

0x0: Limited range selected: 16 subtracted from Y before color 

space conversion 

0x1: Full range selected: Y is not modified before the color 

space conversion 

10 VIDREPLICATION VidReplicationEnable RW 0 

ENABLE 

0x0: Disable Video replication logic 

0x1: Enable Video replication logic 

9 VIDCOLORCONV VidColorConvEnable RW 0 

ENABLE 

0x0: Disable Color Space Conversion CbYCr to RGB 

0x1: Enable Color Space Conversion CbYCr to RGB 

8 VIDVRESIZECONF Video Vertical Resize Configuration RW 0 

0x0: Up-sampling selected 

0x1: Down-sampling selected 

7 VIDHRESIZECONF Video Horizontal Resize Configuration RW 0 

0x0: Up-sampling selected 

0x1: Down-sampling selected 

6:5 VIDRESIZEENABLE Video Resize Enable RW 0x0 

0x0: Disable the resize processing 

0x1: Enable the horizontal resize processing 

0x2: Enable the vertical resize processing 

0x3: Enable both horizontal and vertical resize processing 

4:1 VIDFORMAT Video1 channel Format; Other enums: Reserved (all other values RW 0x0 

(Video 1 channel) between 0x0 and 0x3, 0x5, 0x7, and between 0xC and 0xF) 

0x4: RGB12 (16-bit container) 

0x6: RGB 16 

0x8: RGB 24 (unpacked in 32-bit container) 

0x9: RGB 24 (packed in24-bit container) 

0xA: YUV2 4:2:2 co-sited 

0xB: UYVY 4:2:2 co-sited 

VIDFORMAT Video2 channel Format; Other enums: Reserved (all other values: RW 0x0 

(Video 2 channel) 0x0 and 0x3, 0x7, and 0xF) 

0x4: RGB 12 (16-bit container) 

0x5: ARGB 16 

0x6: RGB 16 


0x9: RGB 24 (packed in 24-bit container) 

0xA: YUV2 4:2:2 co-sited 

0xB: UYVY 4:2:2 co-sited 

0xC: ARGB 32 

0xD: RGBA 32 






0xE: RGBx 32 (24-bit RGB aligned on MSB of the 32-bit 

container) 

0 VIDENABLE VidEnable RW 0 

0x0: Video disabled (video pipeline inactive and window not 

present) 

0x1: Video enabled (video pipeline active and window present 

on the screen) 

Table 7-203. Register Call Summary for Register DISPC_VIDn_ATTRIBUTES 




• Priority Rule: [2] [3] 

• Rotation: [4] 



• Video DMA Registers: [6] [7] [8] [9] [10] [11] 

• Video Configuration Register: [12] [13] 

• Video Window Attributes: [14] [15] [16] [17] [18] 

• Video Up-/Down-Sampling Configuration: [19] [20] [21] [22] [23] [24] [25] 


• Additional Configuration When Using YUV Format: [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] 

[44] 

• Video DMA Optimization: [45] [46] [47] [48] [49] [50] [51] [52] [53] 


• Vertical Filtering: [54] 


• Enabling: [56] [57] 





Table 7-204. DISPC_VIDn_FIFO_THRESHOLD 

Address Offset 0x0D0+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04D0 Instance Display Controller 

0x4805 04D0 Display Controller VID1 



Description The register configures the video FIFO associated with video pipeline #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDFIFOHIGHTHRESHOLD Reserved VIDFIFOLOWTHRESHOLD 



27:16 VIDFIFOHIGH Video FIFO high threshold RW 0x3FF 



11:0 VIDFIFOLOW Video FIFO low threshold RW 0x3C0 




1839



Table 7-205. Register Call Summary for Register DISPC_VIDn_FIFO_THRESHOLD 



• Video DMA Registers: [1] [2] [3] [4] [5] [6] 





Table 7-206. DISPC_VIDn_FIFO_SIZE_STATUS 


Physical address 0x4805 04D4 Instance Display Controller 




Description The register defines the video FIFO size for video pipeline #n. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDFIFOSIZE 



10:0 VIDFIFOSIZE Video FIFO Size R 0x400 

Number of bytes defining the FIFO value 

Table 7-207. Register Call Summary for Register DISPC_VIDn_FIFO_SIZE_STATUS 




Table 7-208. DISPC_VIDn_ROW_INC 


Physical address 0x4805 04D8 Instance DISC 

0x4805 04D8 

0x4805 0568 

0x4805 0568 

Description The register configures the number of bytes to increment at the end of the row for the buffer associated with video 

window #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VIDROWINC 


31:0 VIDROWINC Number of bytes to increment at the end of the row RW 0x00000001 

Encoded signed value (from -2 31 - 1 to 2 31 ) to specify the number of bytes to 

increment at the end of the row in the video buffer. 

The value 0 is invalid. The value 1 means next pixel. The value 1+n*BPP 

means increment of n pixels. The value 1- (n+1)*BPP means decrement of 

n pixels. 





Table 7-209. Register Call Summary for Register DISPC_VIDn_ROW_INC 









Table 7-210. DISPC_VIDn_PIXEL_INC 

Address Offset 0x0DC+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04DC Instance Display Controller 

0x4805 04DC Display Controller VID1 

0x4805 056C Display Controller 


Description The register configures the number of bytes to increment between two pixels for the buffer associated with video 

window #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDPIXELINC 




15:0 VIDPIXELINC Number of bytes to increment at the end of the row RW 0x0001 


bytes between two pixels in the video buffer. 



means decrement of n pixels 

Table 7-211. Register Call Summary for Register DISPC_VIDn_PIXEL_INC 










1841



Table 7-212. DISPC_VIDn_FIR 

Address Offset 0x0E0+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04E0 Instance Display Controller 

0x4805 04E0 Display Controller VID1 



Description The register configures the resize factors for horizontal and vertical up-/down-sampling of video window #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDFIRVINC Reserved VIDFIRHINC 



28:16 VIDFIRVINC Vertical increment of the up-/down-sampling filter RW 0x0000 

Encoded value (from 1 to 4096). The value 0 is invalid. Values 

greater than 4096 are invalid. 


12:0 VIDFIRHINC Horizontal increment of the up-/down-sampling filter RW 0x0000 

Encoded value (from 1 to 4096). The value 0 is invalid. Values 

greater than 4096 are invalid. 

Table 7-213. Register Call Summary for Register DISPC_VIDn_FIR 







• Factor: [5] [6] 

• Coefficients: [7] [8] [9] [10] 




Table 7-214. DISPC_VIDn_PICTURE_SIZE 

Address Offset 0x0E4+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 04E4 Instance Display Controller 

0x4805 04E4 Display Controller VID1 



Description The register configures the size of the video picture associated with video layer #nbefore up-/down-scaling. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDORGSIZEY Reserved VIDORGSIZEX 




26:16 VIDORGSIZEY Number of lines of the video picture RW 0x000 

Encoded value (from 1 to 2048) to specify the number of lines of the 

video picture in memory (program to value minus one). 








10:0 VIDORGSIZEX Number of pixels of the video picture RW 0x000 

Encoded value (from 1 to 2048) to specify the number of pixels of the 

video picture in memory (program to value minus one). The size is 

limited to the size of the line buffer of the vertical sampling block in 

case the video picture is processed by the vertical filtering unit. (1) 

(1) For 5-tap RGB16 and YUV422 picture formats, the width of the input picture must be a multiple of 2 pixels and more than 5 pixels. This 

leads to the following register configuration: 

• DISPC_VIDn_ATTRIBUTES[21] VIDVERTICALTAPS is set to 1. 

• DISPC_VIDn_PICTURE_SIZE[10:0] VIDORGSIZEX must be even and more than 4. 

Table 7-215. Register Call Summary for Register DISPC_VIDn_PICTURE_SIZE 





• Video DMA Registers: [2] [3] [4] 



• Video Up-/Down-Sampling Configuration: [8] 


• Vertical Filtering: [9] 





Table 7-216. DISPC_VIDn_ACCUl 

Address Offset 0x0E8+ ((–1)* 0x90)+ (l*0x04) Index n = 1 for VID1 or 2 for VID2 

l = 0 to 1 

Physical address 0x4805 04E8 + (l* 0x04) Instance Display Controller 

0x4805 04E8 + (l* 0x04) Display Controller VID1 

0x4805 0578 + (l* 0x04) Display Controller 

0x4805 0578 + (l* 0x04) Display Controller VID2 

Description The register configures the resize accumulator init values for horizontal and vertical up-/down-sampling of video 

window #n (#I for ping-pong mechanism with external trigger, based on the field polarity) 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDVERTICALACCU Reserved VIDHORIZONTALACCU 




25:16 VIDVERTICAL Vertical initialization accu value. Encoded value (from 0 to 1023). RW 0x000 

ACCU 



9:0 VIDHORIZONTAL Horizontal initialization accu value. Encoded value (from 0 to 1023). RW 0x000 

ACCU 



1843



Table 7-217. Register Call Summary for Register DISPC_VIDn_ACCUl 






• Initial Phase: [4] [5] 




Table 7-218. DISPC_VIDn_FIR_COEF_Hi 

Address Offset 0x0F0+ ((–1)* 0x90) + (i* 0x08) Index n = 1 for VID1 or 2 for VID2 

i = 0 to 7 

Physical address 0x4805 04F0+ (i* 0x08) Instance Display Controller 

0x4805 04F0+ (i* 0x08) Display Controller VID1 

0x4805 0580 + (i* 0x08) Display Controller 

0x4805 0580 + (i* 0x08) Display Controller VID2 

Description The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video 

picture associated with video window #n for the phases from 0 to 7. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VIDFIRHC3 VIDFIRHC2 VIDFIRHC1 VIDFIRHC0 


31:24 VIDFIRHC3 Signed coefficient C3 for the horizontal up-/down-scaling with the phase n RW 0x00 

23:16 VIDFIRHC2 Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase RW 0x00 

n 



Table 7-219. Register Call Summary for Register DISPC_VIDn_FIR_COEF_Hi 




• Video Up-/Down-Sampling Configuration: [2] [3] [4] 


• Register List: [5] [6] [7] [8] [9] 

• Coefficients: [10] [11] [12] 








Table 7-220. DISPC_VIDn_FIR_COEF_HVi 

Address Offset 0x0F4+ ((–1)* 0x90) + (i* 0x08) Index n = 1 for VID1 or 2 for VID2 

i = 0 to 7 

Physical address 0x4805 04F4 + (i*0x08) Instance Display Controller 

0x4805 04F4 + (i*0x08) Display Controller VID1 

0x4805 0584 + (i*0x08) Display Controller 

0x4805 0584 + (i*0x08) Display Controller VID2 

Description The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the 

video picture associated with video window #n for the phases from 0 to 7. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VIDFIRVC2 VIDFIRVC1 VIDFIRVC0 VIDFIRHC4 


31:24 VIDFIRVC2 Signed coefficient C2 for the vertical up-/down-scaling with the phase n RW 0x00 

23:16 VIDFIRVC1 Unsigned coefficient C1 for the vertical up-/down-scaling with the phase n RW 0x00 

15:8 VIDFIRVC0 Signed coefficient C0 for the vertical up-/down-scaling with the phase n RW 0x00 


Table 7-221. Register Call Summary for Register DISPC_VIDn_FIR_COEF_HVi 




• Video Up-/Down-Sampling Configuration: [2] [3] [4] [5] [6] [7] 


• Register List: [8] [9] [10] [11] [12] [13] [14] [15] 

• Coefficients: [16] [17] [18] [19] [20] 




Table 7-222. DISPC_VIDn_CONV_COEF0 

Address Offset 0x130+((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 0530 Instance Display Controller 


0x4805 05C0 Display Controller 


Description The register configures the color space conversion matrix coefficients for video pipeline #n. 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved RCR Reserved RY 




26:16 RCR RCr Coefficient RW 0x000 

Encoded signed value (from -1024 to 1023). 





1845




10:0 RY RY Coefficient RW 0x000 


Table 7-223. Register Call Summary for Register DISPC_VIDn_CONV_COEF0 


• Image Data from On-Chip SRAM: [0] [1] 

• Video DMA Optimization: [2] 





Address Offset 0x134+((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 







Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GY Reserved RCB 




26:16 GY GY Coefficient RW 0x000 




10:0 RCB RCb Coefficient RW 0x000 













Address Offset 0x138+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 







Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GCB Reserved GCR 




26:16 GCB GCb Coefficient RW 0x000 




10:0 GCR GCr Coefficient RW 0x000 









Address Offset 0x13C+ ((–1)* 0x90) Index n = 1 for VID1 or 2 for VID2 

Physical address 0x4805 053C Instance Display Controller 


0x4805 05CC Display Controller 

0x4805 05CC Display Controller VID2 



Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved BCR Reserved BY 




26:16 BCR BCr coefficient RW 0x000 




10:0 BY BY coefficient RW 0x000 




1847













0x4805 05D0 Display Controller 




Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved BCB 




10:0 BCB BCb Coefficient RW 0x000 




• Image Data from On-Chip SRAM: [0] [1] 

• Video DMA Optimization: [2] 




Table 7-232. DISPC_DATA_CYCLEk 

Address Offset 0x1D4 + (k* 0x04) Index k = 0 to 2 

Physical address 0x4805 05D4+ (k * 0x04) Instance DISPC 

Description The control register configures the output data format for ith (1st, 2nd or 3rd) cycle. 

Shadow register, updated on VFP start period. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

BITALIGNMENTPIXEL2 

Reserved Reserved NBBITSPIXEL2 Reserved Reserved NBBITSPIXEL1 



BITALIGNMENTPIXEL1






27:24 BITALIGNMENT Bit alignment RW 0x0 

PIXEL2 Alignment of the bits from pixel#2 on the output interface 


20:16 NBBITSPIXEL2 Number of bits RW 0x00 

Number of bits from the pixel #2 (value from 0 to 16 bits). The 

values from 17 to 31 are invalid. 


11:8 BITALIGNMENT Bit alignment RW 0x0 

PIXEL1 Alignment of the bits from pixel#1 on the output interface 



Number of bits from the pixel #1 (value from 0 to 16 bits). The 

values from 17 to 31 are invalid. 

Table 7-233. Register Call Summary for Register DISPC_DATA_CYCLEk 


• Multiple Cycle Output Format: [0] [1] [2] 




• LCD TDM: [5] [6] [7] 



Table 7-234. DISPC_VIDn_FIR_COEF_Vi 

Address Offset 0x1E0+ ((–1)* 0x20) + (i* Index n = 1 for VID1 or 2 for VID2 

0x04) i = 0 to 7 

Physical address 0x4805 05E0 + (i* 0x04) Instance DISC 

0x4805 05E0 + (i* 0x04) 

0x4805 0670 + (i* 0x04) 

0x4805 0670 + (i* 0x04) 

Description This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture 

associated with video window #n for phases 0 to 7. Shadow register, updated on VFP start period or EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VIDFIRVC22 VIDFIRVC00 



15:8 VIDFIRVC22 Signed coefficient C22 for vertical up/down-scaling with phase n RW 0x00 

7:0 VIDFIRVC00 Signed coefficient C00 for vertical up/down-scaling with phase n RW 0x00 

Table 7-235. Register Call Summary for Register DISPC_VIDn_FIR_COEF_Vi 





• Register List: [3] [4] [5] 

• Coefficients: [6] [7] [8] 





Table 7-235. Register Call Summary for Register DISPC_VIDn_FIR_COEF_Vi (continued) 





Table 7-236. DISPC_CPR_COEF_R 


Description This register configures the color phase rotation matrix coefficients for the red component. Shadow register, 

updated on VFP start period. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

RR RG RB 


31:22 RR RR coefficient RW 0x000 

Encoded signed value (from -512 to 511) 

21 Reserved Write 0s for future compatibility. Read returns 0. RW 0 

20:11 RG RG coefficient RW 0x000 



9:0 RB RB coefficient RW 0x000 


Table 7-237. Register Call Summary for Register DISPC_CPR_COEF_R 




• LCD Color Phase Rotation: [2] [3] 




Table 7-238. DISPC_CPR_COEF_G 


Description This register configures the color phase rotation matrix coefficients for the green component. Shadow register, 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

GR GG GB 


31:22 GR GR coefficient RW 0x000 




Reserved 

Reserved 





20:11 GG GG coefficient RW 0x000 



9:0 GB GB coefficient RW 0x000 


Table 7-239. Register Call Summary for Register DISPC_CPR_COEF_G 








Table 7-240. DISPC_CPR_COEF_B 


Description This register configures the color phase rotation matrix coefficients for the blue component. Shadow register, 


Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

BR BG BB 


31:22 BR BR coefficient RW 0x000 



20:11 BG BG coefficient RW 0x000 



9:0 BB BB coefficient RW 0x000 


Table 7-241. Register Call Summary for Register DISPC_CPR_COEF_B 








Reserved 


1851




Table 7-242. DISPC_GFX_PRELOAD 


Description This register configures the graphics FIFO. Shadow register, updated on VFP start period or EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved PRELOAD 



11:0 PRELOAD Graphics preload value: Number of bytes defining the preload value. RW 0x100 

Constraint: Maximum value is (FIFO size - DMA burst size - 8) bytes 

Table 7-243. Register Call Summary for Register DISPC_GFX_PRELOAD 



• Graphics DMA Registers: [1] [2] [3] [4] 



Table 7-244. DISPC_VIDn_PRELOAD 



0x4805 0630 

0x4805 0634 

0x4805 0634 

Description This register configures the video FIFO. Shadow register, updated on VFP start period or EVSYNC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved PRELOAD 



11:0 PRELOAD Video preload value: Number of bytes defining the preload value. RW 0x100 

Constraint: Maximum value is (FIFO size - DMA burst size - 8) bytes 

Table 7-245. Register Call Summary for Register DISPC_VIDn_PRELOAD 



• Video DMA Registers: [1] [2] [3] [4] 




7.7.2.3 RFBI Registers 






Table 7-246. RFBI_REVISION 

Physical address 0x4805 0800 Instance RFBI 

Description This register contains the IP revision code. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved REV 







• RFBI Register Mapping Summary: [0] 


Table 7-247. Register Call Summary for Register RFBI_REVISION 

Table 7-248. RFBI_SYSCONFIG 


Description This register allows control of various parameters of the interconnect interface. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 





4:3 SIDLEMODE Slave interface power management, Idle req/ack control RW 0x0 

00: Force-idle: Idle request is acknowledged unconditionally. 

01: No idle: An idle request is never acknowledged 

10: Smart idle: Idle request is acknowledged based on the internal 

activity of the module. 

11: Reserved 

2 Reserved Write 0s for future compatibility RW 0 


1 SOFTRESET Software reset RW 0 

Sets this bit to 1 to trigger a module reset. The bit is automatically 

reset by the hardware. During reads, it always returns 0. 

0: Normal mode 

1: The module is reset 

0 AUTOIDLE Internal clock gating strategy (interconnectL4 and display controller RW 1 

clock) 

0: Interconnect L4 clock and display controller clock are free-running. 

1: Automatic clock gating strategy is applied for the interconnect L4 

clock and display controller clock, based on the interconnect interface 

and internal activity. 



Reserved 

Reserved 

SIDLEMODE 

Reserved 

SOFTRESET 

AUTOIDLE 

1853






• Idle Mode: [2] [3] [4] 

Table 7-249. Register Call Summary for Register RFBI_SYSCONFIG 


• RFBI Configuration: [5] 







Table 7-250. RFBI_SYSSTATUS 


Description This register provides status information about the module, excluding the interrupt status information. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



31: 10 Reserved Reserved. Read returns 0 R 0x000000 

9 BUSYRFBIDATA Data are pending to be processed from interconnect FIFO. R 0 

Read 0x0: No data pending 

Read 0x1: Some data are pending 

8 BUSY L4 Interface busy status bit R 0 

Read 0x0: The access to the following register is not stalled: 

RFBI_CMD, RFBI_DATA, RFBI_STATUS, RFBI_PARAM, 

RFBI_READ. 

Read 0x1: The access to any of the following registers is stalled: 

RFBI_CMD, RFBI_DATA, RFBI_STATUS, RFBI_PARAM, 

RFBI_READ. 

7:1 Reserved Reserved. Read returns 0 R 0x00 


0: Internal module reset is on-going 

1: Reset completed 

Table 7-251. Register Call Summary for Register RFBI_SYSSTATUS 



• RFBI State-Machine: [1] [2] [3] [4] [5] [6] [7] [8] [9] 





BUSYRFBIDATA 

BUSY 

RESETDONE




Table 7-252. RFBI_CONTROL 


Description The control register allows configuration of the RFBI module. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


31: 9 Reserved Write 0s for future compatibility RW 0x0000000 


8 SMART_DMA_REQ Smart DMA request RW 0x0 

0x0: The dmareq is asserted and de-asserted depending on the 

interconnect FIFO space even if MIdlereq is high in smart idle/no-idle 

mode and the entire burst gets error responses from the module. 

0x1: The dmareq is de-asserted after 2 clk cycles if it has been 

asserted for more than or equal to 2 clk cycles and MIdlereq is high 

in smart idle or no idle mode. No more burst requests will be given 

even if the space is available in the interconnect FIFO. 

7 DISABLE_DMA_REQ Disable DMA request RW 0x0 

0x0: The dmareq is enabled and the signal is generated based on the 

space available and the request coming into the data register. 

0x1: The dmareq is disabled and the signal is not generated at all 

based on space in the interconnect FIFO. It stays high until the 

DISABLE DMAREQ is high even if there is space in the interconnect 

FIFO to take requests. 

6:5 HIGHTHRESHOLD Defines the interconnect FIFO high threshold used by HW to assert RW 0x0 

DMA request. Used only if data written to RFBI_DATA are sent using 

system DMA. 

0x0: Size of the transfer of 4 words of 32-bit wide 



4 ITE Internal Trigger RW 0 

0: H/W waits for ITE bit to be set if in internal trigger mode for the 

configuration in use. 

1: User sets the ITE bit to start the transfer, when H/W takes into 

account the bit, the H/W resets it. 

3:2 CONFIGSELECT Select the CS and configuration RW 0x0 

00: No CS selected 

01: CS0 selected and configuration #0 

10: CS1 selected and configuration #1 

11: CS0 and CS1 both selected (only the configuration for CS0 is 

used) 

1 BYPASSMODE Bypass Mode RW 1 

0: The bypass mode not selected 

1: The bypass mode is selected 

0 ENABLE Enable/Disable flag RW 0 

0: Disable the RFBI module 

1: Enable the RFBI module 



SMART_DMA_REQ 

DISABLE_DMA_REQ 

HIGHTHRESHOLD 

ITE 

CONFIGSELECT 

BYPASSMODE 

ENABLE 

1855



Table 7-253. Register Call Summary for Register RFBI_CONTROL 


• Parallel Interface in RFBI Mode (MIPI DBI Protocol): [0] [1] 


• RFBI Control Registers: [2] 

• High Threshold: [3] [4] [5] 

• Bypass Mode: [6] 

• Enable: [7] [8] [9] 

• Configuration Selection: [10] 

• ITE Bit: [11] [12] [13] [14] [15] 

• Number of Pixels to Transfer: [16] [17] 


• Trigger Mode: [19] 

• RFBI Timings: [20] 




Table 7-254. RFBI_PIXEL_CNT 


Description The control register configures the RFBI pixel count value. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

PIXELCNT 


31:0 PIXELCNT Pixel counter value RW 0x00000000 

The S/W indicates the number of pixels to transfer to the LCD panel 

frame buffer. The value is set when the module is disabled. During 

the transfer the HW decrements the register when a pixel has been 

sent to the RFB. 

Table 7-255. Register Call Summary for Register RFBI_PIXEL_CNT 



• Enable: [1] 

• Number of Pixels to Transfer: [2] [3] [4] 




Table 7-256. RFBI_LINE_NUMBER 


Description The control register configures the number of lines to synchronize the beginning of the transfer. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 







31:11 Reserved Write 0s for future compatibility RW 0x000000 


10:0 LINENUMBER Programmable line number RW 0x000 

Line number from 0 to 2 11 -1. Number of HSYNC after the VSYNC 

occurs before the beginning of the transfer. 

Table 7-257. Register Call Summary for Register RFBI_LINE_NUMBER 






Table 7-258. RFBI_CMD 

Physical address 0x4805 084C Instance RFBI 

Description The control register configures the RFBI command 

Type W 

Write Latency 1 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved CMD 


31:16 Reserved Write 0s for future compatibility W 0x0000 


15:0 CMD Command Value W 0x0000 

8/9/12/16 bit value depending on the parallel mode 

[7:0] 8-bit DT 

[8:0] 9-bit Data type 




• Send Commands: [0] 



• RFBI State-Machine: [3] [4] 



• RFBI Registers: [6] [7] 

Table 7-259. Register Call Summary for Register RFBI_CMD 



1857




Table 7-260. RFBI_PARAM 


Description The control register configures the RFBI parameter. 

Type W 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved PARAM 


31:16 Reserved Write 0s for future compatibility W 0x0000 


15:0 PARAM Param Value W 0x0000 













Table 7-261. Register Call Summary for Register RFBI_PARAM 

Table 7-262. RFBI_DATA 


Description The control register configures the RFBI data. 

Type W 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

DATA 


31:0 DATA Data value W 0x00000000 

12/16/18/24/2x16 bit value depending on the Data type 





[31:0] 2x16-bit Data type 

Display Subsystem Overview 

• Display Subsystem Overview: [0] 


• RFBI Interconnect FIFO: [1] [2] 


• High Threshold: [3] [4] [5] 

• RFBI State-Machine: [6] [7] [8] [9] [10] 

Table 7-263. Register Call Summary for Register RFBI_DATA 





Table 7-263. Register Call Summary for Register RFBI_DATA (continued) 



• RFBI Registers: [12] [13] [14] 


Table 7-264. RFBI_READ 


Description The control register configures the RFBI read 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved READ 




15:0 READ Read Value RW 0x0000 













Table 7-265. Register Call Summary for Register RFBI_READ 

Table 7-266. RFBI_STATUS 

Physical address 0x4805 085C Instance RFBI 

Description The control register configures the RFBI status. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved STATUS 




15:0 STATUS Status value RW 0x0000 








1859









Table 7-267. Register Call Summary for Register RFBI_STATUS 

Table 7-268. RFBI_CONFIGi 

Address Offset 0x60+ (i* 0x18) Index i = 0 to 1 

Physical address 0x4805 0860+ (i* 0x18) Instance RFBI 

Description The control register allows configuration #I of the RFBI module. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HSYNCPOLARITY 

TE_VSYNC_POLARITY 


CSPOLARITY 

WEPOLARITY 

REPOLARITY 

A0POLARITY 




21 HSYNCPOLARITY HSYNC polarity RW 1 

0: HSYNC active low 

1: HSYNC active high 

20 TE_VSYNC_ TE or VSYNC Polarity RW 1 

POLARITY 0: TE or VSYNC active low 

1: TE or SYNC active high 

19 CSPOLARITY CS Polarity RW 0 

0: CS active low defined at reset time 

1: CS active high defined at reset time 

18 WEPOLARITY WE Polarity RW 0 

0: WE active low 

1: WE active high 

17 REPOLARITY RE Polarity RW 0 

0: RE active low 

1: RE active high 

16 A0POLARITY A0 Polarity RW 1 

0: A0 active low 

1: A0 active high 



12:11 UNUSEDBITS State of unused bits RW 0x0 

00: Low level (0) 

01: High level (1) 

10: Unchanged from previous state 

11: Reserved 

10:9 CYCLEFORMAT Cycle format RW 0x0 

00: 1 cycle for 1 pixel 

01: 2 cycles for 1 pixel 

10: 3 cycles for 1 pixel 

11: 3 cycles for 2 pixels 


UNUSEDBITS 


CYCLEFORMAT 

L4FORMAT 

DATA TYPE 

TIMEGRANULARITY 

TRIGGERMODE 

PARALLEL MODE




8:7 L4FORMAT L4 Write Access format RW 0x0 

00: 1 pixel per L4 access to the register data 

01: Reserved 

10: 2 pixels per L4 access to the register data with 1st pixel at 

the position [15:0] 

11: 2 pixels per L4 access to the register data with 1st pixel at 

the position [31:16] 

6:5 DATA TYPE Data type from the display controller and L4 RW 0x0 

00: 12-bit 

01: 16-bit 

10: 18-bit 

11: 24-bit 

4 TIMEGRANU Multiplies signal timing latencies by two RW 0 

LARITY 0: x2 latencies disabled 

1: x2 latencies enabled 

3:2 TRIGGERMODE Trigger Mode RW 0x0 

00: Internal trigger mode (ITE bit mode) 

01: External trigger mode (TE signal) 

10: External trigger mode (VSYNC/HSYNC signals) 

11: Reserved 

1:0 PARALLELMODE Parallel Mode RW 0x0 

00: 8-bit parallel output interface selected 




Table 7-269. Register Call Summary for Register RFBI_CONFIGi 


• Parallel Interface in RFBI Mode (MIPI DBI Protocol): [0] 


• Output Parallel Modes: [1] 

• Read/Write: [2] [3] 


• ITE Bit: [4] [5] 

• Number of Pixels to Transfer: [6] [7] [8] [9] [10] 

• Parallel Mode: [11] 

• Cycle Format: [12] 

• Unused Bits: [13] 

• RFBI Timings: [14] 


• RFBI Configuration Flow Charts: [17] [18] [19] 



Table 7-270. RFBI_ONOFF_TIMEi 



Description The control register allows configuration of the RFBI timing. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 

REOFFTIME REONTIME WEOFFTIME WEONTIME CSOFFTIME CSONTIME 



1861






29:24 REOFFTIME Read Enable deassertion time from start access time RW 0x00 

Number of L4Clk cycles 

23:20 REONTIME Read Enable assertion time from start access time RW 0x0 


19:14 WEOFFTIME Write Enable deassertion time from start access time RW 0x00 


13:10 WEONTIME Write Enable assertion time from start access time RW 0x0 


9:4 CSOFFTIME CS deassertion time from start access time RW 0x00 


3:0 CSONTIME CS assertion time from start access time RW 0x0 


Table 7-271. Register Call Summary for Register RFBI_ONOFF_TIMEi 




• RFBI Timings: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] 



Table 7-272. RFBI_CYCLE_TIMEi 



Description The control register allows configuration of the RFBI timing. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

WRENABLE 

WWENABLE 

RRENABLE 

RWENABLE 

Reserved ACCESSTIME CSPULSEWIDTH RECYCLETIME WECYCLETIME 




27:22 ACCESSTIME Access Time RW 0x00 


21 WRENABLE Write to Read Pulse Width Enable (same CS) RW 0 

0: CSPulseWidth does not apply on Write to Read access 

1: CSPulseWidth applies on Write to Read access 

20 WWENABLE Write to Write Pulse Width Enable (same CS) RW 0 

0: CSPulseWidth does not apply on Write to Write access 

1: CSPulseWidth applies on Write to Write access 

19 RRENABLE Read to Read Pulse Width Enable (same CS) RW 0 

0: CSPulseWidth does not apply on Read to Read access 

1: CSPulseWidth applies on Read to Read access 

18 RWENABLE Read to Write Pulse Width Enable (same CS) RW 0 

0: CSPulseWidth does not apply on Read to Write access 

1: CSPulseWidth applies on Read to Write access 

17:12 CSPULSEWIDTH CS Pulse Width RW 0x00 







11:6 RECYCLETIME RE Cycle Time RW 0x00 


5:0 WECYCLETIME WE Cycle Time RW 0x00 


Table 7-273. Register Call Summary for Register RFBI_CYCLE_TIMEi 




• RFBI Timings: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] 



Table 7-274. RFBI_DATA_CYCLE1_i 

Address Offset 0x6C+ (i* 0x18) Index i = 0 to 1 

Physical address 0x4805 086C+ (i* 0x18) Instance RFBI 

Description The control register configures the RFBI data format for 1st cycle. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 






27:24 BITALIGNMENTPIXEL2 Bit alignment RW 0x0 

Alignment of the bits from pixel#2 on the output interface 




Number of bits from the pixel #2 (value from 0 to16 bits). 

The values from 17 to 31 are invalid. 










Table 7-275. Register Call Summary for Register RFBI_DATA_CYCLE1_i 




• Cycle Format: [1] [2] 



BITALIGNMENTPIXEL1



Table 7-275. Register Call Summary for Register RFBI_DATA_CYCLE1_i (continued) 






Description The control register configures the RFBI data format for 2nd cycle. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


























• Cycle Format: [1] [2] 





BITALIGNMENTPIXEL1






Description The control register configures the RFBI data format for 3rd cycle. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


























• Cycle Format: [1] 






1865




Table 7-280. RFBI_VSYNC_WIDTH 


Description The control register configures the RFBI VSYNC minimum pulse width 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved MINVSYNCPULSEWIDTH 




15:0 MINVSYNCPULSEWIDTH Programmable min VSYNC pulse width RW 0x0000 

Minimum VSYNC pulse width from 0 to 65535. Number 

of L4 clock cycles to determine when VSYNC pulse 

occurs. The values 0 and 1 are invalid. 

Table 7-281. Register Call Summary for Register RFBI_VSYNC_WIDTH 





• VSYNC Pulse Width (Minimum Value): [2] 




Table 7-282. RFBI_HSYNC_WIDTH 


Description The control register configures the RFBI HSYNC minimum pulse width. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved MINHSYNCPULSEWIDTH 




15:0 MINHSYNC Programmable min HSYNC pulse width RW 0x0000 

PULSEWIDTH Minimum HSYNC pulse width from 0 to 65535. Number of L4 clock 

cycles to determine when HSYNC pulse occurs. The values 0 and 1 are 

invalid. 

Table 7-283. Register Call Summary for Register RFBI_HSYNC_WIDTH 





• HSYNC Pulse Width (Minimum Value): [2] 







7.7.2.4 Video Encoder Registers 


Table 7-284. VENC_REV_ID 

Physical address 0x4805 0C00 Instance VENC 

Description Revision ID for the encoder 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved REV_ID 


31:8 Reserved Reserved. Read returns 0s. R 0x000000 

7:0 REV_ID This read-only register contains the revision ID for the encoder. The R TI internal data 

revision ID will identify different revisions of the IP. 

Table 7-285. Register Call Summary for Register VENC_REV_ID 


• Video Encoder Register Mapping Summary: [0] 


Table 7-286. VENC_STATUS 


Description VENC_STATUS 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FSQ 


31:5 Reserved Reserved. Read returns 0s. R 0x0000000 

4 CCE Closed caption status for even Field. R 0 

This bit is set immediately after the data in registers LINE21_E0 and 

LINE21_E1 have been encoded to closed caption. This bit is reset 

when both of these registers are written. 

3 CCO Closed Caption Status for Odd Field. R 0 

This bit is set immediately after the data in registers LINE21_O0 and 

LINE21_O1 have been encoded to closed caption. This bit is reset 

when both of these registers are written. 

2:0 FSQ Field Sequence ID. R 0x0 

For PAL, all three FSQ[2:0] are used whereas for NTSC only FSQ[1:0] 

is meaningful. Furthermore, FSQ[0] represents odd field when it is 0 

and even field when it is 1. 

Read 0x0: Odd field 

Read 0x1: Even field 


• Closed Caption Encoding: [0] [1] [2] [3] 

Table 7-287. Register Call Summary for Register VENC_STATUS 



• Video Encoder Registers: [5] 



CCE 

CCO




Table 7-288. VENC_F_CONTROL 


Description This register specifies the input video source and format 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved SVDS BCOLOR FMT 


31:9 Reserved Reserved. Read returns 0s. RW 0x000000 

8 RESET RESET the encoder RW 0 

0x0: No effect 

0x1: Reset the encoder, after reset, this bit is automatically set to 

zero. 

7:6 SVDS Select Video Data Source. RW 0x2 

0x0: Use external video source 

0x1: Use internal Color BAR 

0x2: Use background color 

0x3: Reserved 

5 RGBF RGB/YCrCb input coding range RW 0 

0x0: The input RGB data are in binary format with coding range 

0-255 

The input YCrCb data are in binary format with coding range 

0-255 

0x1: The input RGB data are in binary format with coding range 

16-235 

The input YCrCb data are in binary format conforming to 

ITU-601 standard 

4:2 BCOLOR Background color select RW 0x1 

0x0: black 

0x1: blue 

0x2: red 

0x3: magenta 

0x4: green 

0x5: cyan 

0x6: yellow 

0x7: white 

1:0 FMT These two bits specify the video input data stream format and timing RW 0x3 

0x0: 24-bit 4:4:4 RGB 

0x1: 24-bit 4:4:4 

0x2: 16-bit 4:2:2 

0x3: 8-bit ITU-R 656 4:2:2 

Table 7-289. Register Call Summary for Register VENC_F_CONTROL 


• Test Pattern Generation: [0] 


• Video Encoder Software Reset: [1] 

• Video Encoder Programming Sequence: [2] [3] 

• Video Encoder Register Settings: [4] 



RESET 

RGBF



Table 7-289. Register Call Summary for Register VENC_F_CONTROL (continued) 




Table 7-290. VENC_VIDOUT_CTRL 


Description Encoder output clock 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved 



0 27_54 Encoder output clock RW 0 

0x0: 54 MHz, 4x oversampling 

0x1: 27 MHz, 2x oversampling, the last 2x oversampling filter 

bypassed 

Table 7-291. Register Call Summary for Register VENC_VIDOUT_CTRL 






Table 7-292. VENC_SYNC_CTRL 


Description Sync Control Register 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 




15 FREE Free running RW 1 

0x0: Free running disabled 

0x1: Free running enabled. HSYNC and VSYNC are ignored 

14 ESAV Enable to detect F and V bits only on EAV in ITU-R 656 input mode RW 0 

FREE 

ESAV 

IGNP 

NBLNKS 

0x0: Detection of F and V bits on both EAV and SAV 

0x1: Detection of F and V bits only on EAV 

13 IGNP Ignore protection bits in ITU-R 656 input mode RW 0 

0x0: Protection bits are not ignored 

0x1: Protection bits are ignored 


VBLKM 


HBLKM 

Reserved 

FID_POL 

27_54 

1869




12 NBLNKS Blank shaping RW 0 

0x0: Blank shaping enabled 

0x1: Blank shaping disabled 

11:10 VBLKM Vertical blanking mode RW 0x0 

0x0: Internal default blanking 

0x1: Internal default blanking AND internal programmable blanking 

defined by VENC_FLEN_FAL[24:16]FAL and 

VENC_LAL_PHASE_RESET[8:0] LAL bit fields. 

Note: in this mode, the VENC_LAL_PHASE_RESET[16] 

SBLANK bit must be '0b1' to active the VBLKM functionality. 

0x2: Reserved 

0x3: Reserved 

9:8 HBLKM Horizontal blanking mode RW 0x0 

0x0: Internal default blanking 

0x1: Internal programmable blanking defined by 

VENC_SAVID_EAVID[26:16] SAVID and 

VENC_SAVID_EAVID[10:0] EAVID bit fields. 

0x2: External blanking defined by VENC_AVID_START_STOP_X 

and VENC_AVID_START_STOP_Y registers. 

0x3: Reserved 

7 Reserved Reserved. Read returns 0. RW 0 

6 FID_POL FID output polarity RW 0 

0x0: Odd field = 0 

Even field = 1 

0x1: Odd field = 1 

Even field = 0 

5:0 Reserved Reserved. Read returns 0. RW 0x00 

Table 7-293. Register Call Summary for Register VENC_SYNC_CTRL 


• Video Encoder Programming Sequence: [0] 






Table 7-294. VENC_LLEN 

Physical address 0x4805 0C1C Instance VENC 

Description VENC_LLEN 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved Reserved LLEN 




10:0 LLEN LLEN[10:0] RW 0x359 

Line length or total number of pixels in a scan line including active video and 

blanking. 

Total number of pixels in a scan line = LLEN 

NOTE: A write on the LLEN[10] is illegal. 







Table 7-295. Register Call Summary for Register VENC_LLEN 



• Video Encoder Registers: [2] [3] 


Table 7-296. VENC_FLENS 


Description VENC_FLENS 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FLENS 



10:0 FLENS The frame length or total number of lines in a frame including active RW 0x20C 

video and blanking from the source image. 

Total number of lines in a frame from the source image = FLENS + 1 



Table 7-297. Register Call Summary for Register VENC_FLENS 





Table 7-298. VENC_HFLTR_CTRL 


Description VENC_HFLTR_CTRL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved CINTP 



2:1 CINTP Chrominance interpolation filter control RW 0x0 

0x0: The chrominance interpolation filter is enabled 

0x1: The first section of the chrominance interpolation filter is bypassed 

0x2: The second section of the chrominance interpolation filter is 

bypassed 

0x3: Both sections of the filter are bypassed 

0 YINTP Luminance interpolation filter control RW 0 

0x0: The luminance interpolation filter is enabled 

0x1: The luminance interpolation filter is bypassed 



YINTP 

1871



Table 7-299. Register Call Summary for Register VENC_HFLTR_CTRL 







Table 7-300. VENC_CC_CARR_WSS_CARR 


Description Frequency code control 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

FWSS FCC 


31:16 FWSS Wide screen signaling run-in code frequency control RW 0x043F 

For common values for FWSS[15:0] bit field, refer to Table 7-46 

Reset value is for NTSC-601standard 

15:0 FCC Close caption run-in code frequency control RW 0x2631 

For common values for FCC[15:0] bit field refer to Table 7-44. Reset value is 

for NTSC-601 standard 

Table 7-301. Register Call Summary for Register VENC_CC_CARR_WSS_CARR 


• Closed Caption Encoding: [0] [1] [2] 

• Wide-Screen Signaling (WSS) Encoding: [3] [4] 






Table 7-302. VENC_C_PHASE 


Description VENC_C_PHASE 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved CPHS 



7:0 CPHS Phase of the encoded video color subcarrier (including the color burst) RW 0x00 

relative to H-sync. The adjustable step is 360/256 degrees. 





Table 7-303. Register Call Summary for Register VENC_C_PHASE 


• Subcarrier and Burst Generation: [0] [1] [2] 







Table 7-304. VENC_GAIN_U 


Description Gain control for Cb signal 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GU 



8:0 GU Gain control for Cb signal. Following are typical programming examples for RW 0x102 

NTSC and PAL standards. 

NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GU = 0x102 

NTSC with no pedestal: WHITE - BLACK = 100 IRE GU = 0x117 

PAL with no pedestal: WHITE - BLACK = 100 IRE GU = 0x111 


• Chroma Stage: [0] 

Table 7-305. Register Call Summary for Register VENC_GAIN_U 






Table 7-306. VENC_GAIN_V 


Description Gain control of Cr signal 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GV 



8:0 GV Gain control of Cr signal. Following are typical programming examples for RW 0x16C 

NTSC and PAL standards. 

NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GV = 0x16C 

NTSC with no pedestal: WHITE - BLACK = 100 IRE GV = 0x189 

PAL with no pedestal: WHITE - BLACK = 100 IRE GV = 0x181 



1873




• Chroma Stage: [0] 

Table 7-307. Register Call Summary for Register VENC_GAIN_V 






Table 7-308. VENC_GAIN_Y 


Description Gain control of Y signal 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved GY 



8:0 GY Gain control of Y signal. Following are typical programming examples for RW 0x12F 

NTSC/PAL standards. 

NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE GY = 0x12F 

NTSC with no pedestal: WHITE - BLACK = 100 IRE GY = 0x147 

PAL with no pedestal: WHITE - BLACK = 100 IRE GY = 0x140 


• Luma Stage: [0] 

Table 7-309. Register Call Summary for Register VENC_GAIN_Y 






Table 7-310. VENC_BLACK_LEVEL 


Description Video Encoder BLACK LEVEL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved BLACK 



6:0 BLACK Black level setting. Following are typical programming examples for RW 0x43 


NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLACK_LEVEL = 

0x43 

NTSC with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x38 

PAL with no pedestal: WHITE - BLACK = 100 IRE BLACK_LEVEL = 0x3B 





Table 7-311. Register Call Summary for Register VENC_BLACK_LEVEL 








Table 7-312. VENC_BLANK_LEVEL 


Description Video Encoder BLANK LEVEL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved BLANK 



6:0 BLANK Blank level setting. Following are typical programming examples for RW 0x38 


NTSC with 7.5 IRE pedestal: WHITE - BLACK = 92.5 IRE BLANK_LEVEL = 

0x38 

NTSC with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x38 

PAL with no pedestal: WHITE - BLACK = 100 IRE BLANK_LEVEL = 0x3B 

Table 7-313. Register Call Summary for Register VENC_BLANK_LEVEL 








Table 7-314. VENC_X_COLOR 


Description Cross-Color Control Register 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved XCBW LCD 



6 XCE Cross color reduction enable for composite video output. Cross color does RW 0 

not affect S-video output 

0x0: Cross color reduction is disabled 

0x1: Cross color is enabled 



XCE 

Reserved 

1875




5 Reserved Reserved. Read returns 0. RW 0 

4:3 XCBW Cross color reduction filter selection RW 0x0 

0x0: The notch is at 32.8 % of the frequency of the encoding pixel clock 




2:0 LCD These three bits can be used for chroma channel delay compensation. RW 0x0 

Delay on Luma channel. 

0x0: 0 

0x1: 0.5 pixel clock period 



0x4: -2.0 pixel clock period 




Table 7-315. Register Call Summary for Register VENC_X_COLOR 






Table 7-316. VENC_M_CONTROL 


Description VENC_M_CONTROL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved CBW 



7 PALI PAL I enable RW 0 

0x0: Normal operation 

0x1: PAL I enable 

6 PALN PAL N enable RW 0 

0x0: Normal operation 

0x1: PAL N enable 

5 PALPHS PAL switch phase setting RW 0 

0x0: PAL switch phase is nominal 

0x1: PAL switch phase is inverted compared to nominal 

4:2 CBW Chrominance lowpass filter bandwidth control RW 0x0 

0x0: -6db at 21.8 % of encoding pixel clock frequency 





PALI 

PALN 

PALPHS 

PAL 

FFRQ




0x3: Reserved 

0x4: Reserved 



0x7: Chrominance lowpass filter bypass 

1 PAL Phase alternation line encoding selection RW 0 

0x0: Phase alternation line encoding disabled 

0x1: Phase alternation line encoding enabled 

0 FFRQ The value of this field and the SQP bit in the VENC_BSTAMP_WSS_DATA[7] RW 1 

SQP bit control the number of horizontal pixels displayed per scan line 

Mode: Configuration: 

ITU-R 601 NTSC SQP = 0, FFRQ = 1, Number of pixels by line = 858 

Square pixel NTSC SQP = 1, FFRQ = 1, Number of pixels by line = 780 

ITU-R 601 PAL SQP = 0, FFRQ = 0, Number of pixels by line = 864 

Square pixel PAL SQP = 1, FFRQ = 0, Number of pixels by line = 944 

Table 7-317. Register Call Summary for Register VENC_M_CONTROL 









Table 7-318. VENC_BSTAMP_WSS_DATA 


Description VENC BSTAMP and WSS_DATA 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved WSS_DATA BSTAP 



27:8 WSS_DATA WSS data [19:0]: Wide Screen Signaling data RW 0x00000 

NTSC: WORD 0 WSS_D1, WSS_D0 

WORD 1 WSS_D5, WSS_D4, WSS_D3, WSS_D2 

WORD 2 WSS_D13, WSS_D12, WSS_D11, WSS_D10, 

WSS_D9, WSS_D8, WSS_D7, WSS_D6 

CRC WSS_D19, WSS_D18, WSS_D17, WSS_D16, 

WSS_D15, WSS_D14 

PAL: GROUP A WSS_D3, WSS_D2, WSS_D1, WSS_D0 

GROUP B WSS_D7, WSS_D6, WSS_D5, WSS_D4 

GROUP C WSS_D10, WSS_D9, WSS_D8 

GROUP D WSS_D13, WSS_D12, WSS_D11 

7 SQP Square-pixel sampling rate. Please refer to VENC_M_CONTROL[0] FFRQ RW 0 

bit description for programming information. 



SQP 

1877




0x0: ITU-R 601 sampling rate 

0x1: Square-pixel sampling rate 

6:0 BSTAP Setting of amplitude of color burst. RW 0x38 

Table 7-319. Register Call Summary for Register VENC_BSTAMP_WSS_DATA 


• Subcarrier and Burst Generation: [0] 

• Wide-Screen Signaling (WSS) Encoding: [1] 







Table 7-320. VENC_S_CARR 


Description Color Subcarrier Frequency Registers. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


FSC 

31:0 FSC These four bytes' data program the color subcarrier frequency and are RW 0x21F07C1F 

determined by the following formula. 

S_CARR = ROUND((Fsc/Fclkenc) * 2 32 ) 

Where: Fsc = Frequency of the subcarrier 

Fclkenc = Frequency of the internal video encoding clock = 2*LLEN *Fh 

LLEN = Number of pixels in a scan line. For LLEN setting, please refer 

to the description of VENC_LLEN register (offset 0x1C). 

Fh = Line frequency 

For typical setting of the FSC field, refer to Table 7-42. 

Table 7-321. Register Call Summary for Register VENC_S_CARR 












Table 7-322. VENC_LINE21 


Description VENC LINE 21 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

L21E L21O 


31:16 L21E The two bytes of the closed-caption data in the even field. For a RW 0x0000 

complete field description, refer to CEA-608-x standard. For data stream 

content, see Table 7-43, Closed-Caption Data Format. 

[31:24] First byte of data 

[23:16] Second byte of data 

15:0 L21O The two bytes of the closed caption data in the odd field. For a complete RW 0x0000 

field description, refer to CEA-608-x standard. For data stream content, 

see Table 7-43, Closed-Caption Data Format. 

[15:8] First byte of data 

[7:0] Second byte of data 


• Closed Caption Encoding: [0] [1] [2] [3] 



Table 7-323. Register Call Summary for Register VENC_LINE21 




Table 7-324. VENC_LN_SEL 


Description VENC_LN_SEL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved LN21_RUNIN Reserved SLINE 



25:16 LN21_RUNIN The two bytes of the closed caption run in code position from the RW 0x10B 

HSYNC. 




1879




4:0 SLINE Selects the line where closed caption or extended service data are RW 0x15 

encoded. The value of the SLINE[4:0] bit field depends on the video 

standard: 


• Closed Caption Encoding: [0] [1] [2] 

PAL mode: Because there is a one-line offset, program the desired 

line number – 1. 

To activate the closed caption on line 21 (0x15), program the value 

0x15 – 1 = 0x14. The default value is 0x15 + 1 = 0x16 (line 22). 

NTSC mode: Because there is a four-line offset, program the desired 

line number – 4. 

To activate the closed caption on line 21 (0x15), program the value 

0x15 – 4 = 0x11. The default value is 0x15 + 4 = 0x19 (line 25). 

Table 7-325. Register Call Summary for Register VENC_LN_SEL 







Table 7-326. VENC_L21_WC_CTL 


Description VENC L21 WC_CTL registers 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

INV 

EVEN_ODD_EN 

Reserved LINE Reserved L21EN 



15 INV WSS inverter RW 0 

0x0: No effect 

0x1: Invert WSS data 

14:13 EVEN_ODD_EN This bit controls the WSS encoding. RW 0x0 

0x0: WSS encoding OFF 

0x1: Enables encoding in 1 st field (odd field) 

0x2: Enables encoding in 2 nd field (even field) 

0x3: Enables encoding in both fields 

12:8 LINE Selects the line where WSS data are encoded. The LINE[12:8] bit field RW 0x14 

value depends on the video standard: 

PAL mode: There is an one line offset, so program the wanted line 

number - 1. The recommended value is line 0x16 + 1 = 0x17 (23rd line). 

The default value is 0x14 + 1 = 0x15 (line 21). 

NTSC mode: There is a four line offset, so program the wanted line 

number - 4. The recommended value is line 0x10 + 4 = 0x14 (20th line). 

The default value is 0x14 + 4 = 0x18 (line 24). 







1:0 L21EN Those bits controls the Line21 closed caption encoding according to the RW 0x0 

mode. 

0x0: Line21 encoding OFF 

0x1: Enables encoding in 1st field (odd field) 

0x2: Enables encoding in 2d field (even field) 

0x3: Enables encoding in both fields 

Table 7-327. Register Call Summary for Register VENC_L21_WC_CTL 


• Closed Caption Encoding: [0] [1] 

• Wide-Screen Signaling (WSS) Encoding: [2] [3] 






Table 7-328. VENC_HTRIGGER_VTRIGGER 


Description VENC HTRIGGER and VTRIGGER 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VTRIG Reserved HTRIG 



25:16 VTRIG Vertical trigger reference for VSYNC. These bits specify the phase RW 0x000 

between VSYNC input and the lines in a field. The VTRIG field is 

expressed in units of half-line. 


10:0 HTRIG Horizontal trigger phase, which sets HSYNC. HTRIG is expressed in RW 0x000 

half-pixels or clk2x (27 MHz) periods 

Table 7-329. Register Call Summary for Register VENC_HTRIGGER_VTRIGGER 






Table 7-330. VENC_SAVID_EAVID 


Description VENC SAVID and EAVID 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved EAVID Reserved SAVID 



1881





26:16 EAVID End of active video. These bits define the ending pixel position on a RW 0x693 

horizontal display line where active video will be displayed. 


10:0 SAVID Start of active video. These bits define the starting pixel position on a RW 0x0F4 

horizontal line where active video will be displayed. 

Table 7-331. Register Call Summary for Register VENC_SAVID_EAVID 







Table 7-332. VENC_FLEN_FAL 


Description VENC FLEN and FAL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FAL Reserved FLEN 



24:16 FAL First Active Line of Field. These bits define the first active line of a field RW 0x016 


9:0 FLEN Field length. These bits define the number of half_lines in each field. RW 0x20C 

Length of field = (FLEN + 1) half_lines 

Table 7-333. Register Call Summary for Register VENC_FLEN_FAL 







Table 7-334. VENC_LAL_PHASE_RESET 


Description VENC LAL and PHASE_RESET 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

SBLANK 

Reserved PRES Reserved LAL 







18:17 PRES Phase reset mode. RW 0x3 

0x0: No reset 

0x1: Reset every two lines 

0x2: Reset every eight fields. Color subcarrier phase is reset to 

VENC_CPHASE[7:0] CPHS field value (offset 0x2C) upon reset 

0x3: Reset every four fields. Color subcarrier phase is reset to 

VENC_CPHASE[7:0] CPHS bit field value (offset 0x2C) upon 

reset 

16 SBLANK Data output enable RW 0 

0x0: No functionality 

0x1: Enables the output of data when VENC_SYNC_CTRL[10] 

VBLMK bit is '0b1'. 


8:0 LAL Last Active Line of Field. These bits define the last active line of a field. The RW 0x107 

LAL[8:0] bit field value must be set to a value lower than the active window. 

Table 7-335. Register Call Summary for Register VENC_LAL_PHASE_RESET 







Table 7-336. VENC_HS_INT_START_STOP_X 


Description VENC_HS_INT_START_STOP_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved HS_INT_STOP_X Reserved HS_INT_START_X 



25:16 HS_INT_STOP_X HSYNC internal stop. These bits define HSYNC internal stop pixel RW 0x07E 

value 


9:0 HS_INT_START_X HSYNC internal start. These bits define HSYNCI NTERNAL start RW 0x34E 

pixel value 

Table 7-337. Register Call Summary for Register VENC_HS_INT_START_STOP_X 








1883




Table 7-338. VENC_HS_EXT_START_STOP_X 


Description VENC_HS_EXT_START_STOP_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved HS_EXT_STOP_X Reserved HS_EXT_START_X 



25:16 HS_EXT_STOP_X HSYNC external stop. These bits define HSYNC external stop pixel RW 0x00F 

value 


9:0 HS_EXT_START_X HSYNC external start. These bits define HSYNC EXTERNAL start RW 0x359 

pixel value 

Table 7-339. Register Call Summary for Register VENC_HS_EXT_START_STOP_X 







Table 7-340. VENC_VS_INT_START_X 


Description VENC_VS_INT_START_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VS_INT_START_X Reserved 



25:16 VS_INT_START_X VSYNC internal start. These bits define VSYNC internal start pixel RW 0x1A0 

value. 


Table 7-341. Register Call Summary for Register VENC_VS_INT_START_X 











Table 7-342. VENC_VS_INT_STOP_X_VS_INT_START_Y 


Description VENC VS_INT_STOP_X and VS_INT_START_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VS_INT_START_Y Reserved VS_INT_STOP_X 



25:16 VS_INT_START_Y VSYNC internal start. These bits define VSYNC INTERNAL start line RW 0x209 

value 


9:0 VS_INT_STOP_X VSYNC internal stop. These bits define VSYNC internal stop pixel RW 0x1A0 

value 

Table 7-343. Register Call Summary for Register VENC_VS_INT_STOP_X_VS_INT_START_Y 






Table 7-344. VENC_VS_INT_STOP_Y_VS_EXT_START_X 


Description VENC VS_INT_STOP_Y and VS_EXT_START_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VS_EXT_START_X Reserved VS_INT_STOP_Y 



25:16 VS_EXT_START_X VSYNC external start. These bits define VSYNC external start pixel RW 0x1AC 

value. 


9:0 VS_INT_STOP_Y VSYNC internal stop. These bits define VSYNC INTERNAL stop line RW 0x022 

value. 

Table 7-345. Register Call Summary for Register VENC_VS_INT_STOP_Y_VS_EXT_START_X 







1885




Table 7-346. VENC_VS_EXT_STOP_X_VS_EXT_START_Y 


Description VENC VS_EXT_STOP_X and VS_EXT_START_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VS_EXT_START_Y Reserved VS_EXT_STOP_X 



25:16 VS_EXT_START_Y VSYNC external start. These bits define VSYNC EXTERNAL RW 0x20D 

start line value. 


9:0 VS_EXT_STOP_X VSYNC external stop. These bits define VSYNC EXTERNAL RW 0x1AC 

stop pixel value. 

Table 7-347. Register Call Summary for Register VENC_VS_EXT_STOP_X_VS_EXT_START_Y 






Table 7-348. VENC_VS_EXT_STOP_Y 


Description VENC VS_EXT_STOP_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved VS_EXT_STOP_Y 



9:0 VS_EXT_STOP_Y VSYNC external stop. These bits define VSYNC EXTERNAL RW 0x006 

stop line value. 

Table 7-349. Register Call Summary for Register VENC_VS_EXT_STOP_Y 










Table 7-350. VENC_AVID_START_STOP_X 


Description VENC_AVID_START_STOP_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved AVID_STOP_X Reserved AVID_START_X 



25:16 AVID_STOP_X AVID stop. These bits define AVID stop pixel value RW 0x348 


9:0 AVID_START_X AVID start. These bits define AVID start pixel value RW 0x078 

Table 7-351. Register Call Summary for Register VENC_AVID_START_STOP_X 







Table 7-352. VENC_AVID_START_STOP_Y 


Description VENC_AVID_START_STOP_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved AVID_STOP_Y Reserved AVID_START_Y 



25:16 AVID_STOP_Y AVID stop. These bits define AVID stop line value. RW 0x206 


9:0 AVID_START_Y AVID start. These bits define AVID start line value RW 0x026 

Table 7-353. Register Call Summary for Register VENC_AVID_START_STOP_Y 








1887



Address Offset 0xA0 

Table 7-354. VENC_FID_INT_START_X_FID_INT_START_Y 

Physical address 0x4805 0CA0 Instance VENC 

Description VENC_FID_INT_START_X and FID_INT_START_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FID_INT_START_Y Reserved FID_INT_START_X 



25:16 FID_INT_START_Y FID internal start. These bits define FID internal start line value RW 0x001 


9:0 FID_INT_START_X FID internal start. These bits define FID internal start pixel value RW 0x08A 

Table 7-355. Register Call Summary for Register VENC_FID_INT_START_X_FID_INT_START_Y 






Table 7-356. VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 


Description VENC FID_INT_OFFSET_Y and FID_EXT_START_X 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FID_EXT_START_X Reserved FID_INT_OFFSET_Y 



25:16 FID_EXT_START_X FID external start. These bits define FID external start pixel value RW 0x1AC 


9:0 FID_INT_OFFSET_Y FID internal offset. These bits define FID internal offset linel value RW 0x106 

Table 7-357. Register Call Summary for Register VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 










Table 7-358. VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 


Description VENC FID_EXT_START_Y and FID_EXT_OFFSET_Y 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved FID_EXT_OFFSET_Y Reserved FID_EXT_START_Y 



25:16 FID_EXT_OFFSET_Y FID external offset. These bits define FID external offset line value RW 0x106 


9:0 FID_EXT_START_Y FID external start. These bits define FID external start line value. RW 0x006 

Table 7-359. Register Call Summary for Register VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 





Address Offset 0xB0 

Table 7-360. VENC_TVDETGP_INT_START_STOP_X 

Physical address 0x4805 0CB0 Instance VENC 

Description TV Detection Start and Stop pixel values 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved TVDETGP_INT_STOP_X Reserved TVDETGP_INT_START_X 



25:16 TVDETGP_INT_STOP_X TVDETGP internal stop. These bits define TVDETGP internal RW 0x014 

stop pixel value. 


9:0 TVDETGP_INT_START_X TVDETGP internal start. These bits define TVDETGP internal RW 0x001 

start pixel value 

Table 7-361. Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_X 


• TV Detection/Disconnection Pulse Generation: [0] 

• TV Detection Procedure: [1] [2] [3] 

• TV Disconnection Procedure: [4] [5] [6] 

• Recommended TV Detection/Disconnection Pulse Waveform: [7] 










Table 7-362. VENC_TVDETGP_INT_START_STOP_Y 


Description TV detection Start and Stop line values 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved TVDETGP_INT_STOP_Y Reserved TVDETGP_INT_START_Y 



25:16 TVDETGP_INT_STOP_Y TVDETGP internal stop. These bits define TVDETGP internal RW 0x001 

stop line value. 


9:0 TVDETGP_INT_START_Y TVDETGP internal start. These bits define TVDETGP internal RW 0x001 

start line value. 

Table 7-363. Register Call Summary for Register VENC_TVDETGP_INT_START_STOP_Y 


• TV Detection/Disconnection Pulse Generation: [0] 

• TV Detection Procedure: [1] [2] [3] 

• TV Disconnection Procedure: [4] [5] [6] 






Table 7-364. VENC_GEN_CTRL 


Description TVDETGP enable and SYNC_POLARITY and UVPHASE_POL 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

Reserved Reserved EN 

MS 

656 

CBAR 

HIP 

VIP 

HEP 

VEP 

AVIDP 

FIP 

FEP 

TVDP 



26 MS UVPHASE_POL MS mode UV phase RW 0 

0x0: CbCr 

0x1: CrCb 

25 656 UVPHASE_POL 656 input mode UV phase RW 0 

0x0: CbCr 

0x1: CrCb 

24 CBAR UVPHASE_POL CBAR mode UV phase RW 0 

0x0: CbCr 

0x1: CrCb 

23 HIP HSYNC internal polarity RW 1 








22 VIP VSYNC internal polarity RW 1 



21 HEP HSYNC external polarity RW 1 



20 VEP VSYNC external polarity RW 1 



19 AVIDP AVID polarity RW 1 



18 FIP FID internal polarity RW 1 



17 FEP FID external polarity RW 1 



16 TVDP TVDETGP polarity RW 1 




0 EN TVDETGP generation enable RW 0 

0x0: Disabled 

0x1: Enabled 

Table 7-365. Register Call Summary for Register VENC_GEN_CTRL 


• TV Detection/Disconnection Pulse Generation: [0] [1] 

• TV Detection Procedure: [2] [3] 

• TV Disconnection Procedure: [4] [5] 





Address Offset 0x0000 00C4 

Table 7-366. VENC_OUTPUT_CONTROL 

Physical Address 0x4805 0CC4 Instance VENC 

Description Output channel control register Also contains some test control features 

Type RW 



1891



31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED LUMA_TEST RESERVED 


31:26 RESERVED Reserved. Read returns 0s. RW 0x00 

25:16 LUMA_TEST In test mode, DAC 1 input value RW 0x000 

(if s-video video mode is selected) 


7 CHROMA_SOURCE Source of chroma video data in test mode RW 0x0 

0x0: Chroma test data comes from internal register 

OUTPUT_TEST[25:16] 

0x1: Chroma test data comes from display controller video port 

G[1:0], B[7:0] 

6 COMPOSITE_ Source of composite video data in test mode RW 0x0 

SOURCE 

0x0: Composite test data comes from internal register 

OUTPUT_TEST[9:0] 

0x1: Composite test data comes from display controller video port 

G[1:0], B[7:0] 

5 LUMA_SOURCE Source of luminance video data in test mode RW 0x0 

0x0: Luma test data comes from internal register 

OUTPUT_CONTROL[25:16] 

0x1: Luma test data comes from display controller video port G[1:0], 

B[7:0] 

4 TEST_MODE This enables the video DACs to be tested. The values sent to the RW 0x0 

DACs comes from a register for each output channel (Luma, 

Composite or Chroma) or from the display controller video port bits 

G[1:0], B[7:0], depending on the setting of the Source bits 

0x0: Video outputs are in normal operation 

0x1: Test mode. Video outputs are directly connected to either 

internal registers or the display controller video port. 

3 VIDEO_INVERT Controls the video output polarity. This may be used to correct for RW 0x1 

inversion in an external video amplifier. 

0x0: Video outputs are inverted 

0x1: Video outputs are normal polarity 

2 CHROMA_ENABLE Enable the Chrominance output channel RW 0x0 

0x0: Chroma output is disabled 

0x1: Chroma output is enabled 

1 COMPOSITE_ Enable the Composite output channel RW 0x0 

ENABLE 

0x0: Composite output is disabled 

0x1: Composite output is enabled 

0 LUMA_ENABLE Enable the Luminance output channel RW 0x0 

0x0: Luma output is disabled 

0x1: Luma output is enabled 



CHROMA_SOURCE 

COMPOSITE_SOURCE 

LUMA_SOURCE 

TEST_MODE 

VIDEO_INVERT 

CHROMA_ENABLE 

COMPOSITE_ENABLE 

LUMA_ENABLE



Table 7-367. Register Call Summary for Register VENC_OUTPUT_CONTROL 


• TV Display Support: [0] [1] 


• TV Detection Procedure: [2] [3] 

• TV Disconnection Procedure: [4] [5] 

• Video DAC Stage Test Mode: [6] [7] [8] [9] [10] 

• Video DAC Stage Power Management: [11] [12] [13] 


• Video DAC Stage Settings: [14] [15] [16] 




Address Offset 0x0000 00C8 

Table 7-368. VENC_OUTPUT_TEST 

Physical Address 0x4805 0CC8 Instance VENC 

Description Test values for the Luma/Composite Video DAC1 (if composite video is selected) and the Chroma Video 

DAC2 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED CHROMA_TEST RESERVED COMPOSITE_TEST 



25:16 CHROMA_TEST In test mode, DAC 2 input value RW 0x000 


9:0 COMPOSITE_TEST In test mode, DAC 1 input value (if composite video is selected) RW 0x000 

Table 7-369. Register Call Summary for Register VENC_OUTPUT_TEST 


• Video DAC Stage Test Mode: [0] [1] 





7.7.2.5 DSI Protocol Engine Registers 



1893




Table 7-370. DSI_REVISION 

Physical Address 0x4804 FC00 Instance DSI_PROTOCOL_ENGINE 

Description MODULE REVISION This register contains the IP revision code in binary coded digital. For example, we 

have: 0x01 = revision 0.1 and 0x21 = revision 2.1 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED REV 


31:8 RESERVED Write 0s for future compatibility. R 0x000000 

Reads returns 0. 




Table 7-371. Register Call Summary for Register DSI_REVISION 


• DSI Protocol Engine Register Mapping Summary: [0] 


Table 7-372. DSI_SYSCONFIG 


Description SYSTEM CONFIGURATION REGISTER This register is the system configuration register. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 






9:8 CLOCKACTIVITY Clocks activity during wake up mode period RW 0x0 

0x0: Interface and Functional clocks can be switched off 

0x1: Functional clocks can be switched off and Interface clocks are 

maintained during wake up period 

0x2: Interface clocks can be switched off and Functional clocks are 

maintained during wake up period 

0x3: Interface and Functional clocks are maintained during wake up 

period 





CLOCKACTIVITY 

RESERVED 

SIDLEMODE 

ENWAKEUP 

SOFT_RESET 

AUTO_IDLE




4:3 SIDLEMODE Slave interface power management, Idle req/ack control RW 0x2 

0x0: Force-idle. An idle request is acknowledged unconditionally 

0x1: No-idle. An idle request is never acknowledged 

0x2: Smart-idle. Acknowledgement to an idle request is given based on 

the internal activity of the module. 

0x3: Reserved 

2 ENWAKEUP Wake-up mode enable bit RW 0x0 

0x0: Wakeup is disabled. 

0x1: Wakeup is enabled, 

1 SOFT_RESET Software reset. Set the bit to 1 to trigger a module reset. The bit is RW 0x0 

automatically reset by the hw. During reads return 0. 

0x0: Normal mode. 

0x1: The module is reset 

0 AUTO_IDLE Internal interface clock gating strategy RW 0x1 



• Clock Activity Mode: [1] [2] [3] 


• Idle Mode: [5] [6] [7] 

0x0: Interface clock is free-running. 

0x1: Automatic Interface clock gating strategy is applied based on the 

module interface activity. 

Table 7-373. Register Call Summary for Register DSI_SYSCONFIG 



• Power Management: [9] [10] 



• Reset DSI Modules: [12] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [13] [14] [15] 




Table 7-374. DSI_SYSSTATUS 


Description SYSTEM STATUS REGISTER This register provides status information about the module, excluding the 

interrupt status register. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 



RESET_DONE 

1895




31:1 RESERVED Reads returns 0. R 0x00000000 

0 RESET_DONE Internal reset monitoring R 0x1 

0x0: Internal module reset is on going. 

0x1: Reset completed. 

Table 7-375. Register Call Summary for Register DSI_SYSSTATUS 


• Software Reset: [0] [1] 



• Set Up DSI Protocol Engine: [3] 





Table 7-376. DSI_IRQSTATUS 


Description INTERRUPT STATUS REGISTER - All VCs + complex I/O + PLL This register associates one bit for 

each VC to determine which VC has generated the interrupt. The VC should be enabled for events to be 

generated on that VC. If the VC is disabled, the interrupt is not generated. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 

TA_TO_IRQ 

LDO_POWER_GOOD_IRQ 

SYNC_LOST_IRQ 

ACK_TRIGGER_IRQ 

TE_TRIGGER_IRQ 




20 TA_TO_IRQ Turn-around Time out. RW 0x0 

LP_RX_TO_IRQ 

HS_TX_TO_IRQ 

0x0: READS: Event is false. 

WRITES: Status bit unchanged. 

RESERVED 

0x1: READS: Event is true (pending). 

WRITES: Status bit is reset. 

19 LDO_POWER_ Transition of the status signal LDOPWRGOOD from the RW 0x0 

GOOD_IRQ DSI_PHY indicating a state change for the supply 







RESERVED 

COMPLEXIO_ERR_IRQ 


PLL_RECAL_IRQ 

PLL_UNLOCK_IRQ 

PLL_LOCK_IRQ 

RESERVED 

RESYNCHRONIZATION_IRQ 

WAKEUP_IRQ 




VIRTUAL_CHANNEL0_IRQ




18 SYNC_LOST_IRQ Synchronization with Video port is lost (Video mode only) RW 0x0 





17 ACK_TRIGGER_IRQ Acknowledge Trigger RW 0x0 





16 TE_TRIGGER_IRQ Tearing Effect Trigger RW 0x0 





15 LP_RX_TO_IRQ Interrupt for Low Power Rx Time out RW 0x0 





14 HS_TX_TO_IRQ Interrupt for high-speed Tx Time out. RW 0x0 





13 RESERVED Write 0s for future compatibility. RW 0x0 




10 COMPLEXIO_ Error signaling from complex I/O: status of the complex I/O R 0x0 

ERR_IRQ errors received from the complex I/O(events are defined in 

DSI_COMPLEXIO_IRQSTATUS). 



9 PLL_RECAL_IRQ PLL recalibration event (assertion of recalibration signal from the RW 0x0 

DSI PLL Control module) 





8 PLL_UNLOCK_IRQ PLL un-lock event (de-assertion of lock signal from the DSI PLL RW 0x0 

Control module) 





7 PLL_LOCK_IRQ PLL lock event (assertion of lock signal from the DSI PLL RW 0x0 








5 RESYNCHRONIZATION_ Video mode resynchronization RW 0x0 

IRQ 



1897




Indicates that the video port works but the configuration of the 

timings for the display controller (DISPC) and for DSI protocol 

engine may have to be modified to avoid the resynchronization 

to occur. 

0x0: READS: Event is false. WRITES: Status bit unchanged. 

0x1: READS: Event is true (pending). WRITES: Status bit is 

reset. 

4 WAKEUP_IRQ Wakeup RW 0x0 





3 VIRTUAL_CHANNEL3_ Virtual channel #3 R 0x0 

IRQ 

Error signaling from DSI Virtual Channel3: Status of DSI Virtual 

Channel3 errors received from DSI Virtual Channel3 (events are 

defined in DSI_VC3_IRQSTATUS). 




IRQ 







IRQ 







IRQ 

Error signaling from DSI Virtual Channel0: Status of the DSI 

Virtual Channel0 errors received from DSI Virtual Channel0 

(events are defined in DSI_VC0_IRQSTATUS). 


• DSI Interrupt Request: [0] 


• HS TX Timer: [1] 

• LP RX Timer: [2] 

• Tearing Effect: [3] 

• Acknowledge: [4] 

• Error Handling: [5] [6] [7] 



Table 7-377. Register Call Summary for Register DSI_IRQSTATUS 


• Interrupts: [8] [9] 

• Video Mode: [10] [11] 

• DSI PLL Error Handling: [12] [13] [14] [15] [16] [17] 

• Error Handling: [18] 



• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [20] 





Table 7-377. Register Call Summary for Register DSI_IRQSTATUS (continued) 



• Display Subsystem Registers: [22] 

Address Offset 0x0000 001C 

Table 7-378. DSI_IRQENABLE 

Physical Address 0x4804 FC1C Instance DSI_PROTOCOL_ENGINE 

Description INTERRUPT ENABLE REGISTER - This register associates one bit for each VC to enable/disable each 

VC individually. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

TA_TO_IRQ_EN 

LDO_POWER_GOOD_IRQ_EN 

SYNC_LOST_IRQ_EN 

ACK_TRIGGER_IRQ_EN 

TE_TRIGGER_IRQ_EN 





20 TA_TO_IRQ_EN Turn-around Time out. RW 0x0 

0x0: Event is masked 

LP_RX_TO_IRQ_EN 

HS_TX_TO_IRQ_EN 

RESERVED 

RESERVED 

RESERVED 

0x1: Event generates an interrupt when it occurs 

19 LDO_POWER_GOOD_ Transition of the status signal LDOPWRGOOD from the RW 0x0 

IRQ_EN DSI_PHY indicating a state change for the supply 




18 SYNC_LOST_IRQ_EN Synchronization with Video port is lost (Video mode only) RW 0x0 



17 ACK_TRIGGER_IRQ_EN Acknowledge trigger RW 0x0 



16 TE_TRIGGER_IRQ_EN Tearing Effect trigger RW 0x0 



15 LP_RX_TO_IRQ_EN Interrupt for Low Power Rx Time out. RW 0x0 



14 HS_TX_TO_IRQ_EN Interrupt for high-speed Tx Time out. RW 0x0 





PLL_RECAL_IRQ_EN 

PLL_UNLOCK_IRQ_EN 

PLL_LOCK_IRQ_EN 

RESERVED 

RESYNCHRONIZATION_IRQ_EN 

WAKEUP_IRQ_EN 

1899










9 PLL_RECAL_IRQ_EN PLL recalibration event (assertion of recalibration signal from RW 0x0 

the DSI PLL Control module) 



8 PLL_UNLOCK_IRQ_EN PLL un-lock event (de-assertion of lock signal from the DSI RW 0x0 

PLL Control module) 



7 PLL_LOCK_IRQ_EN PLL lock event (assertion of lock signal from the DSI PLL RW 0x0 






5 RESYNCHRONIZATION_ Resynchronization RW 0x0 

IRQ_EN 



4 WAKEUP_IRQ_EN Wakeup RW 0x0 








Table 7-379. Register Call Summary for Register DSI_IRQENABLE 


• Interrupts: [2] 







Table 7-380. DSI_CTRL 


Description GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register 

should not be modified dynamically (except IF_EN bit field). 

Type RW 





31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 

RGB565_ORDER 

DCS_CMD_CODE 

DCS_CMD_ENABLE 

HSA_BLANKING_MODE 

HBP_BLANKING_MODE 

HFP_BLANKING_MODE 

BLANKING_MODE 

EOT_ENABLE 

VP_HSYNC_END 

VP_HSYNC_START 

VP_VSYNC_END 




26 RGB565_ORDER Byte order for RBG565 command mode from video port RW 0 

0x0: 

VP_VSYNC_START 

0x1: Byte order as for video mode 

25 DCS_CMD_CODE DCS command code value to insert between header and video port RW 0 

data when enabled by DCS_CMD_ENABLE 

TRIGGER_RESET_MODE 

LINE_BUFFER 

0x0: DCS write memory continue code is inserted. 

0x1: DCS write memory start code is inserted. 

24 DCS_CMD_ENABLE Enables automatic insertion of DCS command codes when data is RW 0 

sourced by the video port. 

0x0: DCS command code is not inserted when command mode 

traffic is coming from the Video Port. 

0x1: DCS command code is inserted automatically when command 

mode traffic is coming from the Video Port. 

23 HSA_BLANKING_ Blanking mode RW 0x0 

MODE 

0x0: Packets in TX FIFO are sent during HSA blanking period of 

video mode or LPS is used. 

VP_VSYNC_POL 

VP_HSYNC_POL 

VP_DE_POL 

0x1: LONG BLANKING PACKETS only are used during HSA 

blanking period of video mode. 

22 HBP_BLANKING_ Blanking mode RW 0x0 

MODE 

0x0: Packets in TX FIFO are sent during HBP blanking period of 


0x1: LONG BLANKING PACKETS only are used during HBP 


21 HFP_BLANKING_ Blanking mode RW 0x0 

MODE 

0x0: Packets in TX FIFO are sent during HFP blanking period of 


0x1: LONG BLANKING PACKETS only are used during HFP 


20 BLANKING_MODE Blanking mode RW 0x0 

0x0: LPS is used during blanking periods of video mode (except 

HSA, HBP, HFP defined in HSA_BLANKING_MODE, 

HBP_BLANKING_MODE and HFP_BLANKING_MODE bit fields 

respectively) when there is no command mode data in TX FIFO 

ready to be sent. So blanking periods can be different during the 

frame depending on the TX FIFO. 

0x1: LONG BLANKING PACKETS are used during blanking periods 

of video mode (except HSA, HBP, HFP defined in 

HSA_BLANKING_MODE, HBP_BLANKING_MODE and 

HFP_BLANKING_MODE bit fields respectively) regardless of the 

packets present in the TX FIFO ready to be sent 

19 EOT_ENABLE Enable EOT packets at the end of HS transmission. RW 0 

0x0: No EOT packets 

0x1: EOT packet is sent at all HS to LP transitions 



VP_CLK_POL 

VP_DATA_BUS_WIDTH 

TRIGGER_RESET 

VP_CLK_RATIO 

TX_FIFO_ARBITRATION 

ECC_RX_EN 

CS_RX_EN 

IF_EN 

1901




18 VP_HSYNC_END HSYNC end pulse. RW 0x0 

0x0: Disabled. No HSYNC END short packet is generated. 

0x1: Enabled. While the HSYNC END pulse is detected, the 

associated short packet HSYNC END is generated. 

17 VP_HSYNC_START HSYNC start pulse. RW 0x0 

0x0: Disabled. No HSYNC START short packet is generated. 

0x1: Enabled. While the HSYNC start pulse is detected, the 

associated short packet HSYNC START is generated. 

16 VP_VSYNC_END VSYNC end pulse. RW 0x0 

0x0: Disabled. No VSYNC END short packet is generated. 

0x1: Enabled. While the VSYNC END pulse is detected, the 

associated short packet VSYNC END is generated. 

15 VP_VSYNC_START VSYNC start pulse. RW 0x0 

0x0: Disabled. No VSYNC START short packet is generated. 

0x1: Enabled. While the VSYNC START pulse is detected, the 

associated short packet VSYNC START is generated. 

14 TRIGGER_RESET_ Selection of the trigger reset mode RW 0x0 

MODE 

0x0: Synchronized: the mode is only valid if there is VC using the 

video mode and it is active. The principle is to wait for the current 

video frame to be transferred on the link. Any data received after the 

VSYNC are ignored. 

0x1: Immediate: all pending requests in TX FIFO are taken into 

account for transfer scheduling, the RX FIFO is ignored, and the 

data from video port are ignored as soon as possible. Only the 

current transfer on DSI link and already scheduled ones are 

transmitted. All the other transfers are discarded. 

13:12 LINE_BUFFER Number of line buffers to be used while receiving data on the video RW 0x0 

port. 

0x0: No line buffer 

0x1: 1 line buffer 

0x2: 2 line buffers 

11 VP_VSYNC_POL VP vertical synchronization signal polarity RW 0x0 

0x0: VSYNC signal on the video port is active low. 

0x1: VSYNC signal on the video port is active high. 

10 VP_HSYNC_POL VP horizontal synchronization signal polarity RW 0x0 

0x0: HSYNC signal on the video port is active low. 

0x1: HSYNC signal on the video port is active high. 

9 VP_DE_POL VP data enable signal polarity RW 0x0 

0x0: DE signal on the video port is active low. 

0x1: DE signal on the video port is active high. 

8 VP_CLK_POL VP pixel clock polarity RW 0x1 

0x0: The DSI Protocol Engine module captures the data on the VP 

on the pixel clock falling edge. The module connected to the VP 

must drive the data on the pixel clock rising edge. 

0x1: The DSI Protocol Engine module captures the data on the VP 

on the pixel clock raising edge. The module connected to the VP 

must drive the data on the pixel clock falling edge. 

7:6 VP_DATA_BUS_ Defines the size of the video port data bus RW 0x0 

WIDTH 

0x0: 16-bits data width (LSB of the 24-bit video port data bus) 








5 TRIGGER_RESET Send the reset trigger to the peripheral. RW 0x0 

0x0: READS: Reset trigger generation is completed. It is reset by 

HW when it is completed. 

WRITES: Cancellation of the request for Reset trigger generation 

(maybe too late since it is already on going) 

0x1: READS: Generation of the reset trigger has been requested by 

user (could be on going but not completed yet). 

WRITES: Request for Reset trigger to be sent to the peripheral. 

4 VP_CLK_RATIO This bit indicates the clock ratio between VP_CLK and VP_PCLK. RW 0x0 

The clock VP_PCLK is generated from VP_CLK. It is divided down. 

The information is only used when the video port is used to provide 

data in command mode. In the case of video mode, it is not used. 

0x0: The clock VP_PCLK is the clock VP_CLK divided by 2. The 

duty cycle of VP_PCLK is 50/50. 

0x1: The clock VP_PCLK is the clock VP_CLK divided by 3 or more. 

The duty cycle of VP_PCLK is not 50/50 for odd ratio numbers 

(3,5,7,...). 

3 TX_FIFO_ Defines the arbitration scheme for granting the VC pending ready RW 0x0 

ARBITRATION requests in the TX FIFO 

0x0: Round-Robin Scheme is used 

0x1: Sequential Scheme is used 

2 ECC_RX_EN Enables the ECC check for the received header (short and long RW 0x0 

packets for all VC IDs). 

0x0: Disabled 

0x1: Enabled 

1 CS_RX_EN Enables the checksum check for the received payload (long packet RW 0x0 

only for all VC IDs). 

0x0: Disabled 

0x1: Enabled 

0 IF_EN Enables the module. When the module is disabled the signals from RW 0x0 

the complex I/O are gated (no updates of the interrupt status 

register). 

It is not possible to change the bit fields in the DSI_CTRL register, 

except IF_EN when it is enabled. All the other registers can be 

changed except the ones that require DSI_VCn_CTRL[0] VC_EN to 

be equal to 0 to be modified. 

0x0: The interface is disabled. If one of the VC uses the video mode 

with the video port to receive the data, the DSI protocol engines is 

disabled when the next VSYNC is received and all the data in the 

FIFO for the other VCs in command mode are sent to the 

peripherals (if BTA_EN bit is enabled, the DSI protocol engine needs 

to wait for the response and BTA from the peripheral before 

disabling all the internal logic since an acknowledge is requested). 

0x1: The interface is enabled immediately, the data acquisition on 

the video port starts on the next VSYNC (video mode) or first data 

received in the Slave port FIFO (command mode). 

Table 7-381. Register Call Summary for Register DSI_CTRL 


• Data/Clock Configuration: [0] [1] [2] 

• Video Port (VP) Interface: [3] [4] [5] [6] 

• Video Port Used for Video Mode: [7] [8] [9] 

• Video Port Used on Command Mode: [10] [11] [12] 





Table 7-381. Register Call Summary for Register DSI_CTRL (continued) 


• Clock Requirements: [13] 

• Command Mode: [14] [15] [16] [17] 

• DSI PLL Power Control Commands: [18] [19] [20] [21] 

• TurnRequest FSM: [22] [23] 

• HS TX Timer: [24] [25] 

• LP RX Timer: [26] [27] 

• Bus Turnaround: [28] [29] [30] [31] 

• Reset: [32] [33] [34] 


• ECC Generation: [36] 

• Checksum Generation for Long Packet Payloads: [37] 

• End of Transfer Packet: [38] 


• Global Register Controls: [39] [40] [41] [42] [43] [44] [45] 

• Packets: [46] [47] [48] [49] [50] [51] 

• Video Mode: [52] [53] [54] [55] 

• Video Port Data Bus: [56] 

• Command Mode TX FIFO: [57] [58] 





• Set Up DSI Protocol Engine: [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] 

• Enable Video Mode Using the DISPC Video Port: [76] [77] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [78] [79] [80] [81] [82] [83] [84] [85] [86] 

• Enable Command Mode Using DISPC Video Port: [87] [88] [89] [90] 



• DSI Protocol Engine Registers: [92] [93] [94] [95] [96] [97] [98] [99] 


Table 7-382. DSI_COMPLEXIO_CFG1 


Description COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane 

configuration for the order and position of the lanes (clock and data) and the polarity order for the control 

of the PHY differential signals in addition to the control bit for the power FSM. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

SHADOWING 

GOBIT 

RESET_DONE 

PWR_CMD 

PWR_STATUS 

RESERVED 

LDO_POWER_GOOD_STATE 

USE_LDO_EXTERNAL 

RESERVED 

RESERVED 


RESERVED 

RESERVED 

DATA2_POL 


DATA2_POSITION 

DATA1_POL 

DATA1_POSITION 

CLOCK_POL 

CLOCK_POSITION




31 SHADOWING Shadowing configuration. RW 0x0 

0x0: Disabled. The writes to the DSIPHY_CFG0 and DSIPHY_CFG1 

registers are done like the other SCP registers. 

0x1: Enabled. The writes to the DSIPHY_CFG0 and DSIPHY_CFG1 

registers are done only when the GO bit is set and when the signal 

DISPC_UPDATE_SYNC from the display controller module is active. 

30 GOBIT Allows the synchronized update of the shadow registers when the RW 0 

signal DISPC_UPDATE_SYNC is active. 

0x0: Resets the Gobit. The hardware has finished the update of the 

shadow SCP registers. The bit is reset by Hardware. The software 

can reset the bit in case users decide to abort it. There is no 

guarantee that the software reset is done before the transfer of the 

values to the complex I/O. 

0x1: Set the Gobit. Only when the transfer of the new values for the 

two first registers is completed (2, 1, or 0 transfers are performed 

based on the number of registers to update), the GObit is reset. The 

DISPC_UPDATE_SYNC signal is used to synchronize the update. 

The bit must be set only when it is in reset state. 

29 RESET_DONE Internal reset monitoring of the power domain using the TxByteClkHS R 1 

from the complex I/O 

0x0: Internal module reset is on going. 

0x1: Reset completed. 

28:27 PWR_CMD Command for power control of the complex I/O RW 0x0 

0x0: Command to change to OFF state 

0x1: Command to change to ON state 

0x2: Command to change to ultralow-power state 

26:25 PWR_STATUS Status of the power control of the complex I/O R 0x0 

0x0: complex I/O in OFF state 

0x1: complex I/O in ON state 

0x2: complex I/O in ultralow-power state 



21 LDO_POWER_ Indicates the state of the signal LDOPWRGOOD. VDDALDODSIPLL: R 0x0 

GOOD_STATE 1.2-V power supply for the PLL. The voltage is supplied by the internal 

or external LDO. The interrupt LDO_POWER_GOOD_IRQ is 

generated when a transition is detected on the signal LDOPWRGOOD 

from the DSI_PHY. 

0x0: VDDALDODSIPLL power supply is down 

0x1: VDDALDODSIPLL power supply is up 

20 USE_LDO_ Select the external LDO for the DSI_PHY. RW 0x0 

EXTERNAL 

0x0: DSI_PHY internal LDO is used. 

0x1: External LDO is used. DSI_PHY LDO is tri-stated. 









11 DATA2_POL +/- differential pin order of DATA lane 2. RW 0x0 

0x0: +/- pin order (dsi_dx=+ and dsi_dy=-) 

0x1: -/+ pin order (dsi_dx=- and dsi_dy=+) 



1905




10:8 DATA2_POSITION Position and order of the DATA lane 2. RW 0x0 

0x0: Not used/connected 

0x1: Data lane 2 is at the position 1 (line 1). 



Other values: reserved 

7 DATA1_POL +/- differential pin order of DATA lane 1 RW 0x0 



6:4 DATA1_POSITION Position and order of the DATA lane 1. RW 0x0 





3 CLOCK_POL +/- differential pin order of CLOCK lane. RW 0x0 



2:0 CLOCK_POSITION Position and order of the CLOCK lane. RW 0x0 

The clock lane is always present. 

0x1: Clock lane is at the position 1 (line 1). 




Table 7-383. Register Call Summary for Register DSI_COMPLEXIO_CFG1 


• Data/Clock Configuration: [0] [1] 


• DSI Protocol Architecture: [2] 

• Shadowing Register: [3] [4] [5] [6] [7] [8] [9] 

• Complex I/O Power Control Commands: [10] [11] 


• Exiting ULPS: [12] [13] 


• Pad Configuration: [15] [16] [17] 


• Set Up DSI Protocol Engine: [18] [19] [20] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [21] [22] [23] [24] [25] [26] 








Table 7-384. DSI_COMPLEXIO_IRQSTATUS 


Description INTERRUPT STATUS REGISTER - All errors from complex I/O 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



RESERVED 

RESERVED 

RESERVED 

RESERVED 

ERRCONTENTIONLP1_3_IRQ 






RESERVED 

RESERVED 

STATEULPS3_IRQ 



31 ULPSACTIVENOT_ All the ULPSActiveNOT signals corresponding to the lanes with RW 0x0 

ALL1_IRQ TXULPSExit being high are high. 


RESERVED 



RESERVED 



30 ULPSACTIVENOT_ All signals ULPSActiveNOT are 0 RW 0x0 

ALL0_IRQ 













25 ERRCONTENTIONLP1_ Contention LP1 error for lane #3 RW 0x0 

3_IRQ 






3_IRQ 






2_IRQ 






ERRCONTROL3_IRQ 




RESERVED 

RESERVED 

ERRESC3_IRQ 

ERRESC2_IRQ 

ERRESC1_IRQ 

RESERVED 

RESERVED 









2_IRQ 






1_IRQ 






1_IRQ 









17 STATEULPS3_IRQ Lane #3 in ultralow-power state RW 0x0 



















12 ERRCONTROL3_IRQ Control error for lane #3 RW 0x0 
























7 ERRESC3_IRQ Escape entry error for lane #3 RW 0x0 



















2 ERRSYNCESC3_IRQ Low power Data transmission synchronization error for lane #3 RW 0x0 















Table 7-385. Register Call Summary for Register DSI_COMPLEXIO_IRQSTATUS 


• DSI Interrupt Request: [0] [1] 


• Twakeup Timer: [2] 


• Exiting ULPS: [3] [4] 

• Error Handling: [5] [6] [7] [8] [9] [10] [11] [12] [13] 






• DSI Protocol Engine Registers: [17] 



1909




Table 7-386. DSI_COMPLEXIO_IRQENABLE 


Description INTERRUPT ENABLE REGISTER - All errors from complex I/O 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 



RESERVED 

RESERVED 

RESERVED 

RESERVED 

ERRCONTENTIONLP1_3_IRQ_EN 






RESERVED 

RESERVED 

STATEULPS3_IRQ_EN 



31 ULPSACTIVENOT_ All the ULPSActiveNOT signals corresponding to the lanes RW 0x0 

ALL1_IRQ_EN with TXULPSExit being high are high. 



RESERVED 

RESERVED 

ERRCONTROL3_IRQ_EN 




30 ULPSACTIVENOT_ All signals ULPSActiveNOT are 0 RW 0x0 

ALL0_IRQ_EN 












3_IRQ_EN 




3_IRQ_EN 




2_IRQ_EN 




2_IRQ_EN 




1_IRQ_EN 





RESERVED 

RESERVED 

ERRESC3_IRQ_EN 



RESERVED 

RESERVED 



ERRSYNCESC1_IRQ_EN





1_IRQ_EN 







17 STATEULPS3_IRQ_EN Lane #3 in ultralow-power state RW 0x0 













12 ERRCONTROL3_IRQ_EN Control error for lane #3 RW 0x0 













7 ERRESC3_IRQ_EN Escape entry error for lane #3 RW 0x0 













2 ERRSYNCESC3_IRQ_EN Low power Data transmission synchronization error for lane RW 0x0 

#3 





1911





#2 




#1 



Table 7-387. Register Call Summary for Register DSI_COMPLEXIO_IRQENABLE 







Table 7-388. DSI_CLK_CTRL 


Description CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only 

when IF_EN is reset. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

PLL_PWR_CMD 

PLL_PWR_STATUS 

LP_RX_SYNCHRO_ENABLE 

LP_CLK_ENABLE 

HS_MANUAL_STOP_CTRL 

HS_AUTO_STOP_ENABLE 

LP_CLK_NULL_PACKET_SIZE 

RESERVED LP_CLK_DIVISOR 


31:30 PLL_PWR_CMD Command for power control of the DSI PLL Control RW 0x0 

module 

LP_CLK_NULL_PACKET_ENABLE 

CIO_CLK_ICG 

DDR_CLK_ALWAYS_ON 

0x0: Command to change to OFF state 

0x1: Command to change to ON state for PLL only 

(HSDIVISER is OFF) 

0x2: Command to change to ON state for both PLL and 

HSDIVISER 

0x3: Command to change to ON state for both PLL and 

HSDIVISER (no clock output to the DSI complex I/O) 






29:28 PLL_PWR_STATUS Status of the power control of the DSI PLL Control R 0x0 

module 

0x0: DSI PLL Control module in OFF state 

0x1: DSI PLL Control module in ON state for PLL only 

(HSDIVISER is OFF) 

0x2: DSI PLL Control module in ON state for both PLL 

and HSDIVISER 

0x3: DSI PLL Control module in ON state for both PLL 

and HSDIVISER (no clock output to the DSI complex I/O) 



21 LP_RX_SYNCHRO_ Defines if the DSI functional clock is higher or lower than RW 0x0 

ENABLE 30 MHz. The information is used to define 

synchronization to be used for RxValidEsc. 

0x0: The DSI functional clock is equal or slower than 30 

MHz. The synchronization is falling/rising. 

0x1: The DSI functional clock is higher than 30 MHz. The 

synchronization is rising/rising. 

20 LP_CLK_ENABLE Controls the gating of the TXCLKESC clock. RW 0x0 

0x0: Disabled. The clock is not generated. The value of 

LP_CLK_DIVISOR[12:0] bit field is not used and does not 

have to be programmed. 

0x1: Enabled. The clock is generated. The value of 

LP_CLK_DIVISOR[12:0] bit field is used and must be 

programmed. 

19 HS_MANUAL_STOP_ In case HS_AUTO_STOP_ENABLE bit is set to 0 (reset RW 0x0 

CTRL value), the bit field allows manual control of the 

assertion/de-assertion of the signal DSIStopClk by users. 

0x0: DSIStopClk de-assertion unconditionally. 

0x1: DSIStopClk assertion unconditionally. 

18 HS_AUTO_STOP_ENABLE Enables the automatic assertion/de-assertion of RW 0x0 

DSIStopClk signal. 

0x0: Auto mode disabled. 

0x1: Auto mode enabled. 

17:16 LP_CLK_NULL_PACKET_ Indicates the size of LP NULL Packets to be sent RW 0x0 

SIZE automatically when after the last LP packet transfer. It is 

used by the receiver to drain its internal pipeline. The 

valid values are from 0 to 3 bytes for the payload size. 

15 LP_CLK_NULL_PACKET_ Enables the generation of NULL packet in low speed. RW 0x0 

ENABLE 

0x0: Disabled. The NULL packet is not sent in LP mode 

after the last LP packet. 

0x1: Enabled. The NULL packet is sent in LP mode after 

the last LP packet. 

14 CIO_CLK_ICG Controls the signal for gating the L3_ICLK clock provided RW 0x0 

to the complex I/O 

0x0: Disabled. The L3_ICLK clock to the DSI complex I/O 

is gated. 

0x1: Enabled. The L3_ICLK clock to the DSI complex I/O 

is not gated. 

13 DDR_CLK_ALWAYS_ON Defines if the DDR clock is also sent when there is no HS RW 0x0 

packets sent to the peripheral (low power mode). So 

TXRequest for the clock lane is not de-asserted. 

0x0: Disabled. The DDR clock is only provided when HS 

packets are sent. 

0x1: Enabled. The DDR clock is always sent to the 

peripheral regardless of the state of the data lanes (HS or 

LP mode). 



1913




12:0 LP_CLK_DIVISOR Defines the ratio to be used for the generation of the RW 0x0001 

low-power mode clock from DSI functional clock. 

The supported values are from 1 to 8191(the value 0 is 

invalid). The output frequency must be in the range 

between 20 MHz and 32 kHz. 


• Data/Clock Configuration: [0] [1] 

Table 7-389. Register Call Summary for Register DSI_CLK_CTRL 


• Clock Requirements: [2] [3] [4] [5] 

• Extra LP Transitions: [6] [7] [8] 

• Power Management: [9] 

• DSI PLL Power Control Commands: [10] [11] [12] [13] [14] [15] 


• Entering ULPS: [16] 

• Turn-Around Request in Transmit Mode: [17] 


• Set Up DSI DPLL: [18] [19] [20] 


• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [22] [23] [24] [25] [26] [27] [28] [29] 



• DSI Protocol Engine Registers: [31] [32] 


Table 7-390. DSI_TIMING1 


Description TIMING1 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be 

modified while DSI_CTRL.IF_EN is set to 1. It is used to indicate the number of DSI_FCLK clock cycles 

for the timers FORCE_TX_STOP_TIMER and TA_TO_TIMER 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

TA_TO 

TA_TO_X16 

TA_TO_X8 

FORCE_TX_STOP_MODE_IO 

STOP_STATE_X16_IO 

STOP_STATE_X4_IO 

TA_TO_COUNTER STOP_STATE_COUNTER_IO 


31 TA_TO Enables the turn-around timer RW 0x0 

0x0: Turn-around counter is disabled. 

0x1: Turn-around counter is enabled (required to receive TA 

interrupt in case the turn-around procedure is not successful). 






30 TA_TO_X16 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in TA_TO_COUNTER bit field 

0x0: The number of DSI_FCLK clock cycles defined in 

TA_TO_COUNTER is multiplied by 1x 



29 TA_TO_X8 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in TA_TO_COUNTER bit field 





28:16 TA_TO_COUNTER Turn around counter. It indicates the number of DSI_FCLK clock RW 0x1FFF 

cycles to wait for the change of the Direction PPI signal 

according to the TurnRequest signal 

The value is from 0 to 8191. 

15 FORCE_TX_STOP_ Control of ForceTxStopMode signal RW 0x0 

MODE_IO 

0x0: De-assertion of ForceTxStopMode. The hardware reset the 

bit at the end of the ForceTXStopMode assertion. The SW can 

reset the bit to stop the assertion of the ForceTXStopMode 

signal prior to the completion of the period. 

0x1: Assertion of ForceTxStopMode 

14 STOP_STATE_X16_IO Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in STOP_STATE_COUNTER_IO bit field 


STOP_STATE _COUNTER_IO is multiplied by 1x 



13 STOP_STATE_X4_IO Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in STOP_STATE_COUNTER_IO bit field 





12:0 STOP_STATE_ Stop state counter. It indicates the number of DSI_FCLK clock RW 0x1FFF 

COUNTER_IO cycles to assert ForceTXStopMode signal. The value is from 0 to 

8191. 


• ForceTxStopMode FSM: [0] [1] [2] [3] [4] 

• TurnRequest FSM: [5] [6] [7] [8] [9] 


Table 7-391. Register Call Summary for Register DSI_TIMING1 


• Video Mode Transfer: [11] [12] 

• Command Mode Transfer Example 1: [13] [14] 




• Drive Stop State: [18] [19] 









Table 7-392. DSI_TIMING2 


Description TIMING2 REGISTER This register controls the DSI Protocol Engine module timers. Any bit field can be 

modified while DSI_CTRL.IF_EN is set to 1. It is used to indicate the number of TxByteClkHS clock 

cycles for the timers HS_TX_TIMER and LP_RX_TIMER 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HS_TX_TO 

HS_TX_TO_X16 

HS_TX_TO_X8 

LP_RX_TO 

LP_RX_TO_X16 

HS_TX_TO_COUNTER LP_RX_TO_COUNTER 


31 HS_TX_TO Enables the HS TX timer. RW 0x0 


0x1: Turn-around counter is enabled (required to receive TA interrupt 

in case the turn-around procedure is not successful). 

30 HS_TX_TO_X16 Multiplication factor for the number of TxByteClkHS functional clock RW 0x1 

cycles defined in HS_TX_COUNTER bit field 

0x0: The number of TxByteClkHS functional clock cycles defined in 

HS_TX_TO_COUNTER is multiplied by 1x 



29 HS_TX_TO_X8 Multiplication factor for the number of TxByteClkHS functional clock RW 0x1 

cycles defined in HS_TX_COUNTER bit 





28:16 HS_TX_TO_ HS_TX_TIMER counter. It indicates the number of TxByteClkHS RW 0x1FFF 

COUNTER function clock cycles for the HS TX timer. 


15 LP_RX_TO Enables the LP RX timer. RW 0x0 


0x1: Turn-around counter is enabled (required to receive TA interrupt 

in case the turn-around procedure is not successful). 

14 LP_RX_TO_X16 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in LP_RX_COUNTER bit field 

LP_RX_TO_X4 


LP_RX_TO_COUNTER is multiplied by 1x 



13 LP_RX_TO_X4 Multiplication factor for the number of DSI_FCLK clock cycles RW 0x1 

defined in LP_RX_COUNTER bit 





12:0 LP_RX_TO_ LP_RX_TIMER counter. It indicates the number of DSI_FCLK clock RW 0x1FFF 

COUNTER cycles for the LP RX timer. 







• HS TX Timer: [0] 

• LP RX Timer: [1] [2] [3] [4] [5] 

Table 7-393. Register Call Summary for Register DSI_TIMING2 







Table 7-394. DSI_VM_TIMING1 


Description VIDEO MODE TIMING REGISTER This register defines the video mode timing. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HSA HFP HBP 


31:24 HSA Defines the horizontal Sync active period used in video mode in RW 0x00 

number of byte clock cycles (TxByteClkHS) 

The supported values are from 0 to 255. 

23:12 HFP Defines the horizontal front porch used in video mode in number of RW 0x000 

byte clock cycles (TxByteClkHS) 

The supported values are from 0 to 255 

11:0 HBP Defines the horizontal back porch used in video mode in number of RW 0x000 



Table 7-395. Register Call Summary for Register DSI_VM_TIMING1 


• Video Mode: [0] 










Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

WINDOW_SYNC 

RESERVED VSA VFP VBP 



1917






27:24 WINDOW_SYNC Number of TxByteClkHS clock cycles for the synchronization RW 0x0 

window. An interrupt for synchronization lost is generated when the 

received synchronization on video port is not inside the window. The 

DSI protocol engine does not change its own timings if the synch is 

inside the window. The valid values are from 0 to 15. 

23:16 VSA Defines the vertical Sync active period used in video mode in RW 0x00 

number of lines. 

The supported values are from 0 to 255 It is used to generate the 

short packet for End of Vertical synchronization. 

15:8 VFP Defines the vertical front porch used in video mode in number of RW 0x00 

lines. 


7:0 VBP Defines the vertical back porch used in video mode in number of RW 0x00 

lines. 



• Video Port Used for Video Mode: [0] 



• Video Mode: [1] [2] 









Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

TL VACT 


31:16 TL Defines the number of length of the line in video mode in number of RW 0x0000 


The supported values are from 0 to 8192. The values from 8193 to 

65535 are not supported. 

15:0 VACT Defines the number of active lines used in video mode. RW 0x0000 
















Table 7-400. DSI_CLK_TIMING 


Description CLOCK TIMING REGISTER This register controls the DSI Protocol Engine module timers. This register 

should not be modified while DSI_CTRL.IF_EN is set to 1. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED DDR_CLK_PRE DDR_CLK_POST 




15:8 DDR_CLK_PRE Indicates the number of TxByteClkHS cycles between the start of the RW 0x01 

DDR clock and the assertion of the data request signal. The values 

from 1 to 255 are valid. The value 0 is reserved. The value is not 

used if DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON is set to 1 

since the DDR clock is always present. 

7:0 DDR_CLK_POST Indicates the number of TxByteClkHS cycles after the de-assertion of RW 0x01 

the data request signal and the stop of the DDR clock. The values 

from 1 to 255 are valid. The value 0 is reserved. The value is not 

used if DSI_CLK_CTRL[13] DDR_CLK_ALWAYS_ON is set to 1 

since the DDR clock is always present. 

Table 7-401. Register Call Summary for Register DSI_CLK_TIMING 


• Timing Parameters for an LP to HS Transaction: [0] [1] 

• Timing Parameters for an HS to LP Transaction: [2] [3] 







Table 7-402. DSI_TX_FIFO_VC_SIZE 


Description Defines the corresponding memory entries allocated for each VC. The VC must be disabled to 

allocate/un-allocate some entries in the TX FIFO. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VC3_FIFO_SIZE 

RESERVED 

VC3_FIFO_ADD 

VC2_FIFO_SIZE 

RESERVED 

VC2_FIFO_ADD 


31:28 VC3_FIFO_SIZE Size of the FIFO allocated for VC 3. For a complete description, RW 0x0 

refer to Table 7-68. 




VC1_FIFO_SIZE 

RESERVED 


VC1_FIFO_ADD 

VC0_FIFO_SIZE 

RESERVED 

VC0_FIFO_ADD 

1919




26:24 VC3_FIFO_ADD Address of the space allocated in the FIFO for VC 3. For a RW 0x0 

complete description, refer to Table 7-69. 











10:8 VC1_FIFO_ADD Address of the space allocated in the FIFO for VC 1.For a RW 0x0 








Table 7-403. Register Call Summary for Register DSI_TX_FIFO_VC_SIZE 


• Command Mode TX FIFO: [0] [1] [2] [3] [4] 






Table 7-404. DSI_RX_FIFO_VC_SIZE 


Description Defines the corresponding memory entries allocated for each VC and the addresses. The VC must be 

disabled to allocate/un-allocate some entries in the RX FIFO. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VC3_FIFO_SIZE 

RESERVED 

VC3_FIFO_ADD 

VC2_FIFO_SIZE 

RESERVED 

VC2_FIFO_ADD 






26:24 VC3_FIFO_ADD Address of the space allocated in the FIFO for VC 3.For a RW 0x0 







VC1_FIFO_SIZE 

RESERVED 


VC1_FIFO_ADD 

VC0_FIFO_SIZE 

RESERVED 

VC0_FIFO_ADD


















Table 7-405. Register Call Summary for Register DSI_RX_FIFO_VC_SIZE 


• Command Mode RX FIFO: [0] [1] [2] 






Table 7-406. DSI_COMPLEXIO_CFG2 


Description COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane 

configuration for the ULPS for each lane. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 


LP_BUSY 

HS_BUSY 




17 LP_BUSY Indicates when there are still pending operations for VCs configured for R 0x0 

LP mode. Forced to 1 when at least one VC is enabled and configured for 

LP mode. 

Read 0x0: LP logic is idle 

Read 0x1: LP logic is active 

16 HS_BUSY Indicates when there are still pending operations for VCs configured for R 0x0 

HS mode. Forced to 1 when at least one VC is enabled and configured 

for HS mode 

Read 0x0: HS logic is idle 

Read 0x1: HS logic is active 





RESERVED 

RESERVED 

LANE3_ULPS_SIG2 



RESERVED 

RESERVED 




1921








7 LANE3_ULPS_ Enables the ULPS for the lane #3. The HW should change the state of RW 0x0 

SIG2 the lane to ULPS only when it is in stop state and there is no data 

pending inside the DSI protocol engine and the DSI protocol engine has 

control of the bus (BTA has not been sent). 

The state of the signal TxRequestEsc is change if lane #3 is a data lane. 

The state of the signal TxUlpsClk is change if lane #3 is a clock lane. 

There will be a latency depending on the frequency of TxClkExc. This bit 

should be read back to confirm a write has been effective. 

0x0: READ: Inactive state effective 

WRITE: Request to change to inactive state 

0x1: READ: Active state effective 

WRITE: Change request to active. If the lane is a data lane, 

TxRequestEsc is asserted and synchronously TxUlpsEsc is asserted for 

one period of TxClkEsc. 











0x1: READ: ACTIVE state effective 


























The state of the signal TxULPSExit is changed if lane #3 is a clock lane. 

There will be a latency depending on the frequency of TxClkExc. 

This bit should be read back to confirm a write has been effective. 












1 LANE2_ULPS_ Enables the ULPS for the lane #2. The HW must change the state of the RW 0x0 

SIG1 lane to ULPS only when it is in stop state and there is no data pending 

inside the DSI protocol engine and the DSI protocol engine has control of 

the bus (BTA has not been sent). 










0 LANE1_ULPS_ Enables the ULPS for the lane #1. The HW must change the state of the RW 0x0 

SIG1 lane to ULPS only when it is in stop state and there is no data pending 

inside the DSI protocol engine and the DSI protocol engine has control of 

the bus (BTA has not been sent). 





• ULPS: [0] 







Table 7-407. Register Call Summary for Register DSI_COMPLEXIO_CFG2 


• Ultra-Low Power State: [1] 

• Entering ULPS: [2] [3] [4] [5] [6] [7] [8] [9] 

• Exiting ULPS: [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] 



Address Offset 0x0000 007C 

Table 7-408. DSI_RX_FIFO_VC_FULLNESS 


Description Defines the fullness of each space allocated for each VC. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VC3_FIFO_FULLNESS VC2_FIFO_FULLNESS VC1_FIFO_FULLNESS VC0_FIFO_FULLNESS 


31:24 VC3_FIFO_FULLNESS Fullness of the FIFO allocated for VC 3.The valid values are R 0x00 

from 0 to 127 corresponding to 1x33-bit,...up to 128x33-bit. 









1923



Table 7-409. Register Call Summary for Register DSI_RX_FIFO_VC_FULLNESS 


• Command Mode DMA Requests: [0] 







Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED HSA_HS_INTERLEAVING HFP_HS_INTERLEAVING HBP_HS_INTERLEAVING 




23:16 HSA_HS_INTERLEAVING Defines the number of TxByteClkHS cycles that can be used RW 0x00 

for interleaving high-speed command mode packet into Video 

Mode stream during HSA blanking period. 


15:8 HFP_HS_INTERLEAVING Defines the number of TxByteClkHS cycles that can be used RW 0x00 


Mode stream during HFP blanking period. 


7:0 HBP_HS_INTERLEAVING Defines the number of TxByteClkHS cycles that can be used RW 0x00 


Mode stream during HBP blanking period. 



• Interleaving Mode: [0] [1] [2] 







Table 7-412. DSI_TX_FIFO_VC_EMPTINESS 


Description Defines the emptiness of each space allocated for each VC. 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

VC3_FIFO_EMPTINESS VC2_FIFO_EMPTINESS VC1_FIFO_EMPTINESS VC0_FIFO_EMPTINESS 






31:24 VC3_FIFO_EMPTINESS Emptiness of the FIFO allocated for VC 3.The valid values R 0x00 

are from 0 to 127 corresponding to 1x33-bit,...up to 

128x33-bit. 



128x33-bit. 



128x33-bit. 



128x33-bit. 

Table 7-413. Register Call Summary for Register DSI_TX_FIFO_VC_EMPTINESS 









Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED HSA_LP_INTERLEAVING HFP_LP_INTERLEAVING HBP_LP_INTERLEAVING 




23:16 HSA_LP_INTERLEAVING Defines the number of bytes for Low Power command RW 0x00 

mode packets that can be sent on PPI link during HSA 

blanking period. 


15:8 HFP_LP_INTERLEAVING Defines the number of bytes for Low Power command RW 0x00 

mode packets that can be sent on PPI link during HFP 



7:0 HBP_LP_INTERLEAVING Defines the number of bytes for Low Power command RW 0x00 

mode packets that can be sent on PPI link during HBP 




• Interleaving Mode: [0] [1] [2] 














Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

BL_HS_INTERLEAVING BL_LP_INTERLEAVING 


31:16 BL_HS_INTERLEAVING Defines the number of TxByteClkHS clock cycles that RW 0x0000 

can be used for interleaving high-speed command mode 

packet into Video Mode stream during blanking periods 

during VSA, VBP, VFP periods inside one video frame 

on PPI link. 


15:0 BL_LP_INTERLEAVING Defines the maximum number of bytes for Low Power RW 0x0000 

command mode packets that can be sent on PPI link 

during blanking periods during VSA, VBP or VFP periods 

inside one video frame on PPI link. 





• Interleaving Mode: [1] [2] 









Description Defines the maximum number of bytes of Low Power command mode packets that can be sent on PPI 

link during blanking periods during VSA, VBP or VFP periods inside one video frame on PPI link. The 

supported values are from 0 to 65535 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

ENTER_HS_MODE_LATENCY EXIT_HS_MODE_LATENCY 


31:16 ENTER_HS_MODE_ Defines the number of TxByteClkHS clock cycles necessary RW 0x0000 

LATENCY for entering to HS mode. It corresponds to the delay in 

number of HS clock cycles from assertion of TxRequestHS 

signal to 1 until assertion of TxReadyHS signal to 1. 

The supported values are from 0 to 65535 . 

15:0 EXIT_HS_MODE_ Defines the number of TxByteClkHS clock cycles necessary RW 0x0000 

LATENCY for exiting from HS mode. It corresponds to the maximum 

delay in number of TxByteClkHS from de-assertion of 

TxRequestHS signal until PPI link is in LP-11 state from which 

a new entrance to HS mode can be initiated which does not 

take more than ENTER_HS_MODE_LATENCY clock cycles. 


















Table 7-420. DSI_STOPCLK_TIMING 


Description Number of functional clock cycles to wait for TxByteClock to stop/start after change in DSIStopClk signal 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED DSI_STOPCLK_LATENCY 


31:8 RESERVED Write 0s for future compatibility. Reads returns 0. R 0x000000 

7:0 DSI_STOPCLK_ Clock gating latency from DSI Protocol engine to TxByteClkHS RW 0x80 

LATENCY 

Table 7-421. Register Call Summary for Register DSI_STOPCLK_TIMING 


• DSI PLL Power Control Commands: [0] [1] 



Table 7-422. DSI_VCn_CTRL 

Address Offset 0x0000 0100+ (n* 0x20) Index n = 0 to 3 

Physical Address 0x4804 FD00+ (n* 0x20) Instance DSI_PROTOCOL_ENGINE 

Description CONTROL REGISTER - Virtual channel This register controls the VC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 

DMA_RX_REQ_NB 

DMA_RX_THRESHOLD 

DMA_TX_REQ_NB 

RX_FIFO_NOT_EMPTY 

DMA_TX_THRESHOLD 

TX_FIFO_FULL 

VC_BUSY 

PP_BUSY 

RESERVED 



MODE_SPEED 

ECC_TX_EN 

CS_TX_EN 

BTA_EN 

TX_FIFO_NOT_EMPTY 

MODE 

BTA_LONG_EN 

BTA_SHORT_EN 

SOURCE 

VC_EN 

1927






29:27 DMA_RX_REQ_NB Selection of the use of the DMA request (associated to RW 0x0 

the RX FIFO) 

0x0: DSI_DMA_REQ0 is selected 




0x4: No DMA req selected 

26:24 DMA_RX_THRESHOLD Defines the threshold value for the DMA request RW 0x0 

(associated to the RX FIFO) 

0x0: 1x 32 bits 

0x1: 2 x 32 bits 

0x2: 4 x 32 bits 

0x3: 8 x 32 bits 

0x4: 16 x 32 bits 

0x5: 32 x 32 bits 

23:21 DMA_TX_REQ_NB Selection of the use of the DMA request (associated to RW 0x0 

the TX FIFO) 





0x4: No DMA req selected 

20 RX_FIFO_NOT_EMPTY FIFO status in command mode. Otherwise, this bit can be R 0x0 

ignored. 

0x0: The RX FIFO is empty (the FIFO does not contain 

any data for the VC) 

0x1: The RX FIFO is not empty (the FIFO contains at 

least one byte for the VC) 

19:17 DMA_TX_THRESHOLD Defines the threshold value for the DMA request RW 0x0 

(associated to the TX FIFO) 

0x0: 1x 32 bits 

0x1: 2 x 32 bits 

0x2: 4 x 32 bits 

0x3: 8 x 32 bits 

0x4: 16 x 32 bits 

0x5: 32 x 32 bits 

16 TX_FIFO_FULL FIFO status in command mode. Otherwise, this bit can be R 0x0 

ignored. 

0x0: The TX FIFO is not full (the FIFO can accept at least 

one more 32-bit value) 

0x1: The TX FIFO is full 

15 VC_BUSY Indicates if previously scheduled activities (packets, BTA) R 0x0 

are still being processed. Forced to 1 by hardware if VC 

is enabled. Software should check this bit is 0 before 

changing channel configuration. 

0x0: No pending operations for this VC 

0x1: Pending operations for this VC 

14 PP_BUSY Line buffer busy status. R 0 

0x0: Software is permitted to write a new header for VP 

command mode traffic. 

0x1: Software is NOT permitted to write a new header for 

VP command mode traffic. 








9 MODE_SPEED Selection of the mode. This bit is ignored by hardware RW 0x0 

when video mode is selected. 

0x0: Low-power mode (CMOS) is used to send short and 


0x1: High speed mode (SLVS) is used to send short and 


8 ECC_TX_EN Enables the ECC generation for the transmit header RW 0x0 

(short and long packets). 

0x0: Disabled 

0x1: Enabled 

7 CS_TX_EN Enables the checksum generation for the transmit RW 0x0 

payload (long packet only). 

0x0: Disabled. The value 0x00 is used. 

0x1: Enabled. The Check-sum value is calculated by HW. 

6 BTA_EN Send the bus turn around to the peripheral. It can be RW 0x0 

used when the automatic mode is enabled 

(BTA_SHORT_EN=1 or/and BTA_LONG_EN=1). In that 

case only one BTA is sent to the peripheral. The manual 

mode allows users to define for which packets, the turn 

around is required for example getting acknowledge from 

the peripheral. 

0x0: READS: BTA generation is completed. It is reset by 

HW when it is completed. 

WRITES: Cancellation of the BTA generation (not 

guarantee since it could already on going, must not be 

used). 

0x1: READS: BTA generation has been requested by 

user (it could be on going but not completed). 

WRITES: Request for BTA generation. 

5 TX_FIFO_NOT_EMPTY FIFO status R 0x0 

0x0: The TX FIFO is empty (the FIFO does not contain 

any data for the VC) 

0x1: The TX FIFO is not empty (the FIFO contains at 

least one byte for the VC) 

4 MODE Selection of the mode RW 0x0 

0x0: Command mode. 

0x1: Video mode. 

3 BTA_LONG_EN Enables the automatic bus turn-around after completion RW 0x0 

of each long packet transmission. 

0x0: Disabled 

0x1: Enabled 

2 BTA_SHORT_EN Enables the automatic bus turn-around after completion RW 0x0 

of each short packet transmission. 

0x0: Disabled 

0x1: Enabled 



1929




1 SOURCE Selection of the source between L4 interconnect slave RW 0x0 

port and video port. This bit is ignored by hardware when 

video mode is selected. 

0x0: All the data are provided by the L4 interconnect 

slave port. Any transfer on the video port is ignored for 

this VC. 

0x1: If MODE=VIDEO_MODE. any data received on the 

video port (pixels and enabled synchronization events 

using DSI_CTRL[17] VP_HSYNC_START, 

DSI_CTRL[18] VP_HSYNC_END, DSI_CTRL[15] 

VP_VSYNC_START, DSI_CTRL[16] VP_VSYNC_END,) 

are sent on the VC (only one VC can be associated with 

the video port, the software must ensure that no more 

than one VC is enabled with the video port as the main 

source for data). If MODE=COMMAND_MODE, the 

VP_STALL signal is used by the protocol engine to 

indicate when new data are required. The 

synchronization signals are not generated by the display 

controller. Regardless of the MODE, no data can be 

provided on the L4 interconnect slave port. 

0 VC_EN Enables the VC. RW 0x0 


• Blanking: [0] [1] [2] [3] 

0x0: Disabled. The VC must be disabled for any register 

change in the DSI_VCn_XXX registers the corresponding 

VC ID. 

0x1: Enabled. No change is allowed to the VC registers 

(except for setting the bit fields/registers: 

DSI_VCn_CTRL[6] BTA_EN, DSI_VCn_TE[15:0] 

TE_SIZE, DSI_VCn_TE[31] TE_START, 

DSI_VCn_LONG_XXX, DSI_VCn_SHORT_XXX, 

DSI_VCn_IRQXXX registers). 

Table 7-423. Register Call Summary for Register DSI_VCn_CTRL 


• Command Mode: [4] [5] [6] 


• TurnRequest FSM: [9] 


• Bus Turnaround: [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] 

• Tearing Effect: [28] [29] [30] 

• ECC Generation: [31] 

• Checksum Generation for Long Packet Payloads: [32] 


• Global Register Controls: [33] 

• Virtual Channels: [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] 

• Packets: [45] [46] 

• Video Mode: [47] [48] [49] [50] [51] [52] [53] 

• Command Mode TX FIFO: [54] [55] [56] [57] [58] 

• Command Mode RX FIFO: [59] 

• Command Mode DMA Requests: [60] [61] [62] [63] [64] [65] 

• DSI Programming Sequence Example: [66] [67] 

• Video Mode Transfer: [68] [69] 

• Command Mode Transfer Example 1: [70] [71] [72] [73] [74] 

• Command Mode Transfer Example 2: [75] [76] [77] [78] [79] 








Table 7-424. DSI_VCn_TE 



Description CONTROL REGISTER - Virtual channel This register controls the tearing effect logic. It defines the size 

of the transfer when TE occurs and enables the automatic TE mode. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

TE_START 

TE_EN 

RESERVED TE_SIZE 


31 TE_START Manual control of the start of the transfer. Users can use the TE RW 0 

interrupt to determine that the TE trigger has been received before 

setting the TE_START bit field. It is not mandatory to use the TE 

interrupt. 

0x0: Indicates the end of the transfer. The bit can be used to cancel 

the transfer if not already started. The FIFO must be flushed by 

software to ensure it contains no remaining data. 

0x1: Starts the transfer of the data. The size is defined in TE_SIZE. 

The bit field is set until the transfer completes. It is reset by hardware 

when the transfer completes. 

30 TE_EN Tearing effect control RW 0 

0x0: Disables the automatic transfer of the data using the TE trigger 

as a synchronization event. The interruption is used to know when 

the TE trigger is received. The hardware resets the bit field when the 

transfer completes(TE_SIZE=0). 

0x1: Enables the automatic transfer of the data using the TE trigger 

as a synchronization event. 



23:0 TE_SIZE Defines the number of bytes (payload data excluding the check-sum) RW 0x000000 

to be sent. Users must perform the write into the 

DSI_VCn_LONG_PACKET_HEADER register before sending data 

from the DSI_VCn_LONG_PACKET_PAYLOAD register. The register 

value is decremented for every byte of the DSI link that is sent. At the 

end of the transfer (TE_SIZE = 0), the TE_EN bit field is reset by 

hardware. The DMA_request is asserted when the trigger is received 

in order to receive data in the TX FIFO. It must not be used until all 

data (TE_SIZE) have been received in the FIFO. 

Table 7-425. Register Call Summary for Register DSI_VCn_TE 


• Tearing Effect: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] 






1931



Table 7-426. DSI_VCn_LONG_PACKET_HEADER 



Description LONG PACKET HEADER INFORMATION - virtual channel. This register sets the 32-bit DATA_ID + 

Word count + ECC. The ECC is computed if ECC_TX_EN is set to 1. 

Type W 

DATA_ID is located at bit[7:0]. 

WC is located at bit[23:8]. 

ECC is located at bit[31:24] (least-significant byte first and least significant bit first). 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HEADER 


31:0 HEADER Packet header information: DATA ID + DATA FIELD +ECC W 0x00000000 

Table 7-427. Register Call Summary for Register DSI_VCn_LONG_PACKET_HEADER 


• Video Port Used on Command Mode: [0] [1] 

• Virtual Channel ID - VC Field, DI[7:6]: [2] 



• Command Mode: [4] [5] [6] [7] [8] [9] 

• Bus Turnaround: [10] 

• Tearing Effect: [11] [12] [13] 



• Virtual Channels: [15] 

• Packets: [16] [17] [18] [19] [20] [21] 

• Video Mode: [22] [23] 

• Command Mode TX FIFO: [24] [25] [26] [27] [28] [29] 



• Command Mode Transfer Example 1: [32] [33] [34] 



• Display Subsystem Register Manual: [36] 







Table 7-428. DSI_VCn_LONG_PACKET_PAYLOAD 

Address Offset 0x0000 010C+ (n* 0x20) Index n = 0 to 3 

Physical Address 0x4804 FD0C+ (n* 0x20) Instance DSI_PROTOCOL_ENGINE 

Description LONG PACKET PAYLOAD INFORMATION - virtual channel. This register sets the payload information 

(excluding Check-sum). Hardware must capture the word count in the packet header (in 

DSI_VCn_LONG_PACKET_HEADER register) to determine the last valid data (the VC ID can be 

different from VC). Byte1 is bit[7:0]; Byte2 is bit[15:8]; Byte3 is bit[23:16]; Byte4 is bit[31:24]; and Byten 

is sent before Byten+1 (least-significant byte first and least significant bit first). 

Type W 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

PAYLOAD 


31:0 PAYLOAD Packet payload information (excluding check-sum) W 0x00000000 

Table 7-429. Register Call Summary for Register DSI_VCn_LONG_PACKET_PAYLOAD 


• Command Mode: [0] [1] [2] [3] [4] 


• Tearing Effect: [6] [7] 



• Packets: [9] [10] [11] 

• Command Mode TX FIFO: [12] [13] [14] 






• DSI Protocol Engine Registers: [20] 

Table 7-430. DSI_VCn_SHORT_PACKET_HEADER 



Description SHORT PACKET HEADER INFORMATION - Virtual channel This register sets the 24-bit DATA_ID + 

Short packet data field + ECC (the VC ID can be different than VC) DATA_ID is located at bit[7:0] short 

packet data field is located at bit[23:8] ECC is located at bit[31:24] (least-significant byte first and least 

significant bit first) 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HEADER 


31:0 HEADER WRITES: Packet header information: DATA ID + DATA FIELD +ECC RW 0x00000000 

written into the TX FIFO 

READS: 32-bit values read from the RX FIFO 



1933



Table 7-431. Register Call Summary for Register DSI_VCn_SHORT_PACKET_HEADER 


• Virtual Channel ID - VC Field, DI[7:6]: [0] 


• Command Mode: [1] [2] [3] 




• Virtual Channels: [6] 

• Packets: [7] 

• Command Mode TX FIFO: [8] [9] [10] 







Table 7-432. DSI_VCn_IRQSTATUS 



Description INTERRUPT STATUS REGISTER - Virtual channel This register regroups all the events related to the 

VC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 




8 PP_BUSY_CHANGE_IRQ Video port ping-pong buffer busy status. RW 0 





7 FIFO_TX_UDF_IRQ FIFO underflow status. The FIFO used on the slave port RW 0x0 

for buffering the data received on the OCP slave port for 

the VC has underflowed which means that the data for 

the current packet have not been received in time since 

the transfer of the packet are already started (transfer 

started since the packet size is bigger than space 

allocated in the FIFO). 







PP_BUSY_CHANGE_IRQ 

FIFO_TX_UDF_IRQ 


BTA_IRQ 

FIFO_RX_OVF_IRQ 

FIFO_TX_OVF_IRQ 

PACKET_SENT_IRQ 

ECC_CORRECTION_IRQ 

CS_IRQ




6 ECC_NO_CORRECTION_IRQ ECC error status (short and long packets). No correction RW 0x0 

of the header because of more than 1-bit error. 





5 BTA_IRQ Virtual channel - BTA status. RW 0x0 





4 FIFO_RX_OVF_IRQ FIFO overflow error status. The FIFO used on the slave RW 0x0 

port for buffering the data received on the DSI link for the 

VC has overflowed. 





3 FIFO_TX_OVF_IRQ FIFO overflow error status. The FIFO used on the slave RW 0x0 

port for buffering the data received on the OCP slave port 

for the VC has overflowed. 





2 PACKET_SENT_IRQ Indicates that a packet has been sent. It is used when RW 0x0 

BTA manual mode is used. 





1 ECC_CORRECTION_IRQ Virtual channel - ECC has been used to do the correction RW 0x0 

of the only 1-bit error status (short and long packet only). 





0 CS_IRQ Virtual channel - Check-Sum mismatch status. RW 0x0 


• DSI Interrupt Request: [0] 





Table 7-433. Register Call Summary for Register DSI_VCn_IRQSTATUS 



• Bus Turnaround: [2] [3] 













Table 7-434. DSI_VCn_IRQENABLE 

Address Offset 0x0000 011C+ (n* 0x20) Index n = 0 to 3 

Physical Address 0x4804 FD1C + (n* 0x20) Instance DSI_PROTOCOL_ENGINE 

Description INTERRUPT ENABLE REGISTER - Virtual channel This register regroups all the events related to VC. 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 




8 PP_BUSY_CHANGE_ Video port ping-pong buffer busy. RW 0 

IRQ_EN 



7 FIFO_TX_UDF_IRQ_EN FIFO underflow enable. The FIFO used on the slave port for RW 0x0 

buffering the data received on the OCP slave port for the VC 

has underflowed which means that the data for the current 

packet have not been received in time since the transfer of 

the packet are already started (transfer started since the 

packet size is bigger than space allocated in the FIFO). 



6 ECC_NO_CORRECTION_ ECC error (short and long packets). No correction of the RW 0x0 

IRQ_EN header because of more than 1-bit error. 



5 BTA_IRQ_EN Virtual channel -Bus turn around reception RW 0x0 



4 FIFO_RX_OVF_IRQ_EN FIFO overflow enable. The FIFO used on the slave port for RW 0x0 

buffering the data received on the DSI link for the VC has 

overflowed. 



3 FIFO_TX_OVF_IRQ_EN FIFO overflow enable. The FIFO used on the slave port for RW 0x0 

buffering the data received on the OCP slave port for the VC 

has overflowed. 



2 PACKET_SENT_IRQ_EN Indicates that a packet has been sent. It is used when BTA RW 0x0 

manual mode is used. 





PP_BUSY_CHANGE_IRQ_EN 

FIFO_TX_UDF_IRQ_EN 


BTA_IRQ_EN 

FIFO_RX_OVF_IRQ_EN 

FIFO_TX_OVF_IRQ_EN 

PACKET_SENT_IRQ_EN 

ECC_CORRECTION_IRQ_EN 

CS_IRQ_EN




1 ECC_CORRECTION_ Virtual channel - ECC has been used to correct the only 1-bit RW 0x0 

IRQ_EN error (short and long packet). 



0 CS_IRQ_EN Virtual channel - Check-Sum of the payload mismatch RW 0x0 

detection 



Table 7-435. Register Call Summary for Register DSI_VCn_IRQENABLE 










7.7.2.6 DSI Complex I/O Registers 

NOTE: Copyright 2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member 

Confidential. 


Table 7-436. DSI_PHY_REGISTER0 

Physical Address 0x4804 FE00 Instance DSI_PHY 

Description Configuration register for HS mode timings 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

REG_THSPREPARE REG_THSPRPR_THSZERO REG_THSTRAIL REG_THSEXIT 


31:24 REG_THSPREPARE REG_THSPREPARE timing parameter in multiples of DDR clock RW 0x1E 

period. DDR clock = CLKIN4DDR/4. 

D-PHY specification: 40 ns + 4*UI ÷ 85 ns + 6*UI. 

UI = Unit Interval, equal to the duration of any HS state on the 

clock lane 

Default value is programmed for 400 MHz. 

23:16 REG_THSPRPR_THSZE REG_THSPRPR_THSZERO timing parameter in multiples of RW 0x48 

RO DDR clock period. DDR clock = CLKIN4DDR/4. 

D-PHY specification: 145 ns + 10*UI 


15:8 REG_THSTRAIL REG_THSTRAIL timing parameter in multiples of DDR clock RW 0x1D 


D-PHY specification: 60 ns + 4*UI 


7:0 REG_THSEXIT REG_THSEXIT timing parameter in multiples of DDR clock RW 0x3A 

period. DDR clock = CLKIN4DDR/4) 



1937




D-PHY specification: 100 ns 


Table 7-437. Register Call Summary for Register DSI_PHY_REGISTER0 


• Timing Parameters for an LP to HS Transaction: [0] [1] [2] [3] 

• Timing Parameters for an HS to LP Transaction: [4] [5] [6] [7] 

• Shadowing Register: [8] 


• High-Speed Clock Transmission: [9] [10] 

• High-Speed Data Transmission: [11] [12] [13] 


• Configure DSI_PHY: [14] [15] [16] [17] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [18] [19] [20] [21] 


• DSI_PHY Register Mapping Summary: [22] 




Description Configuration register for LP mode and HS mode timings 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

REG_TTAGO 

REG_TTASURE 

REG_TTAGET 

RESERVED 

REG_TLPXBY2 REG_TCLKTRAIL REG_TCLK_ZERO 


31:29 REG_TTAGO TTA-GO timing in terms of number of TXCLKESC clocks RW 0x2 

0x0: 2 cycles 

0x1: 3 cycles 

0x2: 4 cycles 

0x3: 5 cycles 

0x4: 6 cycles 

0x5: 7 cycles 

0x6: 8 cycles 

0x7: 9 cycles 

Default value: 4 cycles 

28:27 REG_TTASURE TTA-SURE timing in terms of number of TXCLKESC clocks RW 0x0 

0x0: 2 cycles 

0x1: 1 cycle 

0x2: 3 cycles 

0x3: 4 cycles 


26:24 REG_TTAGET TTA-GET timing in terms of number of TXCLKESC clocks RW 0x2 

0x0: 3 cycles 






0x1: 4 cycles 

0x2: 5 cycles 

0x3: 6 cycles 

0x4: 7 cycles 

0x5: 8 cycles 

0x6: 9 cycles 

0x7: 10 cycles 


23:21 RESERVED Reserved. R 0x0 

20:16 REG_TLPXBY2 (TLPX)/2 timing parameter in multiples of DDR clock frequency. DDR RW 0x0A 

clock = CLKIN4DDR/4. 

Default value is programmed for 400 MHz 

This is the internal timer value. The value seen on line will have variance 

due to rise/fall mismatch effects. 

Note: TLPX is used to define the length of LP-01 state in HS Start of 

Transmission sequences on clock and data lanes. For all other purposes 

TLPX is defined by the period of TxLPEsc clock. 

15:8 REG_TCLKTRAIL REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency. RW 0x1A 

DDR clock = CLKIN4DDR/4. 

D-PHY specification: 60 ns 


7:0 REG_TCLKZERO REG_TCLKZERO timing parameter in multiples of DDR clock period. DDR RW 0x6A 

clock = CLKIN4DDR/4. 

D-PHY specification: (REG_TCLKPREPARE + REG_TCLKZERO) 300 ns 

Derived specification for REG_TCLKZERO (Min REG_TCLKPREPARE = 

38 ns): REG_TCLKZERO 262 ns 




• Timing Parameters for an LP to HS Transaction: [0] [1] [2] [3] 


• Shadowing Register: [6] 


• High-Speed Clock Transmission: [7] [8] [9] 

• High-Speed Data Transmission: [10] 

• Turn-Around Request in Transmit Mode: [11] 

• Turn-Around Request in Receive Mode: [12] 


• Configure DSI_PHY: [13] [14] [15] [16] 






1939






Description Sync pattern and reserved bits 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

HSSYNCPATTERN 

OVRRDULPMTX 

RESERVED REGULPMTX REG_TCLKPREPARE 


31:24 HSSYNCPATTERN Default : 184 (10111000). MSB (last received bit of sync pattern), RW 0xB8 

LSB (first received bit of sync pattern). 

23:17 RESERVED Reserved. Read returns zero. Write only zero for future R 0x00 

compatibility. 

16 OVRRDULPMTX Global enable of the weak pulldown on the DSI lanes, configured RW 0 

through the REGULPMTX [15:11] bit field: 

1: Enable weak pulldown on the DSI lanes. 

0: Disable weak pulldown on the DSI lanes (default). 

15:11 REGULPMTX Configuration of the weak pulldowns on the DSI lanes. RW 0x00 

For each bit, the following settings are applicable: 

1: Enable weak pulldown on the lane. 

0: Disable weak pulldown on the lane (default). 

Bit [15]: Reserved 

Bit [14]: Reserved 

Bit [13]: DSI lane 2 



10:8 RESERVED Reserved RW 0x0 

7:0 REG_TCLKPREPARE REG_TCLKPREPARE timing parameter in multiples of DDR clock RW 0x1A 


D-PHY specification: 38 ns ÷ 95 ns 






• High-Speed Data Transmission: [2] 


• Configure DSI_PHY: [3] [4] 






RESERVED





Physical Address 0x4804 FE0C Instance DSI_PHY 

Description Transmitted pattern in case of escape mode trigger command transmission 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

REG_TXTRIGGERESC3 REG_TXTRIGGERESC2 REG_TXTRIGGERESC1 REG_TXTRIGGERESC0 


31:24 REG_TXTRIGGERES Transmitted pattern when REG_TXTRIGGERESC3 is asserted (first RW 0x62 

C3 bit transmitted to last bit transmitted) 

Default: 01100010 

23:16 REG_TXTRIGGERES Default: 01011101 RW 0x5D 

C2 

15:8 REG_TXTRIGGERES Default: 00100001 RW 0x21 

C1 

7:0 REG_TXTRIGGERES Default: 10100000 RW 0xA0 

C0 



• PHY Triggers: [0] 

• Reset: [1] 






Description Received pattern for low-power trigger reception 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

REG_RXTRIGGERESC3 REG_RXTRIGGERESC2 REG_RXTRIGGERESC1 REG_RXTRIGGERESC0 


31:24 REG_RXTRIGGERES Received pattern when REG_RXTRIGGERESC3 is asserted (first RW 0x62 

C3 bit transmitted to last bit transmitted) 

Default: 01100010 

23:16 REG_RXTRIGGERES Default: 01011101 RW 0x5D 

C2 

15:8 REG_RXTRIGGERES Default: 00100001 RW 0x21 

C1 

7:0 REG_RXTRIGGERES Default: 10100000 RW 0xA0 

C0 



• PHY Triggers: [0] 







Table 7-445. Register Call Summary for Register DSI_PHY_REGISTER4 (continued) 






Description Reset done bits 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESETDONETXBYTECLK 

RESETDONESCPCLK 

RESETDONEPWRCLK 

RESERVED 

RESETDONETXCLKESC2 



RESERVED 


31 RESETDONETXBYT RESETDONETXBYTECLK R 0 

ECLK 

0x0: No reset 

0x1: Reset done for the TXBYTECLK domain 

30 RESETDONESCPCL RESETDONESCPCLK R 0 

K 

0x0: No reset 

0x1: Reset done for the SCP clock domain 

29 RESETDONEPWRCL RESETDONEPWRCLK R 0 

K 

0x0: No reset 

0x1: Reset done for the PWR clock domain 

28:27 RESERVED Read-only register. Read returns 0. R 0 

26 RESETDONETXCLK RESETDONETXCLKESC2 R 0 

ESC2 

0x0: No reset 

0x1: Reset done for the TXCLKESC domain for lane 2 


ESC1 

0x0: No reset 



ESC0 

0x0: No reset 


23:0 RESERVED Read-only register. Read returns 0. R 0x000000 







• Reset-Done Bits: [0] [1] [2] [3] [4] [5] [6] 



7.7.2.7 DSI PLL Control Module Registers 


Table 7-448. DSI_PLL_CONTROL 

Physical Address 0x4804 FF00 Instance DSI_PLL_CTRL 

Description This register controls the PLL reset/power and modes 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


31:5 RESERVED Reserved. Write only zero for future compatibility. Reads return R 0x0000000 

zero. 

4 DSI_HSDIV_SYSRESET Force HSDIVIDER SYSRESET RW 0x0 

0x0: HSDIVIDER SYSRESET controlled by power FSM 

0x1: HSDIVIDER SYSRESET forced active 

3 DSI_PLL_SYSRESET Force ADPLLM SYSRESET RW 0x0 

0x0: PLL SYSRESET controlled by power FSM 

0x1: PLL SYSRESET forced active 

2 DSI_PLL_HALTMODE Allow PLL to be halted if no activity RW 0x0 

0x0: PLL will not be halted 

0x1: PLL will be halted based on activity 

1 DSI_PLL_GATEMODE Allow PLL clock gating for power saving RW 0x0 

0x0: CLKIN4DDR on 

0x1: CLKIN4DDR gated by DSI Protocol Engine activity 

0 DSI_PLL_AUTOMODE Automatic update mode. RW 0x0 

If this bit is set then the configuration updates will be 

synchronized to DISPC_UPDATE_SYNC. 

If this bit is clear configuration updates will be done immediately. 

0x0: Manual mode 

0x1: Automatic mode 

Table 7-449. Register Call Summary for Register DSI_PLL_CONTROL 




• DSI PLL Go Sequence: [2] [3] [4] [5] 



DSI_HSDIV_SYSRESET 

DSI_PLL_SYSRESET 

DSI_PLL_HALTMODE 

DSI_PLL_GATEMODE 

DSI_PLL_AUTOMODE



Table 7-449. Register Call Summary for Register DSI_PLL_CONTROL (continued) 


• Set Up DSI DPLL: [6] 



• DSI PLL Controller Register Mapping Summary: [8] 


Table 7-450. DSI_PLL_STATUS 


Description This register contains the status information 

Type R 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


31:10 RESERVED Reserved. Reads return zero. R 0x000000 

9 DSI_BYPASSACKZ State of bypass mode on PHY and HSDIVIDER R 0x0 

0x0: DSI_PHY and HSDIVIDER have switched to using the bypass 

clocks. 

0x1: PLL outputs are still being used by DSI_PHY or HSDIVIDER 

8 DSIPROTO_ Acknowledge for enable of DSI Protocol Engine clock R 0x0 

CLOCK_ACK Verify the status before selecting this source in the DSI Protocol 

Engine clock mux 

0x0: DSI Protocol Engine clock inactive 

0x1: DSI Protocol Engine clock active 

7 DSS_CLOCK_ACK Acknowledge for enable of DSS clock R 0x0 

Verify the status before selecting this source in the DSS clock 

multiplexer 

0x0: DSS clock inactive 

0x1: DSS clock active 

6 DSI_PLL_BYPASS DSI PLL Bypass status R 0x0 

0x0: PLL not bypassing 

0x1: PLL bypass 

5 DSI_PLL_HIGHJITTER DSI PLL High Jitter status R 0x0 

0x0: PLL in normal jitter condition 

0x1: PLL in high jitter condition: Phase error 24% 

(TIGHTPHASELOCK = 0) Phase error 12% 

(TIGHTPHASELOCK = 1) 

4 DSI_PLL_LIMP DSI PLL Limp status R 0x0 

0x0: LIMP mode inactive 

0x1: LIMP mode active 



DSI_BYPASSACKZ 

DSIPROTO_CLOCK_ACK 

DSS_CLOCK_ACK 

DSI_PLL_BYPASS 

DSI_PLL_HIGHJITTER 

DSI_PLL_LIMP 

DSI_PLL_LOSSREF 

DSI_PLL_RECAL 

DSI_PLL_LOCK 

DSI_PLLCTRL_RESET_DONE




3 DSI_PLL_LOSSREF DSI PLL Reference Loss status R 0x0 

0x0: Reference input active 

0x1: Reference input inactive 

2 DSI_PLL_RECAL DSI PLL re-calibration status R 0x0 

If this bit is active, the PLL must be recalibrated 

0x0: Recalibration is not required 

0x1: Recalibration is required 

1 DSI_PLL_LOCK DSI PLL Lock status R 0x0 

See the programming guide for the use of this bit 

0x0: PLL is not locked 

0x1: PLL is locked 

0 DSI_PLLCTRL_ DSI PLL Controller reset done status R 0x0 

RESET_DONE 

0x0: Reset is in progress 

0x1: Reset has completed 

Table 7-451. Register Call Summary for Register DSI_PLL_STATUS 


• Error Handling: [0] [1] 



• DSI PLL Clock Gating Sequence: [3] 

• DSI PLL Error Handling: [4] [5] [6] [7] 







Table 7-452. DSI_PLL_GO 


Description This register contains the GO bit 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

RESERVED 


31:1 RESERVED Reserved. Write only zero for future compatibility. Reads R 0x00000000 

return zero. 

0 DSI_PLL_GO Request (re-)locking sequence of the PLL. RW 0x0 

If the AutoMode bit is set, then this will be deferred until 

DISPC_UPDATE_SYNC goes active 

0x0: No pending action 

0x1: Request PLL (re-)locking/locking pending 



DSI_PLL_GO 

1945




• DSI PLL Go Sequence: [0] [1] 

• DSI PLL Clock Gating Sequence: [2] [3] 

• DSI PLL Recommended Values: [4] 

Table 7-453. Register Call Summary for Register DSI_PLL_GO 


• Set Up DSI DPLL: [5] [6] [7] [8] [9] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [10] [11] [12] [13] [14] 



• DSI PLL Control Module Registers: [16] 


Table 7-454. DSI_PLL_CONFIGURATION1 

Physical Address 0x4804 FF0C Instance DSI_PLL_CTRL 

Description This register contains the latched PLL and HSDIVDER configuration bits 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

DSIPROTO_CLOCK_DIV 

DSS_CLOCK_DIV 

RESERVED DSI_PLL_REGM DSI_PLL_REGN 


31:27 RESERVED Reserved. Write only zero for future compatibility. R 0x00 

Reads return zero. 

26:23 DSIPROTO_CLOCK_DIV Divider value for DSI Protocol Engine clock source RW 0x0 

REGM4 

22:19 DSS_CLOCK_DIV Divider value for DSS clock source RW 0x0 

REGM3 

18:8 DSI_PLL_REGM M Divider for PLL RW 0x000 

7:1 DSI_PLL_REGN N Divider for PLL (Reference) RW 0x00 

0 DSI_PLL_STOPMODE DSI PLL STOPMODE RW 0x0 

0x0: STOPMODE is not selected 

0x1: STOPMODE is selected 

Table 7-455. Register Call Summary for Register DSI_PLL_CONFIGURATION1 


• DSI PLL Operations: [0] [1] [2] 


• DSI PLL Lock Sequence: [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] 

• DSI PLL Recommended Values: [15] 


• Set Up DSI DPLL: [16] [17] [18] [19] [20] 

• Configure DSI Protocol Engine, DSI PLL, and Complex I/O: [21] [22] [23] [24] [25] 





DSI_PLL_STOPMODE




Table 7-456. DSI_PLL_CONFIGURATION2 


Description This register contains the unlatched PLL and HSDIVDER configuration bits These bits are "shadowed" 

when automatic mode is selected 

Type RW 

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

DSI_HSDIVBYPASS 

DSI_PROTO_CLOCK_PWDN 

DSI_PROTO_CLOCK_EN 

DSS_CLOCK_PWDN 

DSS_CLOCK_EN 

DSI_BYPASSEN 

DSI_PHY_CLKINEN 



31:21 RESERVED Reserved. Write only zero for future compatibility. Reads return R 0x000 

zero. 

20 DSI_HSDIVBYPASS Forces HSDIVIDER to bypass mode RW 0x0 

0x0: HSDIVIDER in normal operation. Bypass controlled by PLL. 

DSI_PLL_REFEN 

0x1: HSDIVIDER forced to bypass mode. 

19 DSI_PROTO_CLOCK_ Power down for DSI Protocol Engine clock source RW 0x0 

PWDN 

0x0: DSI Protocol Engine clock divider is active 

DSI_PLL_HIGHFREQ 

DSI_PLL_CLKSEL 

0x1: DSI Protocol Engine clock divider is powered-down 

18 DSI_PROTO_CLOCK_ Enable for DSI Protocol Engine clock source RW 0x0 

EN 

0x0: DSI Protocol Engine clock divider is disabled 

0x1: DSI Protocol Engine clock divider is enabled 

17 DSS_CLOCK_PWDN Power down for DSS clock source RW 0x0 

0x0: DSS clock divider is active 

0x1: DSS clock divider is powered-down 

16 DSS_CLOCK_EN Enable for DSS clock source RW 0x0 

0x0: DSS clock divider is disabled 

0x1: DSS clock divider is enabled 

15 DSI_BYPASSEN Selects DSS functional clock as CLKIN4DDR source RW 0x0 

0x0: PLL controls CLKIN4DDR source: PLL DCO if PLL is locked 

DSS functional clock if not locked 

DSI_PLL_LOCKSEL 

0x1: Force DSS functional clock to be used as CLKIN4DDR 

source 

14 DSI_PHY_CLKINEN CLKIN4DDR control RW 0x0 

0x0: CLKIN4DDR is disabled 

0x1: CLKIN4DDR is enabled 

13 DSI_PLL_REFEN PLL reference clock control RW 0x0 

0x0: PLL reference clock disabled 

0x1: PLL reference clock enabled 

12 DSI_PLL_HIGHFREQ Enables a division of pixel clock by 2 before input to the PLL RW 0x0 

Required for pixel clock frequencies above 32 MHz (21 MHZ if N 

= 0) 

0x0: Pixel clock is not divided 

0x1: Pixel clock is divided by 2 



DSI_PLL_DRIFTGUARDEN 

DSI_PLL_TIGHTPHASELOCK 

DSI_PLL_LOWCURRSTBY 

DSI_PLL_PLLLPMODE 

DSI_PLL_IDLE 

1947




11 DSI_PLL_CLKSEL Reference clock selection RW 0x0 

0x0: Selects DSS2_ALWON_FCLK as PLL reference clock 

0x1: Selects Pixel Clock (PCLKFREE) as PLL reference clock 

10:9 DSI_PLL_LOCKSEL Selects the lock criteria for the PLL RW 0x0 

0x0: Phase Lock criteria depends on setting of 

DSI_PLL_TIGHTPHASELOCK bit 

0x1: Frequency lock 

0x2: Spare 

8 DSI_PLL_ DSI PLL DRIFTGUARDEN RW 0x0 

DRIFTGUARDEN 

0x0: Only RECAL flag is asserted in case of temperature drift. 

The programmer should take appropriate action. 

0x1: Temperature drift will initiate automatic recalibration. RECAL 

flag will be asserted while this is taking place. 

7 DSI_PLL_ DSI PLL Phase Lock criteria RW 0x0 

TIGHTPHASELOCK If this bit is set, the phase lock tolerance is reduced 

0x0: Normal phase lock criteria Phase error lower than 6.4 % 

0x1: Tightened phase lock criteria Phase error lower than 3.2 % 

6 DSI_PLL_ PLL LOW CURRENT STANDBY RW 0x0 

LOWCURRSTBY 

0x0: LOWCURRSTBY is not selected 

0x1: LOWCURRSTBY is selected 

5 DSI_PLL_ Select the power/performance of the PLL RW 0x0 

PLLLPMODE 

0x0: Full performance, minimized jitter 

0x1: Reduced power, increased jitter 

4:1 RESERVED Reserved R 0x0 

0 DSI_PLL_IDLE DSI PLL IDLE: RW 0x0 

0x0: IDLE is not selected 

0x1: IDLE is selected 

Table 7-457. Register Call Summary for Register DSI_PLL_CONFIGURATION2 


• Clocks: [0] [1] 


• DSI PLL Controller Architecture: [2] [3] 

• DSI PLL Operations: [4] [5] [6] 


• DSI PLL Go Sequence: [7] [8] [9] 

• DSI PLL Lock Sequence: [10] [11] [12] [13]

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