Chapter 02 Memory Mapping.pdf

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This chapter describes memory mapping in the device.
Chapter 2
SPRUGN4L–May 2010–Revised June 2011
Memory Mapping
NOTE: This chapter gives information about all modules and features in the high-tier device. To
check availability of modules and features, see Section 1.5, AM/DM37x Family and your
device-specific data manual. In unavailable modules and features, the memory area is
reserved, read is undefined, and write can lead to unpredictable behavior.
Topic ........................................................................................................................... Page
2.1 Introduction .................................................................................................... 202
2.2 Global Memory Space Mapping ......................................................................... 204
2.3 L3 and L4 Memory Space Mapping .................................................................... 207
2.4 IVA2.2 Subsystem Memory Space Mapping ........................................................ 216
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Introduction www.ti.com
2.1 Introduction
The microprocessor unit (MPU) has a 32-bit address port, allowing it to handle a 4-GB space divided into
several regions, depending on the target type.
The memory map is composed of a memory space (general-purpose memory controller [GPMC],
synchronous dynamic random-access memory [SDRAM] controller [SDRC], etc.), register space (level 3
[L3] and level 4 [L4] interconnects), and dedicated spaces (image and video accelerator [IVA2.2]
subsystem, graphics accelerator (SGX), etc.), all of which are shared among the initiators (for example,
the MPU subsystem or the IVA2.2 subsystem).
The GPMC and SDRC are dedicated to memory connection. The GPMC is used for NOR/NAND flash and
SRAM memories. The SDRC is used for SDRAM memories, such as regular SDR-SDRAM (single data
rate), regular JEDEC DDR1 memory (double data rate), low-power SDR-SDRAM, and mobile
DDR-SDRAM. For more information, see Chapter 10, Memory Subsystem.
The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip
memories, among all the initiators of the platform. The L4 interconnects control access to the peripherals.
Transfers between initiators and targets across the platform are physically conditioned by the chip
interconnect and can be logically conditioned by firewalls. For more information about the
intercommunication (L3 and L4 interconnects) and protection mechanisms implemented in the device, see
Chapter 9, Interconnect.
Figure 2-1 shows the interconnect of the device and the main modules and subsystems in the platform.
202 Memory Mapping SPRUGN4L–May 2010–Revised June 2011
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OCM
RAM
MPU
subsystem
OCM
ROM
SGX
SMS: SDRAM
memory
scheduler /
rotation
SDRC: SDRAM
memory
controller
Stacked memories
IVA2.2
subsystem
GPMC: generalpurpose
memory
controller
sDMA
External and stacked memories
L4
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www.ti.com Introduction
Figure 2-1. Interconnect Overview
Display
subsystem
L3 interconnect
L4
L4 interconnect (peripheral)
Camera
ISP
UART3, UART4, McBSP2, McBSP3, McBSP4,
WDT3, GPTIMER2, GPTIMER3,
GPTIMER4,GPTIMER5, GPTIMER6,
GPTIMER7, GPTIMER8, GPTIMER9, GPIO2,
GPIO3, GPIO4, GPIO5, GPIO6
External peripherals ports
L4
USB
HS-OTG
USB
HS-HOST
L4
L4
D2D
L4 interconnect (core)
SCM, CM, display SS, sDMA, USB TLL,
HS USB Host, I2C1, I2C2, I2C3, UART1,
UART2, McBSP1, McBSP5, GPTIMER10,
GPTIMER11, Mailbox, McSPI1,
McSPI2, McSPI3, McSPI4,
MMC/SD/SDIO1, MMC/SD/SDIO2,
MMC/SD/SDIO3, HDQ/1-Wire,
ICR, camera ISP, HS USB OTG,
MODEM INTC, MPU INTC
External peripherals ports
L4 interconnect (wake-up)
GPTIMER1, WDT2,
GPIO1, 32KTIMER
DAP
L4 interconnect
(emulation)
Emulation, trace, and
debug modules
L4
memmap-177-001
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2.2 Global Memory Space Mapping
This section provides a global view of the memory mapping and describes the boot, GPMC, SDRC, and
virtual rotated frame buffer (VRFB) memory spaces.
The system memory mapping is flexible, with two levels of granularity for target address space allocation:
• Level 1 (L1): Four quarters are labeled Q0, Q1, Q2, and Q3. Each quarter corresponds to a 1-GB
address space (total address space is 4GB).
• Level 2 (L2): Each quarter is divided into eight blocks of 128MB, with target spaces mapped in the
blocks.
This organization allows all target spaces to be decoded based on the five most-significant bits (MSBs) of
the 32-bit address ([31:27]).
• Boot space
The system has a 1-MB boot space in the on-chip boot ROM or on the GPMC memory space.
When booting from the on-chip ROM with the appropriate external sys_boot5 pin configuration, the
1-MB memory space is redirected to the on-chip boot ROM memory address space [0x4000 0000 –
0x400F FFFF].
When booting from the GPMC with the appropriate external sys_boot5 pin configuration, the memory
space is part of the GPMC memory space.
For more information about sys_boot5 pin configuration, see Chapter 10, Memory Subsystem, and
Chapter 26, Initialization.
• GPMC space
Eight independent GPMC chip-selects (gpmc_ncs0 to gpmc_ncs7) are available in the first quarter
(Q0) of the addressing space to access NOR/NAND flash and SRAM memories. The chip-selects have
a programmable start address and programmable size (16, 32, 64, or 128MB) in a total memory space
of 1GB.
• SDRC space
Two SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available on the third quarter (Q2) of the
addressing space to access SDRAM memories. The chip-selects have a programmable size (64, 128,
256, or 512MB) in a total memory space of 1GB.
The base address of the chip-select 0 (sdrc_ncs0) memory space is always 0x8000 0000. The base
address of the chip-select 1 (sdrc_ncs1) memory space is programmable. The default value after reset
is 0xA000 0000.
• VRFB space
The SDRC-SMS virtual memory space is a different memory space used to access a subset of the
SDRC memory space through the rotation engine (ROT). The virtual address space size is 768MB split
into two parts: The first 256-MB part is in the second quarter (Q1) of the memory; the second 512-MB
part is in the fourth quarter (Q3) of the memory.
For more information about boot, GPMC, SDRC, and VRFB, see Chapter 10, Memory Subsystem.
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-1 describes the global memory space mapping.
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Table 2-1. Global Memory Space Mapping
Quarter Device Name Start Address End Address Size Description
(Hex) (Hex)
Q0 Boot space (1)
1MB
(1GB) GPMC 1GB
or 1GB-1MB
GPMC 0x0000 0000 0x3FFF FFFF 1GB 8/16 Ex (2) /R/W
Q1 On-chip memory 128MB ROM/SRAM address space
(1GB)
0x4000 0000 0x4001 3FFF 80KB Reserved for boot code
Boot ROM Not accessible after boot
internal (1)
0x4001 4000 0x4001 BFFF 32KB 32-bit Ex (2) /R
Reserved 0x4001 C000 0x400F FFFF 912KB Reserved
Reserved 0x4010 0000 0x401F FFFF 1MB Reserved
SRAM internal 0x4020 0000 0x4020 FFFF 64KB 32-bit Ex (2) /RW
Reserved 0x4021 0000 0x4024 FFFF 256KB Reserved
Reserved 0x4025 0000 0x47FF FFFF 128,704KB Reserved
L4 interconnects 128MB All system peripherals
L4-Core 0x4800 0000 0x48FF FFFF 16MB See Table 2-3.
(L4-Wakeup) (3) (0x4830 0000) (0x4833 FFFF) (256KB) See Table 2-4.
L4-Per 0x4900 0000 0x490F FFFF 1MB See Table 2-5.
Reserved 0x4910 0000 0x4FFF FFFF 111MB Reserved
SGX 64MB Graphic accelerator slave
port
SGX 0x5000 0000 0x5000 FFFF 64KB Graphic accelerator slave port
Reserved 0x5001 0000 0x53FF FFFF 65,472KB Reserved
L4 emulation 64MB Emulation
L4-Emu 0x5400 0000 0x547F FFFF 8MB See Table 2-6.
Reserved 0x5480 0000 0x57FF FFFF 56MB Reserved
Reserved 64MB Reserved
Reserved 0x5800 0000 0x5BFF 0FFF 64MB Reserved
IVA2.2 64MB IVA2.2 subsystem
subsystem
IVA2.2 0x5C00 0000 0x5EFF FFFF 48MB IVA2.2 subsystem. See
subsystem Table 2-8.
Reserved 0x5F00 0000 0x5FFF FFFF 16MB Reserved
Reserved 128MB Reserved
Reserved 0x6000 0000 0x67FF FFFF 128MB Reserved
L3 interconnect 128MB Control registers
L3 control 0x6800 0000 0x68FF FFFF 16MB See Table 2-2.
registers
Reserved 0x6900 0000 0x6BFF FFFF 48MB Reserved
SMS registers 0x6C00 0000 0x6CFF FFFF 16MB Configuration registers SMS
address space 2
SDRC registers 0x6D00 0000 0x6DFF FFFF 16MB Configuration registers SMS
address space 3
GPMC registers 0x6E00 0000 0x6EFF FFFF 16MB Configuration registers GPMC
address space 1
Reserved 0x6F00 0000 0x6FFF FFFF 16MB Reserved
SDRC/SMS 256MB SDRC/SMS
(1)
Boot space location depends on the external sys_boot5 pin configuration.
(2)
Executable
(3)
Peripherals connected to the L4-Wakeup interconnect are accessed through the L4-Core interconnect.
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Table 2-1. Global Memory Space Mapping (continued)
Quarter Device Name Start Address End Address Size Description
(Hex) (Hex)
SDRC/SMS 0x7000 0000 0x7FFF FFFF 256MB SDRC-SMS virtual address
virtual space 0
Address space 0
Q2 SDRC/SMS 1GB SDRAM main address space
(1GB) (SMS)
CS0 – SDRAM (4)
CS1 – SDRAM (4)
0x8000 0000 0x9FFF FFFF 512MB SDRC/SMS
0xA000 0000 0xBFFF FFFF 512MB SDRC/SMS
Q3 Reserved 512MB Reserved
(1GB)
Reserved 0xC000 0000 0xDFFF FFFF 512MB Reserved for future use
SDRC/SMS 512MB SDRC/SMS
SDRC/SMS 0xE000 0000 0xFFFF FFFF 512MB SDRC-SMS virtual address
virtual space 1
Address space 1
(4) Chip-select 0 and chip-select 1 spaces are configurable in the 1-GB SDRC/SMS space.
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2.3 L3 and L4 Memory Space Mapping
The memory space system is hierarchical: L1, L2, L3, and L4.
L1 and L2 are memories in the MPU and IVA2.2 subsystems.
The chip-level interconnect, which consists of one L3 and four L4s, enables communication among all
modules and subsystems.
L3 handles many types of data transfers, including data exchange with system on-chip/external memories.
The four L4s handle transfers with peripherals, but are in four distinct power domains: the L4-Core,
L4-Wakeup, L4-Per, and L4-Emu interconnects, which are in the CORE, WKUP, PER, and EMU power
domains, respectively.
For more information about the interconnect, see Chapter 9, Interconnect.
The following sections describe the register mapping of the L3 and L4 interconnects. Software configures
these registers.
2.3.1 L3 Memory Space Mapping
The L3 interconnect control registers are mapped in a 16-MB space and allow the configuration of the L3
interconnect parameters.
The L3 default settings are fully functional and enable all possible functional data paths. However, the
interconnect parameters can be changed to accommodate requirements.
Accesses to the L3 interconnect can be configured on a per-module basis using the internal L3 registers,
which are grouped into five register block types:
• IA: Initiator agent configuration registers
• TA: Target agent configuration registers
• RT: Register target (global) configuration registers
• PM: Protection mechanism (firewalls) configuration registers
• SI: Global sideband signal configuration registers
For more information, see Chapter 9, Interconnect.
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-2 describes the mapping of the L3 interconnect control registers.
Table 2-2. L3 Control Register Mapping
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
L3 RT 0x6800 0000 0x6800 03FF 1 L3 configuration registers
L3 SI 0x6800 0400 0x6800 07FF 1 Sideband signal configuration
Reserved 0x6800 0800 0x6800 13FF 3 Reserved
MPU subsystem IA 0x6800 1400 0x6800 17FF 1 MPU subsystem instruction port agent
configuration
IVA2.2 subsystem IA 0x6800 1800 0x6800 1BFF 1 IVA2.2 subsystem initiator port agent
configuration
SGX subsystem IA 0x6800 1C00 0x6800 1FFF 1 SGX subsystem initiator port agent
configuration
SMS TA 0x6800 2000 0x6800 23FF 1 SMS target port agent configuration
GPMC TA 0x6800 2400 0x6800 27FF 1 GPMC target port agent configuration
OCM RAM TA 0x6800 2800 0x6800 2BFF 1 OCM RAM target port agent
configuration
OCM ROM TA 0x6800 2C00 0x6800 2FFF 1 OCM ROM target port agent
configuration
D2D IA 0x6800 3000 0x6800 33FF 1 Die-to-die (D2D) initiator port agent
configuration
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Table 2-2. L3 Control Register Mapping (continued)
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
D2D TA 0x6800 3400 0x6800 37FF 1 D2D target port agent configuration
Reserved 0x6800 3800 0x6800 3FFF 2 Reserved
HS USB host IA 0x6800 4000 0x6800 43FF 1 HS USB host initiator port agent
configuration
HS USB OTG IA 0x6800 4400 0x6800 47FF 1 HS USB OTG initiator port agent
configuration
Reserved 0x6800 4800 0x6800 4BFF 1 Reserved
sDMA RD IA 0x6800 4C00 0x6800 4FFF 1 System DMA (sDMA) RD initiator port
agent configuration
sDMA WR IA 0x6800 5000 0x6800 53FF 1 sDMA WR initiator port agent
configuration
Display subsystem IA 0x6800 5400 0x6800 57FF 1 Display subsystem initiator port agent
configuration
CAMERA ISP IA 0x6800 5800 0x6800 5BFF 1 Camera ISP initiator port agent
configuration
DAP IA 0x6800 5C00 0x6800 5FFF 1 Debug access port initiator port agent
configuration
IVA2.2 subsystem TA 0x6800 6000 0x6800 63FF 1 IVA2.2 subsystem target port agent
configuration
SGX subsystem TA 0x6800 6400 0x6800 67FF 1 SGX subsystem target port agent
configuration
L4-Core TA 0x6800 6800 0x6800 6BFF 1 L4-Core target port agent configuration
L4-Per TA 0x6800 6C00 0x6800 6FFF 1 L4-Per target port agent configuration
Reserved 0x6800 7000 0x6800 FFFF 36 Reserved
RT PM 0x6801 0000 0x6801 03FF 1 Register target port protection
Reserved 0x6801 0400 0x6801 23FF 8 Reserved
GPMC PM 0x6801 2400 0x6801 27FF 1 GPMC target port protection
OCM RAM PM 0x6801 2800 0x6801 2BFF 1 OCM RAM target port protection
OCM ROM PM 0x6801 2C00 0x6801 2FFF 1 OCM ROM target port protection
D2D PM 0x6801 3000 0x6801 33FF 1 D2D target port protection
Reserved 0x6801 3400 0x6801 3FFF 3 Reserved
IVA2.2 PM 0x6801 4000 0x6801 43FF 1 IVA2.2 subsystem target port protection
Reserved 0x6801 4400 0x68FF FFFF 16,303 Reserved
2.3.2 L4 Memory Space Mapping
The device contains four L4 interconnects: L4-Core, L4-Wakeup, L4-Per, and L4-Emu.
As with the L3 interconnect, the L4 interconnects can be configured to tune the access depending on the
characteristics of each module.
For more information about the L4 interconnect, see Chapter 9, Interconnect.
2.3.2.1 L4-Core Memory Space Mapping
The L4-Core interconnect is a 16-MB space composed of the L4-Core interconnect configuration registers
and the module registers.
Table 2-3 describes the mapping of the registers for the L4-Core interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Core interconnect. All other accesses are internal to the L4-Core interconnect.
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This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-3. L4-Core Memory Space Mapping (1)
Device Name Start Address End Address Size Description
(Hex) (Hex)
L4-Core 0x4800 0000 0x48FF FFFF 16MB
Reserved 0x4800 0000 0x4800 1FFF 8KB Reserved
System control module (SCM) 0x4800 2000 0x4800 2FFF 4KB Module
0x4800 3000 0x4800 3FFF 4KB L4 interconnect
Clock manager 0x4800 4000 0x4800 5FFF 8KB Module region A
• DPLL 0x4800 6000 0x4800 67FF 2KB Module region B
• Clock manager
0x4800 6800 0x4800 6FFF 2KB Reserved
0x4800 7000 0x4800 7FFF 4KB L4 interconnect
Reserved 0x4800 8000 0x4802 3FFF 112KB Reserved
Reserved 0x4802 4000 0x4802 4FFF 4KB Reserved
0x4802 5000 0x4802 5FFF 4KB Reserved
Reserved 0x4802 6000 0x4803 FFFF 104KB Reserved
L4-Core configuration 0x4804 0000 0x4804 07FF 2KB Address/protection (AP)
0x4804 0800 0x4804 0FFF 2KB Initiator port (IP)
0x4804 1000 0x4804 1FFF 4KB Link agent (LA)
Reserved 0x4804 2000 0x4804 FBFF 55KB Reserved
Display subsystem 0x4804 FBFF 0x4804 FFFF 1KB DSI
• DSI 0x4805 0000 0x4805 03FF 1KB Display subsystem top
•
•
•
Display subsystem top
Display controller
Remote frame buffer interface
(RFBI)
0x4805 0400
0x4805 0800
0x4805 0C00
0x4805 07FF
0x4805 0BFF
0x4805 0FFF
1KB
1KB
1KB
Display controller
RFBI
Video encoder
• Video encoder (VENC) 0x4805 1000 0x4805 1FFF 4KB L4 interconnect
Reserved 0x4805 2000 0x4805 5FFF 16KB Reserved
sDMA 0x4805 6000 0x4805 6FFF 4KB Module
0x4805 7000 0x4805 7FFF 4KB L4 interconnect
Reserved 0x4805 8000 0x4805 FFFF 32KB Reserved
I2C3 0x4806 0000 0x4806 0FFF 4KB Module
0x4806 1000 0x4806 1FFF 4KB L4 interconnect
USBTLL 0x4806 2000 0x4806 2FFF 4KB Module
0x4806 3000 0x4806 3FFF 4KB L4 interconnect
HS USB Host 0x4806 4000 0x4806 4FFF 4KB Module
0x4806 5000 0x4806 5FFF 4KB L4 interconnect
Reserved 0x4806 6000 0x4806 9FFF 16KB Reserved
UART1 0x4806 A000 0x4806 AFFF 4KB Module
0x4806 B000 0x4806 BFFF 4KB L4 interconnect
UART2 0x4806 C000 0x4806 CFFF 4KB Module
0x4806 D000 0x4806 DFFF 4KB L4 interconnect
Reserved 0x4806 E000 0x4806 FFFF 8KB Reserved
I2C1 0x4807 0000 0x4807 0FFF 4KB Module
0x4807 1000 0x4807 1FFF 4KB L4 interconnect
I2C2 0x4807 2000 0x4807 2FFF 4KB Module
0x4807 3000 0x4807 3FFF 4KB L4 interconnect
(1) The registers mapped in this range are shadow registers of the first 2-KB region A [0x4800 4000 – 0x4800 47FF]. Region A and region B
share the same port.
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Table 2-3. L4-Core Memory Space Mapping (2) (continued)
Device Name Start Address End Address Size Description
(Hex) (Hex)
McBSP1 0x4807 4000 0x4807 4FFF 4KB Module
(digital baseband data)
0x4807 5000 0x4807 5FFF 4KB L4 interconnect
Reserved 0x4807 6000 0x4808 5FFF 64KB Reserved
GPTIMER10 0x4808 6000 0x4808 6FFF 4KB Module
0x4808 7000 0x4808 7FFF 4KB L4 interconnect
GPTIMER11 0x4808 8000 0x4808 8FFF 4KB Module
0x4808 9000 0x4808 9FFF 4KB L4 interconnect
Reserved 0x4808 A000 0x4808 AFFF 4KB Reserved
0x4808 B000 0x4808 BFFF 4KB Reserved
Reserved 0x4808 C000 0x4809 3FFF 32KB Reserved
Mailbox 0x4809 4000 0x4809 4FFF 4KB Module
0x4809 5000 0x4809 5FFF 4KB L4 interconnect
McBSP5 0x4809 6000 0x4809 6FFF 4KB Module
(MIDI data)
0x4809 7000 0x4809 7FFF 4KB L4 interconnect
McSPI1 0x4809 8000 0x4809 8FFF 4KB Module
0x4809 9000 0x4809 9FFF 4KB L4 interconnect
McSPI2 0x4809 A000 0x4809 AFFF 4KB Module
0x4809 B000 0x4809 BFFF 4KB L4 interconnect
MMC/SD/SDIO1 0x4809 C000 0x4809 CFFF 4KB Module
0x4809 D000 0x4809 DFFF 4KB L4 interconnect
Reserved 0x4809 E000 0x4809 EFFF 4KB Reserved
0x4809 F000 0x4809 FFFF 4KB Reserved
Reserved 0x480A 0000 0x480A AFFF 44KB Reserved
HS USB OTG 0x480A B000 0x480A BFFF 4KB Module
0x480A C000 0x480A CFFF 4KB L4 interconnect
MMC/SD/SDIO3 0x480A D000 0x480A DFFF 4KB Module
0x480A E000 0x480A EFFF 4KB L4 interconnect
Reserved 0x480A F000 0x480A FFFF 4KB Reserved
Reserved 0x480B 0000 0x480B 0FFF 4KB Reserved
0x480B 1000 0x480B 1FFF 4KB Reserved
HDQ /1-Wire ® 0x480B 2000 0x480B 2FFF 4KB Module
0x480B 3000 0x480B 3FFF 4KB L4 interconnect
MMC/SD/SDIO2 0x480B 4000 0x480B 4FFF 4KB Module
0x480B 5000 0x480B 5FFF 4KB L4 interconnect
ICR MPU port 0x480B 6000 0x480B 6FFF 4KB Module
(chassis mode only)
0x480B 7000 0x480B 7FFF 4KB L4 interconnect
McSPI3 0x480B 8000 0x480B 8FFF 4KB Module
0x480B 9000 0x480B 9FFF 4KB L4 interconnect
McSPI4 0x480B A000 0x480B AFFF 4KB Module
0x480B B000 0x480B BFFF 4KB L4 interconnect
Camera ISP 0x480B C000 0x480B FFFF 16KB Camera ISP
0x480C 0000 0x480C 0FFF 4KB L4 interconnect
Reserved 0x480C 1000 0x480C 8FFF 32KB Reserved
SR1 0x480C 9000 0x480C 9FFF 4KB Module
0x480C A000 0x480C AFFF 4KB L4 interconnect
SR2 0x480C B000 0x480C BFFF 4KB Module
0x480C C000 0x480C CFFF 4KB L4 interconnect
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Table 2-3. L4-Core Memory Space Mapping (2) (continued)
Device Name Start Address End Address Size Description
(Hex) (Hex)
ICR modem port 0x480C D000 0x480C DFFF 4KB Module
(chassis mode only)
0x480C E000 0x480C EFFF 4KB L4 interconnect
Reserved 0x480C F000 0x482F FFFF 2208KB Reserved
L4-Wakeup interconnect (region A) 0x4830 0000 0x4830 9FFF 40KB Nonshared device mapping
Control module ID code 0x4830 A000 0x4830 AFFF 4KB See Table 2-4.
0x4830 B000 0x4830 BFFF 4KB L4 interconnect
L4-Wakeup interconnect (Region B) 0x4830 C000 0x4833 FFFF 208KB See Table 2-4.
0x4834 0000 0x4834 0FFF 4KB L4 interconnect
Reserved 0x4834 1000 0x48FF EFFF 13,052KB Reserved
2.3.2.2 L4-Wakeup Memory Space Mapping
The L4-Wakeup interconnect is a 256-KB space composed of the L4-Wakeup interconnect configuration
registers and the module registers.
Table 2-4 describes the mapping of the registers for the L4-Wakeup interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Wakeup interconnect. All other accesses are internal to the L4-Wakeup interconnect.
Table 2-4. L4-Wakeup Memory Space Mapping
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
L4-Wakeup 0x4830 0000 0x4833 FFFF 256
Reserved 0x4830 0000 0x4830 5FFF 24 Reserved
Power and reset manager 0x4830 6000 0x4830 7FFF 8 Module region A
• Power manager 0x4830 8000 0x4830 87FF 2 Module region B (1)
• Reset manager
0x4830 8800 0x4830 8FFF 2 Reserved
0x4830 9000 0x4830 9FFF 4 L4 interconnect
Reserved 0x4830 A000 0x4830 FFFF 24 Reserved
GPIO1 0x4831 0000 0x4831 0FFF 4 Module
0x4831 1000 0x4831 1FFF 4 L4 interconnect
Reserved 0x4831 2000 0x4831 3FFF 8 Reserved
WDT2 0x4831 4000 0x4831 4FFF 4 Module
0x4831 5000 0x4831 5FFF 4 L4 interconnect
Reserved 0x4831 6000 0x4831 7FFF 8 Reserved
GPTIMER1 0x4831 8000 0x4831 8FFF 4 Module
0x4831 9000 0x4831 9FFF 4 L4 interconnect
Reserved 0x4831 A000 0x4831 FFFF 24 Reserved
32KTIMER 0x4832 0000 0x4832 0FFF 4 Module
0x4832 1000 0x4832 1FFF 4 L4 interconnect
Reserved 0x4832 2000 0x4832 7FFF 24 Reseved
L4-Wakeup configuration 0x4832 8000 0x4832 87FF 2 AP
0x4832 8800 0x4832 8FFF 2 IP L4-Core
0x4832 9000 0x4832 9FFF 4 LA
0x4832 A000 0x4832 A7FF 2 IP L4-Emu
(1) The registers mapped in this range are shadow registers of the first 2-KB region A [0x4830 6000 – 0x4830 67FF]. Regions A and B
share the same port.
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Table 2-4. L4-Wakeup Memory Space Mapping (continued)
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
Reserved 0x4832 A800 0x4833 FFFF 86 Reserved
2.3.2.3 L4-Peripheral Memory Space Mapping
The L4-Per interconnect is a 1-MB space composed of the L4-Per interconnect configuration registers and
the module registers.
Table 2-5 describes the mapping of the registers for the L4-Per interconnect.
NOTE: All memory spaces described as modules provide direct access to the module registers
outside the L4-Per interconnect. All other accesses are internal to the L4-Per interconnect.
Table 2-5. L4-Peripheral Memory Space Mapping
Device Name Start Address End Address Size Description
(Hex) (Hex)
L4-Per 0x4900 0000 0x490F FFFF 1MB
L4-Per configuration 0x4900 0000 0x4900 07FF 2KB AP
0x4900 0800 0x4900 0FFF 2KB IP
0x4900 1000 0x4900 1FFF 4KB LA
Reserved 0x4900 2000 0x4901 FFFF 120KB Reserved
UART3 0x4902 0000 0x4902 0FFF 4KB Module
(infrared)
0x4902 1000 0x4902 1FFF 4KB L4 interconnect
McBSP2 0x4902 2000 0x4902 2FFF 4KB Module
(audio for codec)
0x4902 3000 0x4902 3FFF 4KB L4 interconnect
McBSP3 0x4902 4000 0x4902 4FFF 4KB Module
(Bluetooth ® voice data)
0x4902 5000 0x4902 5FFF 4KB L4 interconnect
McBSP4 0x4902 6000 0x4902 6FFF 4KB Module
(digital baseband voice data)
0x4902 7000 0x4902 7FFF 4KB L4 interconnect
McBSP2 (sidetone) 0x4902 8000 0x4902 8FFF 4KB Module
0x4902 9000 0x4902 9FFF 4KB L4 interconnect
McBSP3 (sidetone) 0x4902 A000 0x4902 AFFF 4KB Module
0x4902 B000 0x4902 BFFF 4KB L4 interconnect
Reserved 0x4902 C000 0x4902 FFFF 16KB Reserved
WDT3 0x4903 0000 0x4903 0FFF 4KB Module
0x4903 1000 0x4903 1FFF 4KB L4 interconnect
GPTIMER2 0x4903 2000 0x4903 2FFF 4KB Module
0x4903 3000 0x4903 3FFF 4KB L4 interconnect
GPTIMER3 0x4903 4000 0x4903 4FFF 4KB Module
0x4903 5000 0x4903 5FFF 4KB L4 interconnect
GPTIMER4 0x4903 6000 0x4903 6FFF 4KB Module
0x4903 7000 0x4903 7FFF 4KB L4 interconnect
GPTIMER5 0x4903 8000 0x4903 8FFF 4KB Module
0x4903 9000 0x4903 9FFF 4KB L4 interconnect
GPTIMER6 0x4903 A000 0x4903 AFFF 4KB Module
0x4903 B000 0x4903 BFFF 4KB L4 interconnect
GPTIMER7 0x4903 C000 0x4903 CFFF 4KB Module
0x4903 D000 0x4903 DFFF 4KB L4 interconnect
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Table 2-5. L4-Peripheral Memory Space Mapping (continued)
Device Name Start Address End Address Size Description
(Hex) (Hex)
GPTIMER8 0x4903 E000 0x4903 EFFF 4KB Module
0x4903 F000 0x4903 FFFF 4KB L4 interconnect
GPTIMER9 0x4904 0000 0x4904 0FFF 4KB Module
0x4904 1000 0x4904 1FFF 4KB L4 interconnect
UART4 0x4904 2000 0x4904 2FFF 4KB Module
0x4904 3000 0x4904 3FFF 4KB L4 interconnect
Reserved 0x4904 4000 0x4904 FFFF 48KB Reserved
GPIO2 0x4905 0000 0x4905 0FFF 4KB Module
0x4905 1000 0x4905 1FFF 4KB L4 interconnect
GPIO3 0x4905 2000 0x4905 2FFF 4KB Module
0x4905 3000 0x4905 3FFF 4KB L4 interconnect
GPIO4 0x4905 4000 0x4905 4FFF 4KB Module
0x4905 5000 0x4905 5FFF 4KB L4 interconnect
GPIO5 0x4905 6000 0x4905 6FFF 4KB Module
0x4905 7000 0x4905 7FFF 4KB L4 interconnect
GPIO6 0x4905 8000 0x4905 8FFF 4KB Module
0x4905 9000 0x4905 9FFF 4KB L4 interconnect
Reserved 0x4905 A000 0x490F FFFF 664KB Reserved
2.3.2.4 L4-Emulation Memory Space Mapping
The L4-Emu interconnect is an 8-MB space composed of the L4-Emu interconnect configuration registers
and module registers.
Table 2-6 describes the mapping of the registers for the L4-Emu interconnect.
NOTE: All memory spaces described as modules provide direct access to the module registers
outside the L4-Emu interconnect. All other accesses are internal to the L4-Emu interconnect.
Table 2-6. L4-Emulation Memory Space Mapping
Device Name Start Address End Address Size Description
(Hex) (Hex)
L4-Emu 0x5400 0000 0x547F FFFF 8MB
Reserved 0x5400 0000 0x5400 3FFF 16KB Reserved
Reserved 0x5400 4000 0x5400 5FFF 8KB Reserved
L4-Emu configuration 0x5400 6000 0x5400 67FF 2KB AP
0x5400 6800 0x5400 6FFF 2KB IP L4-Core
0x5400 7000 0x5400 7FFF 4KB LA
0x5400 8000 0x5400 87FF 2KB IP DAP
Reserved 0x5400 8800 0x5400 FFFF 30KB Reserved
MPU emulation 0x5401 0000 0x5401 7FFF 16KB Module
0x5401 8000 0x5401 7FFF 4KB L4 interconnect
TPIU 0x5401 9000 0x5401 9FFF 4KB Module
0x5401 A000 0x5401 AFFF 4KB L4 interconnect
ETB 0x5401 B000 0x5401 BFFF 4KB Module
0x5401 C000 0x5401 CFFF 4KB L4 interconnect
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Table 2-6. L4-Emulation Memory Space Mapping (continued)
Device Name Start Address End Address Size Description
(Hex) (Hex)
DAPCTL 0x5401 D000 0x5401 DFFF 4KB Module
0x5401 E000 0x5401 EFFF 4KB L4 interconnect
SDTI 0x5401 F000 0x5401 FFFF 4KB L4 interconnect
0x5402 0000 0x544F FFFF 4992KB Reserved
0x5450 0000 0x5450 FFFF 4KB SDTI module (configuration)
0x5451 0000 0x545F FFFF 1984KB Reserved
0x5460 0000 0x546F FFFF 1MB SDTI module (window)
Reserved 0x5470 0000 0x5470 5FFF 24KB Reserved
Power and reset manager 0x5470 6000 0x5470 7FFF 8KB Module region A
• Power manager 0x5470 8000 0x5470 87FF 2KB Module region B (2)
• Reset manager
(WKUP domain
0x5470 8800 0x5470 8FFF 2KB Reserved
(1) )
0x5470 9000 0x5470 9FFF 4KB L4 interconnect
Reserved 0x5470 A000 0x5470 FFFF 24KB Reserved
GPIO1 0x5471 0000 0x5471 0FFF 4KB Module
(WKUP domain (1) )
0x5471 1000 0x5471 1FFF 4KB L4 interconnect
Reserved 0x5471 2000 0x5471 3FFF 8KB Reserved
WDT2 0x5471 4000 0x5471 4FFF 4KB Module
(WKUP domain (3) )
0x5471 5000 0x5471 5FFF 4KB L4 interconnect
Reserved 0x5471 6000 0x5471 7FFF 8KB Reserved
GPTIMER1 0x5471 8000 0x5471 8FFF 4KB Module
(WKUP domain (3) )
0x5471 9000 0x5471 9FFF 4KB L4 interconnect
Reserved 0x5471 A000 0x5471 FFFF 24KB Reserved
32KTIMER 0x5472 0000 0x5472 0FFF 4KB Module
(WKUP domain (3) )
0x5472 1000 0x5472 1FFF 4KB L4 interconnect
Reserved 0x5472 2000 0x5472 7FFF 24KB Reserved
L4-Wakeup configuration 0x5472 8000 0x5472 87FF 2KB AP
(WKUP domain (3) )
0x5472 8800 0x5472 8FFF 2KB IP L4-Core
0x5472 9000 0x5472 9FFF 4KB LA
0x5472 A000 0x5472 A7FF 2KB IP L4-Emu
Reserved 0x5472 A800 0x547F FFFF 854KB Reserved
(1) These modules are accessed through the L4-Wakeup interconnect (for emulation only).
(2) The registers mapped in this range are shadow registers of the first 2-KB region A [0x5470 6000 – 0x5470 67FF]. Regions A and B
share the same port.
(3) These modules are accessed through the L4-Wakeup interconnect (for emulation only).
2.3.3 Register Access Restrictions
This section describes all modules and features in the high-tier device. In unavailable modules and
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
Table 2-7 lists the supported data access widths per module.
Table 2-7. Register Access Restrictions
Module Allowed Access (Bits)
MPU subsystem 8/16/32
IVA2.2 subsystem 32
SGX subsystem 32
Camera ISP 8/16/32
Display subsystem 32
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Table 2-7. Register Access Restrictions (continued)
Module Allowed Access (Bits)
GPMC 8/16/32
SMS 8/16/32
SDRC 8/16/32
sDMA 8/16/32
HS USB host 32
USBTLL 32
USB – ULPI and UTMI registers 8
HS USB OTG 32
L3 interconnect 8/16/32
L4-Wakeup interconnect 8/16/32
L4-Core interconnect 8/16/32
Clock manager 32
Power and reset manager 32
System control module 8/16/32
ICR (chassis mode only) 32
32KTIMER 16/32
GPIO 8/16/32
GPTIMER 16/32
WDTIMER 16/32
I2C 8/16
HDQ/1-Wire 32
McBSP 32
Sidetone 8/16/32
McSPI 8/16/32
UART 8/16/32
MMC/SD/SDIO 32
Mailbox 8/16/32
MPU INTC 16/32
MODEM INTC (chassis mode only) 16/32
SR 8/16/32
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2.4 IVA2.2 Subsystem Memory Space Mapping
This section describes the hardware accelerators of IVA2.2. In unavailable modules and features, the
memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
The device includes the high-performance Texas Instruments IVA2.2. For more information, see
Chapter 5, IVA2.2 Subsystem.
This section describes how internal memories and registers of the IVA2.2 are accessed through the L3
interconnect and by the internal initiators of the IVA2.2 (the digital signal processor [DSP] and the
enhanced direct memory access [EDMA]).
Three views of the IVA2.2 subsystem memory space mapping are provided:
• L3 interconnect view: External view (subsystem memories and configuration registers) as seen by the
MPU subsystem and most of the initiators of the platform through the L3 interconnect
• IVA2.2 DSP view: Internal view as seen by the DSP
• IVA2.2 EDMA view: Internal view as seen by the EDMA
NOTE: The IVA2.2 subsystem also contains a local interconnect with its own memory space
mapping that can be accessed only by the DSP and the video accelerator and sequencer in
the IVA2.2 subsystem. For more information about this video accelerator/sequencer local
interconnect and its memory space mapping, see Chapter 5, IVA2.2 Subsystem.
2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy
The IVA2.2 subsystem includes the following memory features:
• L1P (program)
– 32-KB configurable: Memory-mapped (default after reset) or direct-mapped cache—32-byte cache
line
• L1D (data)
– 32-KB configurable: Memory-mapped (default after reset) or 2-way set associative cache—64-byte
cache line
– 48-KB memory-mapped
• L2 (program and data)
– 64-KB configurable: Memory-mapped (default after reset) or 2-way set associative cache—128-byte
cache line
– 32-KB memory-mapped
– 16-KB ROM
The local memories can be used as cache RAMs or memory-mapped RAMs, depending on the
configuration of the different memory controllers in the IVA2.2 subsystem.
Figure 2-2 shows the memory hierarchy of the IVA2.2 subsystem.
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L1P memorymapped
SRAM
L1P cache
allocated
SRAM
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IVA2.2 DSP
L1P RAM L1D RAM
2.4.1.2 IVA2.2 Cache Allocation
Figure 2-2. IVA2.2 Subsystem Memory Hierarchy
L2 RAM
cache
SDRAM
(connected through the
SDRC)
L1D cache
allocated
SRAM
L1D memorymapped
SRAM
memmap-002
After reset, the L1P RAM is used as a 32-KB memory-mapped RAM. The L1P RAM can be programmed
in the C64x+ DSP program memory controller to allocate 0 (default), 4, 8, 16, or 32KB to cache. When
32KB are allocated to cache, there is no more memory-mapped L1P.
After reset, the L1D RAM is used as an 80-KB memory-mapped RAM. The L1D RAM can be programmed
in the C64x+ DSP data memory controller to allocate 0 (default), 4, 8, 16, or 32KB to cache. When 32KB
are allocated to cache, 48KB are still allocated to the memory-mapped L1D.
After reset, L2 is used as a 96-KB memory-mapped RAM. L2 can be programmed to allocate 0 (default),
32, or 64KB to cache. When 64KB are allocated to cache, 32KB are still allocated to memory-mapped L2.
Figure 2-3 is an example of the L1D RAM cache allocation, where 16KB are allocated to cache.
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0x5CF1 8000
0x5CF1 0000
0x5CF0 4000
Configuration at reset
L1D RAM
memory mapped
(32KB)
(programmable)
L1D RAM
memory
mapped
(48KB)
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Figure 2-3. L1D RAM Cache Allocation Example (L3 Interconnect View)
2.4.2 DSP Access to L2 Memories
2.4.2.1 DSP Access to L2 ROM
L1D RAM cache software
reallocation
Configuration after
software programming
L1D RAM cache
allocated (16KB)
L1D RAM memory
mapped
(16KB)
L1D RAM
memory
mapped
(48KB)
The IVA2.2 subsystem contains 16KB of L2 ROM. The L2 ROM provides boot code.
0x5CF1 8000
0x5CF1 4000
0x5CF1 0000
0x5CF0 4000
memmap-003
When the L1P cache is configured to be inactive (default configuration), DSP program fetch accesses to
the L2 ROM are performed directly, and thus suffer the L2 latency.
When the L1P cache is configured to be active, DSP program fetch accesses to L2 ROM are always
serviced by the L1P cache controller, which partly hides the L2 latency.
2.4.2.2 DSP Access to L2 RAM
The IVA2.2 contains 96KB of L2 RAM. The L2 RAM can be configured to allocate up to 64KB to the L2
cache.
When the L1P and L1D caches are configured to be inactive (default configuration), DSP accesses to the
L2 RAM are accomplished directly, and thus suffer the L2 latency.
When the L1P and L1D RAM are configured to be active, DSP program accesses to L2 RAM are always
serviced by the L1P cache controller (if code fetch) or the L1D cache controller (if data access), which
partly hides the L2 latency
2.4.3 DSP and EDMA Access to Memories and Peripherals
The IVA2.2 DSP and EDMA access the memories and peripherals using virtual addressing. This lets the
DSP and EDMA access memories and peripherals in the same contiguous view, even when the memory
is physically segmented. Table 2-9 and Table 2-10 give the address range where the DSP and the EDMA
can access the memories and peripherals, respectively.
The IVA2.2 memory management unit (IVA2.2 iMMU) handles the virtual-to-physical address translation
based on the software configuration (typically under control of the MPU subsystem).
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Virtual addresses of
device memories
and peripherals
Virtual memory
(IVA2.2 memory space mapping)
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Virtual addresses are issued by the initiator to the IVA2.2 iMMU. Using the translation look-aside buffer
(TLB), the MMU translates the initiator virtual addresses into real physical addresses.
Figure 2-4 shows the relationship among physical addresses, virtual addresses, and the IVA2.2 iMMU.
Figure 2-4. IVA2.2 iMMU Address Translation
IVA2.2 iMMU
address translation
Physical memory
(device memory space mapping)
For more information about the MMU, see Chapter 15, Memory Management Units.
2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space
Physical addresses of
device memories
and peripherals
memmap-004
Table 2-8 lists the IVA2.2 subsystem memory space mapping from the perspective of the MPU subsystem
through the L3 interconnect.
Table 2-8. L3 Interconnect View of the IVA2.2 Subsystem Memory Space
Region Name Start Address End Address Size Description
(Hex) (Hex)
Address space 0 0x5C00 0000 0x5CFF FFFF 16MB
Reserved 0x5C00 0000 0x5C7D FFFF 8064KB Reserved
L2 ROM 0x5C7E 0000 0x5C7E 3FFF 16KB IVA2.2 internal memories
Reserved 0x5C7E 4000 0x5C7F 7FFF 80KB Reserved
L2 RAM 0x5C7F 8000 0x5C7F FFFF 32KB IVA2.2 internal memories
L2 RAM (cache) 0x5C80 0000 0x5C80 FFFF 64KB IVA2.2 internal memories
Reserved 0x5C81 0000 0x5CDF FFFF 6080KB Reserved
L1P RAM (cache) 0x5CE0 0000 0x5CE0 7FFF 32KB IVA2.2 internal memories
Reserved 0x5CE0 8000 0x5CF0 3FFF 1008KB Reserved
L1D RAM 0x5CF0 4000 0x5CF0 FFFF 48KB IVA2.2 internal memories
L1D RAM (cache) 0x5CF1 0000 0x5CF1 7FFF 32KB IVA2.2 internal memories
Reserved 0x5CF1 8000 0x5CFF FFFF 928KB Reserved
Address space 1 0x5D00 0000 0x5DFF FFFF 16MB
MMU registers 0x5D00 0000 0x5D00 0FFF 4KB IVA2.2 iMMU
Reserved 0x5D00 1000 0x5DFF FFFF 16,380KB Reserved
Address space 2 0x5E00 0000 0x5EFF FFFF 16MB
Video coprocessor and 0x5E00 0000 0x5E0F FFFF 1MB IVA2.2 video modules
sequencer
Reserved 0x5E10 0000 0x5EFF FFFF 15MB Reserved
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space
Table 2-9 lists the IVA2.2 subsystem memory space mapping internally from the perspective of the DSP.
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Table 2-9. DSP View of the IVA2.2 Subsystem Memory Space
Region Name Start Address End Address Size (KB) Description
(Hex) (Hex)
Reserved 0x0000 0000 0x007D FFFF 8064 Reserved
L2 ROM 0x007E 0000 0x007E 3FFF 16 IVA2.2 internal memories
Reserved 0x007E 4000 0x007F 7FFF 80 Reserved
L2 RAM 0x007F 8000 0x007F FFFF 32 IVA2.2 internal memories
L2 RAM (cache) 0x0080 0000 0x0080 FFFF 64 IVA2.2 internal memories
Reserved 0x0081 0000 0x00DF FFFF 6080 Reserved
L1P RAM (cache) 0x00E0 0000 0x00E0 7FFF 32 IVA2.2 internal memories
Reserved 0x00E0 8000 0x00F0 3FFF 1008 Reserved
L1D RAM 0x00F0 4000 0x00F0 FFFF 48 IVA2.2 internal memories
L1D RAM (cache) 0x00F1 0000 0x00F1 7FFF 32 IVA2.2 internal memories
Reserved 0x00F1 8000 0x017F FFFF 9120 Reserved
C64x+ interrupt selector 0x0180 0000 0x0180 FFFF 64 C64x+ DSP interrupt controller
C64x+ PDC 0x0181 0000 0x0181 0FFF 4 C64x+ DSP power-down
controller
C64x+ protection ID 0x0181 1000 0x0181 1FFF 4 C64x+ DSP protection ID
C64x+ revision ID 0x0181 2000 0x0181 2FFF 4 C64x+ DSP revision ID
Reserved 0x0181 3000 0x0181 FFFF 52 Reserved
C64x+ EMC 0x0182 0000 0x0182 FFFF 64 C64x+ DSP extended memory
controller
Reserved 0x0183 0000 0x0183 FFFF 64 Reserved
C64x+ memory system 0x0184 0000 0x0184 FFFF 64 Memory controller control
registers
Reserved 0x0185 0000 0x01BF FFFF 3776 Reserved
TPCC configuration 0x01C0 0000 0x01C0 FFFF 64 DMA transfer engine control
registers
TPTC0 configuration 0x01C1 0000 0x01C1 03FF 1 DMA transfer scheduler 0 control
registers
TPTC1 configuration 0x01C1 0400 0x01C1 07FF 1 DMA transfer scheduler 1 control
registers
Reserved 0x01C1 0800 0x01C1 FFFF 62 Reserved
SYSC configuration 0x01C2 0000 0x01C2 0FFF 4 SYSC module control registers
WUGEN configuration 0x01C2 1000 0x01C2 1FFF 4 Wake-up generator control
registers
Reserved 0x01C2 2000 0x0FFF FFFF 233,336 Reserved
Reserved 0x1000 0000 0x107D FFFF 8064 Reserved
L2 ROM (1) 0x107E 0000 0x107E 3FFF 16 IVA2.2 internal memories
Reserved 0x107E 4000 0x107F 7FFF 80 Reserved
L2 RAM (1) 0x107F 8000 0x107F FFFF 32 IVA2.2 internal memories
L2 RAM (cache) (1) 0x1080 0000 0x1080 FFFF 64 IVA2.2 internal memories
Reserved 0x1081 0000 0x10DF FFFF 6080 Reserved
L1P RAM (cache) (1) 0x10E0 0000 0x10E0 7FFF 32 IVA2.2 internal memories
Reserved 0x10E0 8000 0x10F0 3FFF 1008 Reserved
L1D RAM (1) 0x10F0 4000 0x10F0 FFFF 48 IVA2.2 internal memories
L1D RAM (cache)2 (1) 0x10F1 0000 0x10F1 7FFF 32 IVA2.2 internal memories
Reserved 0x10F1 8000 0x10FF FFFF 928 Reserved
Memories and peripherals (2)
0x1100 0000 0xFFFF FFFF 3,915,776 Controlled by the IVA2.2 MMU to
access memories and
peripherals external to the IVA2.2
subsystem
(1)
IVA2.2 internal memories are reachable in the [0x007E 0000-0x00F1 7FFF] and [0x107E 0000-0x10F1 7FFF] (aliasing) ranges.
(2)
For more information, see Chapter 5, IVA2.2 Subsystem.
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2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space
Table 2-10 lists the IVA2.2 subsystem memory space mapping from the perspective of the EDMA.
Table 2-10. EDMA View of the IVA2.2 Subsystem Memory Space
Region Name Start Address End Address Size (KB) Description
(Hex) (Hex)
Reserved 0x0000 0000 0x0007 FFFF 512 Reserved
iVLCD CFG 0x0008 0000 0x0008 1FFF 8 Improved variable-length coding
decoding configuration registers
Reserved 0x0008 2000 0x0008 3FFF 8 Reserved
iVLCD IBUF0A 0x0008 4000 0x0008 43FF 1 Improved variable-length coding
decoding buffer
Reserved 0x0008 4400 0x0008 4FFF 3 Reserved
iVLCD IBUF0B 0x0008 5000 0x0008 53FF 1 Improved variable-length coding
decoding buffer
Reserved 0x0008 5400 0x0008 5FFF 3 Reserved
iVLCD IBUF1 0x0008 6000 0x0008 6BFF 3 Improved variable-length coding
decoding buffer
Reserved 0x0008 6C00 0x0008 7FFF 5 Reserved
iVLCD QMEM 0x0008 8000 0x0008 83FF 1 Improved variable-length coding
decoding quantize memory
Reserved 0x0008 8400 0x0008 BFFF 15 Reserved
iVLCD HMEM 0x0008 C000 0x0008 DBFF 7 Improved variable-length coding
decoding huffman memory
Reserved 0x0008 DC00 0x0008 FFFF 9 Reserved
SEQ CFG 0x0009 0000 0x0009 07FF 2 Video sequencer configuration
registers
Reserved 0x0009 0800 0x0009 3FFF 14 Reserved
SEQ DMEM 0x0009 4000 0x0009 4FFF 4 Video sequencer data memory
Reserved 0x0009 5000 0x0009 7FFF 12 Reserved
SEQ IMEM 0x0009 8000 0x0009 9FFF 8 Video sequencer instruction
memory
Reserved 0x0009 A000 0x0009 BFFF 8 Reserved
Video sysc 0x0009 C000 0x0009 CFFF 4 Video system controller
Reserved 0x0009 D000 0x0009 FFFF 12 Reserved
iME CFG 0x000A 0000 0x000A 0FFF 4 Improved motion estimation
configuration registers
iLF CFG 0x000A 1000 0x000A 1FFF 4 Variable-length coding decoding
configuration registers
Reserved 0x000A 2000 0x000F 7FFF 344 Reserved
Local interconnect 0x000F 8000 0x000F BFFF 16 Video accelerator/sequencer
local interconnect
Reserved 0x000F C000 0x000F FFFF 16 Reserved
Reserved 0x0010 0000 0x107D FFFF 269,184 Reserved
L2 ROM 0x107E 0000 0x107E 3FFF 16 IVA2.2 internal memories
Reserved 0x107E 4000 0x107F 7FFF 80 Reserved
L2 RAM 0x107F 8000 0x107F FFFF 32 IVA2.2 internal memories
L2 RAM (cache) 0x1080 0000 0x1080 FFFF 64 IVA2.2 internal memories
Reserved 0x1081 0000 0x10DF FFFF 6080 Reserved
L1P RAM (cache) 0x10E0 0000 0x10E0 7FFF 32 IVA2.2 internal memories
Reserved 0x10E0 8000 0x10F0 3FFF 1008 Reserved
L1D RAM 0x10F0 4000 0x10F0 FFFF 48 IVA2.2 internal memories
L1D RAM (cache) 0x10F1 0000 0x10F1 7FFF 32 IVA2.2 internal memories
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Table 2-10. EDMA View of the IVA2.2 Subsystem Memory Space (continued)
Region Name Start Address End Address Size (KB) Description
(Hex) (Hex)
Reserved 0x10F1 8000 0x10FF FFFF 928 Reserved
Memories and peripherals (1)
(1) For more information, see Chapter 5, IVA2.2 Subsystem.
0x1100 0000 0xFFFF FFFF 3,915,776 Controlled by the IVA2.2 MMU to
access memories and
peripherals external to the IVA2.2
subsystem
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