Chapter 02 Memory Mapping.pdf
Chapter 02 Memory Mapping.pdf
Chapter 02 Memory Mapping.pdf
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0x5CF1 8000<br />
0x5CF1 0000<br />
0x5CF0 4000<br />
Configuration at reset<br />
L1D RAM<br />
memory mapped<br />
(32KB)<br />
(programmable)<br />
L1D RAM<br />
memory<br />
mapped<br />
(48KB)<br />
Public Version<br />
IVA2.2 Subsystem <strong>Memory</strong> Space <strong>Mapping</strong> www.ti.com<br />
Figure 2-3. L1D RAM Cache Allocation Example (L3 Interconnect View)<br />
2.4.2 DSP Access to L2 Memories<br />
2.4.2.1 DSP Access to L2 ROM<br />
L1D RAM cache software<br />
reallocation<br />
Configuration after<br />
software programming<br />
L1D RAM cache<br />
allocated (16KB)<br />
L1D RAM memory<br />
mapped<br />
(16KB)<br />
L1D RAM<br />
memory<br />
mapped<br />
(48KB)<br />
The IVA2.2 subsystem contains 16KB of L2 ROM. The L2 ROM provides boot code.<br />
0x5CF1 8000<br />
0x5CF1 4000<br />
0x5CF1 0000<br />
0x5CF0 4000<br />
memmap-003<br />
When the L1P cache is configured to be inactive (default configuration), DSP program fetch accesses to<br />
the L2 ROM are performed directly, and thus suffer the L2 latency.<br />
When the L1P cache is configured to be active, DSP program fetch accesses to L2 ROM are always<br />
serviced by the L1P cache controller, which partly hides the L2 latency.<br />
2.4.2.2 DSP Access to L2 RAM<br />
The IVA2.2 contains 96KB of L2 RAM. The L2 RAM can be configured to allocate up to 64KB to the L2<br />
cache.<br />
When the L1P and L1D caches are configured to be inactive (default configuration), DSP accesses to the<br />
L2 RAM are accomplished directly, and thus suffer the L2 latency.<br />
When the L1P and L1D RAM are configured to be active, DSP program accesses to L2 RAM are always<br />
serviced by the L1P cache controller (if code fetch) or the L1D cache controller (if data access), which<br />
partly hides the L2 latency<br />
2.4.3 DSP and EDMA Access to Memories and Peripherals<br />
The IVA2.2 DSP and EDMA access the memories and peripherals using virtual addressing. This lets the<br />
DSP and EDMA access memories and peripherals in the same contiguous view, even when the memory<br />
is physically segmented. Table 2-9 and Table 2-10 give the address range where the DSP and the EDMA<br />
can access the memories and peripherals, respectively.<br />
The IVA2.2 memory management unit (IVA2.2 iMMU) handles the virtual-to-physical address translation<br />
based on the software configuration (typically under control of the MPU subsystem).<br />
218 <strong>Memory</strong> <strong>Mapping</strong> SPRUGN4L–May 2010–Revised June 2011<br />
Copyright © 2010–2011, Texas Instruments Incorporated
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