Chapter 02 Memory Mapping.pdf

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L3 and L4 Memory Space Mapping www.ti.com
Table 2-2. L3 Control Register Mapping (continued)
Device Name Start Address End Address Size (KB) Description
(Hex) (Hex)
D2D TA 0x6800 3400 0x6800 37FF 1 D2D target port agent configuration
Reserved 0x6800 3800 0x6800 3FFF 2 Reserved
HS USB host IA 0x6800 4000 0x6800 43FF 1 HS USB host initiator port agent
configuration
HS USB OTG IA 0x6800 4400 0x6800 47FF 1 HS USB OTG initiator port agent
configuration
Reserved 0x6800 4800 0x6800 4BFF 1 Reserved
sDMA RD IA 0x6800 4C00 0x6800 4FFF 1 System DMA (sDMA) RD initiator port
agent configuration
sDMA WR IA 0x6800 5000 0x6800 53FF 1 sDMA WR initiator port agent
configuration
Display subsystem IA 0x6800 5400 0x6800 57FF 1 Display subsystem initiator port agent
configuration
CAMERA ISP IA 0x6800 5800 0x6800 5BFF 1 Camera ISP initiator port agent
configuration
DAP IA 0x6800 5C00 0x6800 5FFF 1 Debug access port initiator port agent
configuration
IVA2.2 subsystem TA 0x6800 6000 0x6800 63FF 1 IVA2.2 subsystem target port agent
configuration
SGX subsystem TA 0x6800 6400 0x6800 67FF 1 SGX subsystem target port agent
configuration
L4-Core TA 0x6800 6800 0x6800 6BFF 1 L4-Core target port agent configuration
L4-Per TA 0x6800 6C00 0x6800 6FFF 1 L4-Per target port agent configuration
Reserved 0x6800 7000 0x6800 FFFF 36 Reserved
RT PM 0x6801 0000 0x6801 03FF 1 Register target port protection
Reserved 0x6801 0400 0x6801 23FF 8 Reserved
GPMC PM 0x6801 2400 0x6801 27FF 1 GPMC target port protection
OCM RAM PM 0x6801 2800 0x6801 2BFF 1 OCM RAM target port protection
OCM ROM PM 0x6801 2C00 0x6801 2FFF 1 OCM ROM target port protection
D2D PM 0x6801 3000 0x6801 33FF 1 D2D target port protection
Reserved 0x6801 3400 0x6801 3FFF 3 Reserved
IVA2.2 PM 0x6801 4000 0x6801 43FF 1 IVA2.2 subsystem target port protection
Reserved 0x6801 4400 0x68FF FFFF 16,303 Reserved
2.3.2 L4 Memory Space Mapping
The device contains four L4 interconnects: L4-Core, L4-Wakeup, L4-Per, and L4-Emu.
As with the L3 interconnect, the L4 interconnects can be configured to tune the access depending on the
characteristics of each module.
For more information about the L4 interconnect, see Chapter 9, Interconnect.
2.3.2.1 L4-Core Memory Space Mapping
The L4-Core interconnect is a 16-MB space composed of the L4-Core interconnect configuration registers
and the module registers.
Table 2-3 describes the mapping of the registers for the L4-Core interconnect.
NOTE: All memory spaces described as modules provide direct access to module registers outside
the L4-Core interconnect. All other accesses are internal to the L4-Core interconnect.
208 Memory Mapping SPRUGN4L–May 2010–Revised June 2011
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