Chapter 02 Memory Mapping.pdf

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Public Version L3 and L4 Memory Space Mapping www.ti.com Table 2-4. L4-Wakeup Memory Space Mapping (continued) Device Name Start Address End Address Size (KB) Description (Hex) (Hex) Reserved 0x4832 A800 0x4833 FFFF 86 Reserved 2.3.2.3 L4-Peripheral Memory Space Mapping The L4-Per interconnect is a 1-MB space composed of the L4-Per interconnect configuration registers and the module registers. Table 2-5 describes the mapping of the registers for the L4-Per interconnect. NOTE: All memory spaces described as modules provide direct access to the module registers outside the L4-Per interconnect. All other accesses are internal to the L4-Per interconnect. Table 2-5. L4-Peripheral Memory Space Mapping Device Name Start Address End Address Size Description (Hex) (Hex) L4-Per 0x4900 0000 0x490F FFFF 1MB L4-Per configuration 0x4900 0000 0x4900 07FF 2KB AP 0x4900 0800 0x4900 0FFF 2KB IP 0x4900 1000 0x4900 1FFF 4KB LA Reserved 0x4900 2000 0x4901 FFFF 120KB Reserved UART3 0x4902 0000 0x4902 0FFF 4KB Module (infrared) 0x4902 1000 0x4902 1FFF 4KB L4 interconnect McBSP2 0x4902 2000 0x4902 2FFF 4KB Module (audio for codec) 0x4902 3000 0x4902 3FFF 4KB L4 interconnect McBSP3 0x4902 4000 0x4902 4FFF 4KB Module (Bluetooth ® voice data) 0x4902 5000 0x4902 5FFF 4KB L4 interconnect McBSP4 0x4902 6000 0x4902 6FFF 4KB Module (digital baseband voice data) 0x4902 7000 0x4902 7FFF 4KB L4 interconnect McBSP2 (sidetone) 0x4902 8000 0x4902 8FFF 4KB Module 0x4902 9000 0x4902 9FFF 4KB L4 interconnect McBSP3 (sidetone) 0x4902 A000 0x4902 AFFF 4KB Module 0x4902 B000 0x4902 BFFF 4KB L4 interconnect Reserved 0x4902 C000 0x4902 FFFF 16KB Reserved WDT3 0x4903 0000 0x4903 0FFF 4KB Module 0x4903 1000 0x4903 1FFF 4KB L4 interconnect GPTIMER2 0x4903 2000 0x4903 2FFF 4KB Module 0x4903 3000 0x4903 3FFF 4KB L4 interconnect GPTIMER3 0x4903 4000 0x4903 4FFF 4KB Module 0x4903 5000 0x4903 5FFF 4KB L4 interconnect GPTIMER4 0x4903 6000 0x4903 6FFF 4KB Module 0x4903 7000 0x4903 7FFF 4KB L4 interconnect GPTIMER5 0x4903 8000 0x4903 8FFF 4KB Module 0x4903 9000 0x4903 9FFF 4KB L4 interconnect GPTIMER6 0x4903 A000 0x4903 AFFF 4KB Module 0x4903 B000 0x4903 BFFF 4KB L4 interconnect GPTIMER7 0x4903 C000 0x4903 CFFF 4KB Module 0x4903 D000 0x4903 DFFF 4KB L4 interconnect 212 Memory Mapping SPRUGN4L–May 2010–Revised June 2011 Copyright © 2010–2011, Texas Instruments Incorporated
Public Version www.ti.com L3 and L4 Memory Space Mapping Table 2-5. L4-Peripheral Memory Space Mapping (continued) Device Name Start Address End Address Size Description (Hex) (Hex) GPTIMER8 0x4903 E000 0x4903 EFFF 4KB Module 0x4903 F000 0x4903 FFFF 4KB L4 interconnect GPTIMER9 0x4904 0000 0x4904 0FFF 4KB Module 0x4904 1000 0x4904 1FFF 4KB L4 interconnect UART4 0x4904 2000 0x4904 2FFF 4KB Module 0x4904 3000 0x4904 3FFF 4KB L4 interconnect Reserved 0x4904 4000 0x4904 FFFF 48KB Reserved GPIO2 0x4905 0000 0x4905 0FFF 4KB Module 0x4905 1000 0x4905 1FFF 4KB L4 interconnect GPIO3 0x4905 2000 0x4905 2FFF 4KB Module 0x4905 3000 0x4905 3FFF 4KB L4 interconnect GPIO4 0x4905 4000 0x4905 4FFF 4KB Module 0x4905 5000 0x4905 5FFF 4KB L4 interconnect GPIO5 0x4905 6000 0x4905 6FFF 4KB Module 0x4905 7000 0x4905 7FFF 4KB L4 interconnect GPIO6 0x4905 8000 0x4905 8FFF 4KB Module 0x4905 9000 0x4905 9FFF 4KB L4 interconnect Reserved 0x4905 A000 0x490F FFFF 664KB Reserved 2.3.2.4 L4-Emulation Memory Space Mapping The L4-Emu interconnect is an 8-MB space composed of the L4-Emu interconnect configuration registers and module registers. Table 2-6 describes the mapping of the registers for the L4-Emu interconnect. NOTE: All memory spaces described as modules provide direct access to the module registers outside the L4-Emu interconnect. All other accesses are internal to the L4-Emu interconnect. Table 2-6. L4-Emulation Memory Space Mapping Device Name Start Address End Address Size Description (Hex) (Hex) L4-Emu 0x5400 0000 0x547F FFFF 8MB Reserved 0x5400 0000 0x5400 3FFF 16KB Reserved Reserved 0x5400 4000 0x5400 5FFF 8KB Reserved L4-Emu configuration 0x5400 6000 0x5400 67FF 2KB AP 0x5400 6800 0x5400 6FFF 2KB IP L4-Core 0x5400 7000 0x5400 7FFF 4KB LA 0x5400 8000 0x5400 87FF 2KB IP DAP Reserved 0x5400 8800 0x5400 FFFF 30KB Reserved MPU emulation 0x5401 0000 0x5401 7FFF 16KB Module 0x5401 8000 0x5401 7FFF 4KB L4 interconnect TPIU 0x5401 9000 0x5401 9FFF 4KB Module 0x5401 A000 0x5401 AFFF 4KB L4 interconnect ETB 0x5401 B000 0x5401 BFFF 4KB Module 0x5401 C000 0x5401 CFFF 4KB L4 interconnect SPRUGN4L–May 2010–Revised June 2011 Memory Mapping Copyright © 2010–2011, Texas Instruments Incorporated 213
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