Chapter 02 Memory Mapping.pdf
Chapter 02 Memory Mapping.pdf
Chapter 02 Memory Mapping.pdf
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Global <strong>Memory</strong> Space <strong>Mapping</strong> www.ti.com<br />
2.2 Global <strong>Memory</strong> Space <strong>Mapping</strong><br />
This section provides a global view of the memory mapping and describes the boot, GPMC, SDRC, and<br />
virtual rotated frame buffer (VRFB) memory spaces.<br />
The system memory mapping is flexible, with two levels of granularity for target address space allocation:<br />
• Level 1 (L1): Four quarters are labeled Q0, Q1, Q2, and Q3. Each quarter corresponds to a 1-GB<br />
address space (total address space is 4GB).<br />
• Level 2 (L2): Each quarter is divided into eight blocks of 128MB, with target spaces mapped in the<br />
blocks.<br />
This organization allows all target spaces to be decoded based on the five most-significant bits (MSBs) of<br />
the 32-bit address ([31:27]).<br />
• Boot space<br />
The system has a 1-MB boot space in the on-chip boot ROM or on the GPMC memory space.<br />
When booting from the on-chip ROM with the appropriate external sys_boot5 pin configuration, the<br />
1-MB memory space is redirected to the on-chip boot ROM memory address space [0x4000 0000 –<br />
0x400F FFFF].<br />
When booting from the GPMC with the appropriate external sys_boot5 pin configuration, the memory<br />
space is part of the GPMC memory space.<br />
For more information about sys_boot5 pin configuration, see <strong>Chapter</strong> 10, <strong>Memory</strong> Subsystem, and<br />
<strong>Chapter</strong> 26, Initialization.<br />
• GPMC space<br />
Eight independent GPMC chip-selects (gpmc_ncs0 to gpmc_ncs7) are available in the first quarter<br />
(Q0) of the addressing space to access NOR/NAND flash and SRAM memories. The chip-selects have<br />
a programmable start address and programmable size (16, 32, 64, or 128MB) in a total memory space<br />
of 1GB.<br />
• SDRC space<br />
Two SDRC chip-selects (sdrc_ncs0 and sdrc_ncs1) are available on the third quarter (Q2) of the<br />
addressing space to access SDRAM memories. The chip-selects have a programmable size (64, 128,<br />
256, or 512MB) in a total memory space of 1GB.<br />
The base address of the chip-select 0 (sdrc_ncs0) memory space is always 0x8000 0000. The base<br />
address of the chip-select 1 (sdrc_ncs1) memory space is programmable. The default value after reset<br />
is 0xA000 0000.<br />
• VRFB space<br />
The SDRC-SMS virtual memory space is a different memory space used to access a subset of the<br />
SDRC memory space through the rotation engine (ROT). The virtual address space size is 768MB split<br />
into two parts: The first 256-MB part is in the second quarter (Q1) of the memory; the second 512-MB<br />
part is in the fourth quarter (Q3) of the memory.<br />
For more information about boot, GPMC, SDRC, and VRFB, see <strong>Chapter</strong> 10, <strong>Memory</strong> Subsystem.<br />
This section describes all modules and features in the high-tier device. In unavailable modules and<br />
features, the memory area is reserved, read is undefined, and write can lead to unpredictable behavior.<br />
Table 2-1 describes the global memory space mapping.<br />
204 <strong>Memory</strong> <strong>Mapping</strong> SPRUGN4L–May 2010–Revised June 2011<br />
Copyright © 2010–2011, Texas Instruments Incorporated