Chapter 02 Memory Mapping.pdf

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IVA2.2 Subsystem Memory Space Mapping www.ti.com
2.4 IVA2.2 Subsystem Memory Space Mapping
This section describes the hardware accelerators of IVA2.2. In unavailable modules and features, the
memory area is reserved, read is undefined, and write can lead to unpredictable behavior.
The device includes the high-performance Texas Instruments IVA2.2. For more information, see
Chapter 5, IVA2.2 Subsystem.
This section describes how internal memories and registers of the IVA2.2 are accessed through the L3
interconnect and by the internal initiators of the IVA2.2 (the digital signal processor [DSP] and the
enhanced direct memory access [EDMA]).
Three views of the IVA2.2 subsystem memory space mapping are provided:
• L3 interconnect view: External view (subsystem memories and configuration registers) as seen by the
MPU subsystem and most of the initiators of the platform through the L3 interconnect
• IVA2.2 DSP view: Internal view as seen by the DSP
• IVA2.2 EDMA view: Internal view as seen by the EDMA
NOTE: The IVA2.2 subsystem also contains a local interconnect with its own memory space
mapping that can be accessed only by the DSP and the video accelerator and sequencer in
the IVA2.2 subsystem. For more information about this video accelerator/sequencer local
interconnect and its memory space mapping, see Chapter 5, IVA2.2 Subsystem.
2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy
The IVA2.2 subsystem includes the following memory features:
• L1P (program)
– 32-KB configurable: Memory-mapped (default after reset) or direct-mapped cache—32-byte cache
line
• L1D (data)
– 32-KB configurable: Memory-mapped (default after reset) or 2-way set associative cache—64-byte
cache line
– 48-KB memory-mapped
• L2 (program and data)
– 64-KB configurable: Memory-mapped (default after reset) or 2-way set associative cache—128-byte
cache line
– 32-KB memory-mapped
– 16-KB ROM
The local memories can be used as cache RAMs or memory-mapped RAMs, depending on the
configuration of the different memory controllers in the IVA2.2 subsystem.
Figure 2-2 shows the memory hierarchy of the IVA2.2 subsystem.
216 Memory Mapping SPRUGN4L–May 2010–Revised June 2011
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