Xilinx System Generator for DSP: Reference Guide (UG638),Xilinx ...

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Chapter 1: Xilinx Blockset Simulink Blocks Supported by System Generator In general, Simulink blocks can be included in a Xilinx design for simulation purposes, but will not be mapped to Xilinx hardware. However, the following Simulink blocks are fully supported by System Generator and is mapped to Xilinx hardware: Table 1-13: Simulink Blocks Supported by System Generator Simulink Block Description Demux The Demux block extracts the components of an input signal and outputs the components as separate signals. From The From block accepts a signal from a corresponding Goto block, then passes it as output. Goto The Goto block passes its input to its corresponding From blocks. Mux The Mux block combines its inputs into a single vector output. Refer to the corresponding Simulink documentation for a complete description of the block. 46 www.xilinx.com System Generator for DSP Reference Guide UG638 (v14.5) March 20, 2013
Common Options in Block Parameter Dialog Boxes Common Options in Block Parameter Dialog Boxes Each Xilinx block has several controls and configurable parameters, seen in its block parameters dialog box. This dialog box can be accessed by double-clicking on the block. Many of these parameters are specific to the block. Block-specific parameters are described in the documentation for the block. The remaining controls and parameters are common to most blocks. These common controls and parameters are described below. Each dialog box contains four buttons: OK, Cancel, Help, and Apply. Apply applies configuration changes to the block, leaving the box open on the screen. Help displays HTML help for the block. Cancel closes the box without saving changes. OK applies changes and closes the box. Avoid Naming Your Design the Same as a Xilinx Block Precision Arithmetic Type Number of Bits Binary Point It is important that you don’t name your design the same as a Xilinx block. For example, if you name your design shared_memory.mdl, it may cause System Generator to issue an error message. The fundamental computational mode in the Xilinx blockset is arbitrary precision fixe- point arithmetic. Most blocks give you the option of choosing the precision, for example, the number of bits and binary point position. By default, the output of Xilinx blocks is full precision; that is, sufficient precision to represent the result without error. Most blocks have a User-Defined precision option that fixes the number of total and fractional bits In the Type field of the block parameters dialog box, you can choose unsigned or signed (two's complement) as the data type of the output signal. Fixed-point numbers are stored in data types characterized by their word size as specified by number of bits, binary point, and arithmetic type parameters. The maximum number of bits supported is 4096. The binary point is the means by which fixed-point numbers are scaled. The binary point parameter indicates the number of bits to the right of the binary point (for example,, the size of the fraction) for the output port. The binary point position must be between zero and the specified number of bits. Overflow and Quantization When user-defined precision is selected, errors can result from overflow or quantization. Overflow errors occur when a value lies outside the representable range. Quantization errors occur when the number of fractional bits is insufficient to represent the fractional portion of a value. The Xilinx fixed-point data type supports several options for user-defined precision. For overflow the options are to Saturate to the largest positive/smallest negative value, to Wrap (for example, to discard bits to the left of the most significant representable bit), or to Flag as error (an overflow as System Generator for DSP Reference Guide www.xilinx.com 47 UG638 (v14.5) March 20, 2013
Page 1 and 2: System Generator for DSP Reference
Page 3 and 4: Table of Contents Chapter 1: Xilinx
Page 5 and 6: Block Parameters Dialog Box. . . .
Page 7 and 8: DSP48E . . . . . . . . . . . . . .
Page 9 and 10: Block Interface . . . . . . . . . .
Page 11 and 12: Device Support . . . . . . . . . .
Page 13 and 14: See Also . . . . . . . . . . . . .
Page 15 and 16: Data Format . . . . . . . . . . . .
Page 17 and 18: See Also . . . . . . . . . . . . .
Page 19 and 20: Xilinx Blockset Chapter 1 Organizat
Page 21 and 22: AXI4 Blocks Table 1-1: AXI4 Blocks
Page 23 and 24: Table 1-2: Basic Element Blocks Blo
Page 25 and 26: Table 1-3: Communication Blocks - F
Page 27 and 28: Data Type Blocks Table 1-4: Control
Page 29 and 30: Table 1-6: DSP Blocks DSP Block Des
Page 31 and 32: Table 1-7: Floating-Point Blocks In
Page 33 and 34: Table 1-8: Index Blocks Index Block
Page 41 and 42: Math Blocks Table 1-9: Math Blocks
Page 43 and 44: Memory Blocks Table 1-10: Memory Bl
Page 45: Table 1-12: Tool Blocks Tool Blocks
Page 49 and 50: Sample Period Common Options in Blo
Page 51 and 52: Block Reference Pages Block Referen
Page 53 and 54: Device Support Floating-Point suppo
Page 55 and 56: LogiCORE Documentation Device Suppo
Page 57 and 58: Block Parameters Basic tab Addressa
Page 59 and 60: Refer to the section Overflow and Q
Page 61 and 62: Assert Other parameters used by thi
Page 63 and 64: AXI FIFO Block Interface Block Para
Page 65 and 66: LogiCORE Documentation Device Suppo
Page 67 and 68: Slice Repeat output_var = {port_ide
Page 69 and 70: Black Box Black Box This block is l
Page 71 and 72: Black Box can usually be used witho
Page 73 and 74: Block Parameters Basic tab Black Bo
Page 75 and 76: An Example Black Box The following
Page 77 and 78: ChipScope ChipScope This block is l
Page 79 and 80: Known Issues More Information ChipS
Page 81 and 82: Implementation tab CIC Compiler 2.0
Page 83 and 84: CIC Compiler 3.0 Number of Stages:
Page 85 and 86: Clock Enable Probe Clock Enable Pro
Page 87 and 88: Clock Probe Clock Probe This block
Page 89 and 90: Signed (2’s comp): The output is
Page 91 and 92: Complex Multiplier 3.1 Optional Por
Page 93 and 94: Page 2 tab Output Product Range Com
Page 95 and 96: Complex Multiplier 5.0 System Gener
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Concat Block Interface Block Parame
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Block Parameters The dialog box for
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Constant Floating-point Precision -
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Convert Block Parameters Convert Th
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Convolution Encoder 7.0 Convolution
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Convolution Encoder 8.0 Convolution
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CORDIC 4.0 CORDIC 4.0 This block is
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CORDIC 4.0 Precision: Configures t
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y_in to cartesian_tdata_imag phase
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CORDIC 5.0 Precision: Configures t
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Counter Counter This block is liste
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DDS Compiler 4.0 DDS Compiler 4.0 T
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DDS Compiler 4.0 phase_in: used wh
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DDS Compiler 4.0 rfd: When checked
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DDS Compiler 5.0 When set to stream
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Implementation tab DDS Compiler 5.0
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Phase Offset Angles tab DDS Compile
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Delay Block Parameters System Gener
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cascaded, albeit without using the
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System Generator for DSP Reference
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Depuncture Depuncture This block is
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Disregard Subsystem Disregard Subsy
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OR_all_TLASTS: Pass the logical OR
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Divider Generator 3.0 latency: Thi
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AXI Interface AXI behavior: NonBlo
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Down Sample Down Sample This block
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Block Parameters Basic tab Xilinx L
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DSP48 Provide BCOUT port: when sel
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DSP48 Macro Block Interface Block P
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DSP48 Macro Consider the simple mod
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Reserved Port Identifier Opmode Sel
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DSP48 Macro Pseudo Opmode P=+C+P+Ci
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External Registers DSP48 Macro This
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DSP48 macro 2.0 Individual register
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DSP48 macro 2.0 1. Make sure that i
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DSP48 Macro 2.1 Block Parameters DS
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DSP48 Macro 2.1 shown below. Notice
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DSP48 Macro 2.1 You can find the ab
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DSP48A Provide PCOUT port: when se
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DSP48E Block Parameters Basic tab D
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DSP48E carryout. When the mode of o
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See Also Implementation DSP48E Para
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DSP48E1 subtracter in the adder/sub
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DSP48E1 Length of acout pipeline:
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Dual Port RAM Block Interface Dual
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Collision Behavior The result of si
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Xilinx LogiCORE Dual Port RAM This
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EDK Processor EDK Processor This bl
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Advanced tab Parameters specific to
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Expression Block Parameters Express
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Output Signals: Fast Fourier Transf
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Basic tab Fast Fourier Transform 7.
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Virtex-7, Kintex-7, Virtex-6, Spart
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Block Parameters Fast Fourier Trans
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Fast Fourier Transform 8.0 Display
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Data path and control signals: Fast
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FDATool Example of Use FDA Tool Int
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FIR Compiler 5.0 coef_we: Used for
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FIR Compiler 5.0 The figure below s
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Number of paths: Specifies the numb
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FIR Compiler 6.2 FIR Compiler 6.2 T
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FIR Compiler 6.2 The output pins of
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FIR Compiler 6.2 User_Field: In th
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FIR Compiler 6.2 Both FIR Compiler
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Filter Specification Filter Type:
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Implementation tab FIR Compiler 6.3
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Interface tab FIR Compiler 6.3 Data
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From FIFO Block Parameters From FIF
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Output tab Output Type From FIFO S
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Binary point: position of the binar
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Gateway In Binary point: specifies
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System Generator Data Type Simulink
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Interleaver/De-interleaver 6.0 Inte
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Block Parameters Interleaver/De-int
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Interleaver/De-interleaver 6.0 Num
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Port Parameters tab Interleaver/De-
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Interleaver/De-interleaver 6.0 To a
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Device Support Virtex-7 and Kintex-
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Interleaver/De-interleaver 7.0 Alth
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AXI Interface Interleaver/De-interl
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Block Parameters Interleaver/De-int
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Rectangular Parameters #2 Tab Param
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Interleaver/De-interleaver 7.1 Inte
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Configuration Swapping Interleaver/
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Control Channel Input Signals: Inte
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COE File: The branch lengths are sp
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Interleaver/De-interleaver 7.1 ARE
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JTAG Co-Simulation Block Parameters
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Software tab JTAG Co-Simulation Par
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LFSR Feedback polynomial: This fie
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MCode MCode This block is listed in
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Relational operators: < Less than
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Constant Expressions MCode An expre
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Slice Function: xl_slice MCode Func
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MCode A method of a vector that que
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'b = ', num2str(b), ', ', ... 'x =
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FOR Loop FOR statement is fully unr
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MCode During the Simulink simulatio
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The following figure shows the bloc
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MCode The following M-code will als
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Pipelining Combinational Logic MCod
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ModelSim Block Parameters ModelSim
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Fine Points ModelSim The time scale
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ModelSim time scales. The actual de
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data type you select does not requi
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Multiple Subsystem Generator There
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domain_b_ce: in std_logic := '1'; d
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Mux Block Parameters This block is
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Natural Logarithm Natural Logarithm
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Network-based Ethernet Co-Simulatio
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Opmode Block Parameters Opmode This
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DSP48A Control Instruction Format D
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Instruction Field Name Carry In op[
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DSP48E1 Control Instruction Format
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Instruction Field Name Location Mne
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Pause Simulation Block Parameters P
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PicoBlaze Microcontroller Block Int
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PicoBlaze6 Instruction Display Bloc
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Block Interface Signal Direction De
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Device Support Supported PicoBlaze6
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Point-to-point Ethernet Co-Simulati
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Puncture Block Parameters Puncture
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Reciprocal SquareRoot Block Paramet
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Block Parameters Reed-Solomon Decod
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Reed-Solomon Decoder 7.1 Symbols P
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Reed-Solomon Decoder 8.0 Reed-Solom
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Reed-Solomon Decoder 8.0 event_s_c
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Attributes 2 tab Reed-Solomon Decod
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Reed-Solomon Encoder 7.1 Block Inte
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Block Parameters Reed-Solomon Encod
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Reed-Solomon Encoder 7.1 This is a
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Block Interface Channels and Pins R
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Reed-Solomon Encoder 8.0 Symbol wi
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Register Block Interface Block Para
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LogiCORE Documentation Device Suppo
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Reset Generator Block Parameters Re
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Resource Estimator hardware (except
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Resource Estimator design that is n
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Register Block Interface Block Para
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Scale Block Parameters Xilinx LogiC
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Shared Memory Block Interface Share
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Block Parameters Basic tab Shared M
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Shared Memory Read FIFO Transaction
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Shared Memory Write FIFO Transactio
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Shift Block Parameters Xilinx LogiC
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Block Parameters Simulation Multipl
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Write Modes Single Port RAM Provid
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Xilinx LogiCORE Single Port RAM The
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Single-Step Simulation Block Parame
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SquareRoot Block Parameters Basic t
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System Generator Create interface
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c. Observe the elements in the gene
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System Generator Block icon displa
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Threshold Block Parameters Xilinx L
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Block Parameters Time Division Demu
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To FIFO Block Parameters To FIFO Th
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Output tab Output Type To FIFO Spe
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Output tab Specify explicit output
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Toolbar Block Interface Toolbar Thi
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Up Sample Block Interface Up Sample
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VDMA Interface 4.0 VDMA Interface 4
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X-Ref Target - Figure 1-5 X-Ref Tar
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VDMA Interface 4.0 AXI VDMA registe
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Block Parameters Basic tab VDMA Int
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VDMA Interface 5.4 VDMA Interface 5
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Block Parameters Basic tab VDMA Int
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Viterbi Decoder 7.0 Block Interface
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Viterbi Decoder 7.0 Best State Use
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Page7 tab Synchronization Options V
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Viterbi Decoder 8.0 Block Interface
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data points. The delay equals the d
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Viterbi Decoder 8.0 Best State Use
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LogiCORE Documentation Device Suppo
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WaveScope automatically updates. Yo
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Block Interface WaveScope Cursor >
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WaveScope A logic signal will, by d
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The Grid WaveScope Displaying the G
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Move Cursor Next WaveScope This opt
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Xilinx Reference Blockset Communica
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2 Channel Decimate by 2 MAC FIR Fil
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2n-tap Linear Phase MAC FIR Filter
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4-channel 8-tap Transpose FIR Filte
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5x5Filter tab. 5x5Filter The Xilinx
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BPSK AWGN Channel Block Parameters
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Block Parameters Reference CIC Filt
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Block Interface Block Parameters Co
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CORDIC DIVIDER Block Parameters Ref
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Reference CORDIC LOG 1. J. E. Volde
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CORDIC SQRT Block Parameters CORDIC
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Dual Port Memory Interpolation MAC
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m-channel n-tap Transpose FIR Filte
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Example Block Parameters Mealy Stat
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Mealy State Machine The following t
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Example Moore State Machine Conside
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Multipath Fading Channel Model Theo
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Functions Multipath Fading Channel
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Input Multipath Fading Channel Mode
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Reference Multipath Fading Channel
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n-tap MAC FIR Filter Block Paramete
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Example Registered Mealy State Mach
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Registered Moore State Machine Regi
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Block Parameters Registered Moore S
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Virtex2 Line Buffer Block Parameter
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White Gaussian Noise Generator Whit
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Xilinx XtremeDSP Kit Blockset Block
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XtremeDSP Co-Simulation Block Param
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XtremeDSP Digital to Analog Convert
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XtremeDSP LED Flasher Block Paramet
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System Generator Utilities xlAddTer
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xlAddTerms Syntax Description xlAdd
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Examples Remarks See Also optionStr
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See Also xlCache [maxentries] = xlC
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xlfda_denominator Syntax Descriptio
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xlGenerateButton Syntax Description
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xlgetparam and xlsetparam When xlse
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See Also directory: './bitstream' t
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See Also Example To illustrate how
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xlLoadChipScopeData Syntax Descript
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xlSBDBuilder JTAG Options: System G
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xlSetNonMemMap Syntax Description E
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xlSwitchLibrary Syntax Description
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Field Names Description [Default va
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Remarks See Also xlTBUtils The acti
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xlUpdateModel Syntax Description xl
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Examples Example 1: >> xlUpdateMode
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xlVersion Syntax Description See Al
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System Generator GUI Utilities Chap
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Xilinx BlockAdd As shown below, to
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Xilinx BlockConnect Simple Connecti
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Xilinx Tools > Terminate How to Use
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Verifying Input Port Data Type Requ
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Programmatic Access System Generato
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xInport xOutport System Generator A
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System Generator API for Programmat
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PG API Examples Hello World PG API
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MACC in a Masked Subsystem PG API E
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You’ll get the following subsyste
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PG API Error/Warning Handling & Mes
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M-Code Access to Hardware Co-Simula
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M-Hwcosim Examples M-Code Access to
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Example 3 M-Code Access to Hardware
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Resource Management M-Code Access t
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Write data Syntax h('portName') = i
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elease(m); Description Releases the
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Set properties Syntax set(m, prop,
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xlHwcosimSimulate Syntax M-Code Acc
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Index Numerics 2 Channel Decimate b
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Expose Clock Ports option 408 Hybri
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