MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to ...

Software Impact of Errata Differences
The workaround stated above will have the same behavior on silicon versions 2.1.x and 3.1.x. As a result
of this erratum fix in silicon version 3.1.x, an invalid CRC is always appended when an error is detected
for a transmit frame, regardless of the FIFOCFG[CRCAPP] value. Software-implemented CRCs are now
supported with silicon version 3.1.x, since an invalid CRC will be appended if the frame has any error.
3.1.19 eTSEC 79: Generation of Ethernet Pause Frames May Cause Tx
Lockup and False BD Close
Software workaround:
• Option 1: Disable transmit flow control by setting MACCFG1[Tx_flow] = 0.
• Option 2: Run with a minimum platform (CCB) frequency of 500 MHz to insure correct Ethernet
operation at gigabit data rates. This workaround only applies to Ver 2.1.x.
• Option 3: Use the following method to detect TX lock up and recover from it.
Monitor Transmit Packet Counter TPKT and or Transmit Buffer Descriptor Pointers TBPTRn by
software and if no change is detected in the expected time (several multiple of maximum transition
time), and the Transmit halt of ring n bits in the transmit status register TSTAT[THLTn] is not set,
assume the transmitter is stuck by the above condition and proceed with the following recovery
mechanism:
a) Set DMACTRL[GRS] = 1 to perform a graceful receive stop.
b) Wait for IEVENT[GRSC] to be set, indicating stop complete.
c) Set DMACTRL[GTS] = 1 to perform a graceful transmit stop.
d) Wait for IEVENT[GTSC] to be set, indicating stop complete.
e) Write a 1 to IEVENT[GTSC] to acknowledge the event.
f) Clear MACCFG1[Tx_Flow].
g) Wait 256 TX_CLK cycles.
h) Clear MACCFG1[Tx_EN].
i) Wait 3 TX_CLK cycles.
j) Set MACCFG1[TX_EN] and MACCFG1[Tx_Flow].
k) Set DMACTRL[GTS] = 0 to clear the graceful transmit stop.
l) Set DMACTRL[GRS] = 0 to clear the graceful receive stop.
The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. As a result of this
erratum being fixed in silicon version 3.1.x, the workarounds are no longer necessary, but will not
adversely impact device functionality.
3.1.20 eTSEC 81: eTSEC Does Not Verify IPv6 Routing Header Type Field
Software workaround:
If this device is operating in a network that is using non-type0 IPv6 routing headers, then the upper
layer processing (IPv6 extension headers and payload checksumming operations) must be
performed in software.
MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0
10 Freescale Semiconductor