MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to ...

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Software Impact of Errata Differences In silicon version 2.1.x, stashing is controlled by the eTSEC DMA ATTR register. As a result of this erratum being fixed in silicon version 3.1.x, ring-by-ring control of stashing is available via the RQUEUE[EXn] bits. To achieve the same behavior as Rev 2.1.x, software must set all RQUEUE[EXn] bits to 0b1. By default, only EX0 is set to 1. If any of the EXn fields are set to 0b0, data transferred to the corresponding RxBD ring is not extracted to into the L2 cache, potentially resulting in a negative performance impact. 3.1.4 eTSEC58—Parsing of MPLS Label Stack or Non-IPv4/IPv6 Label Not Supported Software workaround: Limit MPLS Ether-type packets to MPLS label stack depth = 1 with IPv4 or IPv6 label. The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. 3.1.5 eTSEC59—Arbitrary Extraction on Short Frames Uses Data From Previous Frame Software workaround: • Option 1: Use only BnCTL = 01 (extract from offset of DA-8 bytes). For valid Ethernet frames (minimum length 64 bytes), the 6-bit offset cannot go beyond the end of the frame. • Option 2: Do not use the ARB filer property to reject frames if the controller may receive frames shorter than the location of any arbitrary extraction byte offset. Software must handle short frames that may be filed in the wrong queue. The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. As a result of this erratum being fixed in silicon version 3.1.x, filing based on arbitrary extraction of bytes is supported. Software that implements this workaround with silicon version 3.1.x is not taking full advantage of the filing capabilities supported in that version of silicon. 3.1.6 eTSEC62—eTSEC Half Duplex Receiver Packet Corruption Software workaround: The eTSEC can be configured through either the MAC address filter or the filer to discard such packets that are received in this manner through the use of MAC addresses filtering match and drop. The receive MIB counters may still incorrectly count packet errors. Use eTSEC loopback mode configuration for full-duplex operation. The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0 6 Freescale Semiconductor
Software Impact of Errata Differences 3.1.7 eTSEC63—May Drop Rx Packets in Non-FIFO Modes with Lossless Flow Control Enabled Software workaround: • Option 1: Enable interrupts on transmit of pause frames (IMASK[TXCEN] = 1). For every interrupt due to pause frame transmission (IEVENT[TXC] = 1), enable a counter such as a cycle count in the Performance Monitor block which would overflow and generate an interrupt after 2/3 of PVT time. If the counter is already enabled, reset the count to 2/3 of PTV time. In the overflow event interrupt handler, check the current number of free receive buffer descriptors versus the threshold. If the number of free BDs are below the threshold, manually transmit a pause frame by setting TCTRL[TFC_PAUSE] = 1. This also restarts the lossless flow control state machine. In either case (free BDs above or below threshold), disable the counter until the next transmit control frame event. • Option 2: Enable interrupts on dropped packets due to lack of RxBDs (EDIS[BSYDIS] = 0, IMASK[BSYEN] = 1). On detecting a busy dropped packet event (IEVENT[BSY] = 1), manually transmit a pause frame by setting TCTRL[TFC_PAUSE] to restart the lossless flow control state machine. As a result of this erratum being fixed in silicon version 3.1.x, the above workarounds are no longer necessary. Software that implements this workaround with silicon version 3.1.x may result in a system transmitting more pause frames than necessary. 3.1.8 eTSEC64—Back-to-Back IPv6 Routing Headers Not Supported by Parser Software workaround: Software must parse the L4 information out of packets that indicate PRO = 0xFF. The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. As a result of this erratum fix in silicon version 3.1.x, parsing continues beyond the back-to-back routing headers and is reflected in the RxFCB. 3.1.9 eTSEC65—RxBD[TR] Not Asserted During Truncation When Last 4 Bytes Match CRC There is no workaround provided for erratum eTSEC65. As a result of this erratum fix in silicon version 3.1.x, these truncated packets have their RxBD[TR] set. This does not have any impact on systems that send frames of size MAXFRM or smaller. 3.1.10 eTSEC 66—Parser Continues Parsing L4 Fields When RCTRL[PRSDEP] Set for L2 and L3 Fields Only Software workaround: Knowing this behavior, the user can simply ignore the information associated with L4 protocols. In the case of filer PID = 1, the user must mask bits associated with TCP and UDP. MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0 Freescale Semiconductor 7
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: Table 2. Summary of Silicon Errata
Page 5: 3 Software Impact of Errata Differe
Page 9 and 10: Software Impact of Errata Differenc
Page 17 and 18: MPC8548 PowerQUICC III Silicon Chan

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