MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to ...

System and Processor Version
1 System and Processor Version
Table 1 provides a cross-reference to match the revision level to the processor version register (PVR) and
the system version register (SVR). Software that uses the PVR or the SVR must take into account the
changes in these values with silicon version 3.1.x.
SC8548HMPC854
8/E Revision
Table 1. Revision Level to Part Marking Cross-Reference
e500 v2 Core
Revision
Processor Version
Register Value
2 Errata Difference Summary
This section describes the errata differences in MPC8548 between versions 2.1.x and 3.1.x.
2.1 Full Errata Fix Implemented in Rev 3.1.x
System Version
Register Value
2.0 2.0 0x8021_0020 With security
0x8039_0020
Without security
0x80310020
2.1.1 2.2 0x8021_0022 With security
0x8039_0021
Without security
0x80310021
2.1.2 2.2 0x8021_0022 With security
0x8039_0021
Without security
0x80310021
3.1.x 2.3 0x8021_0023 With security
0x8039_0031
Without security
0x80310031
Table 2 lists the silicon version 2.1.x device errata which have had a full fix implemented in silicon version
3.1.x.
Table 2. Summary of Silicon Errata Fixed in MPC8548 Rev 3.1.x
Errata Name
eTSEC
eTSEC 34 Transmit frames aborted under 16-bit FIFO GMII-style mode
eTSEC 38 WWR bit Anomaly
eTSEC 57 RQUEUE[EXn] bits have no effect
eTSEC 58 Parsing of MPLS label stack or non-IPv4/IPv6 label not supported
eTSEC 59 Arbitrary extraction on short frames uses data from previous frame
eTSEC 62 eTSEC half duplex receiver packet corruption
MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0
Device Marking
2M39E
3M39E
6M39E
7M39E
1N06D, 2N06D
2 Freescale Semiconductor