MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to ...

Freescale Semiconductor 

Application Note 

MPC8548 PowerQUICC III Silicon 

Changes from Version 2.1.x 

to Version 3.1.x 

By Freescale Semiconductor, Inc. 

The MPC8548 PowerQUICC III integrated processor 

version 3.1.x silicon built on Power Architecture® 

technology incorporates changes to fix known errata. This 

document describes the differences between version 2.1.x 

and version 3.1.x. 

© 2012 Freescale Semiconductor, Inc. All rights reserved. 

Document Number: AN4191 

Rev. 0, 02/2012 

Contents 

1. System and Processor Version . . . . . . . . . . . . . . . . . . 2 

2. Errata Difference Summary . . . . . . . . . . . . . . . . . . . . 2 

3. Software Impact of Errata Differences . . . . . . . . . . . . 5 

4. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

System and Processor Version 

1 System and Processor Version 

Table 1 provides a cross-reference to match the revision level to the processor version register (PVR) and 

the system version register (SVR). Software that uses the PVR or the SVR must take into account the 

changes in these values with silicon version 3.1.x. 

SC8548HMPC854 

8/E Revision 

Table 1. Revision Level to Part Marking Cross-Reference 

e500 v2 Core 

Revision 

Processor Version 

Register Value 

2 Errata Difference Summary 

This section describes the errata differences in MPC8548 between versions 2.1.x and 3.1.x. 

2.1 Full Errata Fix Implemented in Rev 3.1.x 

System Version 

Register Value 

2.0 2.0 0x8021_0020 With security 

0x8039_0020 

Without security 

0x80310020 

2.1.1 2.2 0x8021_0022 With security 

0x8039_0021 


0x80310021 

2.1.2 2.2 0x8021_0022 With security 

0x8039_0021 


0x80310021 

3.1.x 2.3 0x8021_0023 With security 

0x8039_0031 


0x80310031 

Table 2 lists the silicon version 2.1.x device errata which have had a full fix implemented in silicon version 

3.1.x. 

Table 2. Summary of Silicon Errata Fixed in MPC8548 Rev 3.1.x 

Errata Name 

eTSEC 

eTSEC 34 Transmit frames aborted under 16-bit FIFO GMII-style mode 

eTSEC 38 WWR bit Anomaly 

eTSEC 57 RQUEUE[EXn] bits have no effect 

eTSEC 58 Parsing of MPLS label stack or non-IPv4/IPv6 label not supported 

eTSEC 59 Arbitrary extraction on short frames uses data from previous frame 

eTSEC 62 eTSEC half duplex receiver packet corruption 

MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0 

Device Marking 

2M39E 

3M39E 

6M39E 

7M39E 

1N06D, 2N06D 

2 Freescale Semiconductor

Table 2. Summary of Silicon Errata Fixed in MPC8548 Rev 3.1.x (continued) 

Errata Name 

eTSEC 63 May drop Rx packets in non-FIFO modes with lossless flow control enabled 

eTSEC 64 Back-to-back IPv6 routing headers not supported by parser 

eTSEC 65 RxBD[TR] not asserted during truncation when last 4 bytes match CRC 

eTSEC 66 Parser continues parsing L4 fields when RCTRL[PRSDEP] set for L2 and L3 fields only 


Errata Difference Summary 

eTSEC 68 Rx TCP/UDP checksum checking may be incorrect while operating at low frequencies in FIFO mode 

eTSEC 69 Filer does not support matching against broadcast address flag PID1[EBC] 

eTSEC 71 eTSEC filer reports incorrect Ether-types with certain MPLS frames 

eTSEC 72 Compound filer rules do not roll back the mask 

eTSEC 73 Incomplete frame with error causes false CR error on next frame 

eTSEC 74 eTSEC 74: Parser does not check VER/TYPE of PPPoE packets 

eTSEC 76 RMCA, RBCA counters do not correctly count valid VLAN tagged frames 

eTSEC 77 Tx errors truncate packets without error in 8-bit Encoded FIFO mode 

eTSEC 79 Generation of Ethernet pause frames may cause Tx lockup and false BD close 

eTSEC 81 eTSEC does not verify IPv6 routing header type field 

eTSEC 82 Transmission of truncated frames may cause hang or lost data 

eTSEC 83 L3 fragment frame files on non-existent source/destination ports 

eTSEC 85 TxBD[TC] is not reliable in 16-bit FIFO modes 

eTSEC 87 Arbitrary Extraction cannot extract last data bytes of frame 

eTSEC 88 False TCP/UDP and IP checksum error in FIFO mode without CRC appending 

eTSEC 89 Frames greater than 9600 bytes with TOE = 1 will hang controller 

eTSEC 90 Setting RCTRL[LFC] = 0 may not immediately disable LFC 

eTSEC 92 False parity error at Tx startup 

eTSEC 94 Rx packet padding limitations at low clock ratios 

eTSEC 95 False TCP/UDP checksum error for some values of pseudo header Source Address 

eTSEC 98 FIFO16 interface encoded mode maximum frequency is 1/4.2 platform clock 

eTSEC 99 ECNTRL[AUTOZ] not guaranteed if reading MIB counters with software 

eTSEC 104 Rx may hang if RxFIFO overflows 

eTSEC 105 Malformed Magic Packet Triggers Magic Packet Exit 

eTSEC 106 Excess delays when transmitting TOE=1 large frames 

eTSEC 107 Controller may not be able to transmit pause frame during pause state 

eTSEC-A001 MAC: Pause time may be shorter than specified if transmit in progress 

eTSEC-A004 User-defined preamble not supported at low clock ratios 

CPU 

Freescale Semiconductor 3

Errata Difference Summary 

Table 2. Summary of Silicon Errata Fixed in MPC8548 Rev 3.1.x (continued) 

Errata Name 

CPU-A005 Enabling IEEE 754 exceptions can cause errors 

DMA 2 Transfer error reported for wrong channel 

DMA 

GEN 

GEN 11 Some pins do not meet 500V CDM ESD criteria 

GEN 13 CPU write to platform failures in all core, platform, and SYSCLK frequency combinations 

PCI-Express 

PCI-Ex 35 Rx detection by transmitter does not pass high receiver impedance test 

PCI-Ex 37 Completion Timeout error disable corrupts CRS threshold error data 

PCI-Ex 38 PCI Express LTSSM may fail to properly train with a link partner following HRESET 

PCI-Ex 39 No mechanism for recovery from hang after access to down link 

PCI-Ex 42 Reads to PCI Express CCSRs or local configuration space temporarily return all Fs 

PCIe-A001 PCI Express Hot Reset event may cause data corruption 

SRIO 

SRIO-A002 SRIO reset command does not result in device reset 

I2C 2 Enabling I2C could cause I2C bus freeze when other I2C devices communicate 

2.2 Partial Errata Fix Implemented in Rev 3.1.x 

Table 3 lists the silicon version 2.1.x device errata which have had a partial fix implemented in silicon 

version 3.1.x. 

I2C 

Table 3. Summary of Silicon Errata Partially Fixed in MPC8548 Rev 3.1.x 

Errata Name 

eTSEC 

eTSEC 67 Fetches with errors not flagged, may cause livelock or false halt 

eTSEC 84 Multiple BD frame may cause hang 

eTSEC 93 Transmit fails to utilize 100% of line bandwidth 

DMA 1 DMA_DACK bus timing violation when operating in external DMA master mode 



3 Software Impact of Errata Differences 

Software Impact of Errata Differences 

This section describes the software impact of errata differences between silicon versions 2.1.x and 3.1.x. 

3.1 Software Impact of Full Errata Fixes in Rev 3.1.x 

This section describes the software impact of full errata fixes in silicon version 3.1.x, including the impact 

of leaving the silicon version 2.1.x workaround in software used with silicon version 3.1.x. 

3.1.1 eTSEC 34—Transmit Frames Aborted Under 16-bit FIFO GMII-style 

Mode 

Software workaround: 

Use of encoded mode for any 16 bit FIFO packet interface instead of GMII style signaling is 

recommended. The FIFO Encoded mode will not abort packets if underrun occurs; instead, it will 

assert idle bytes during the data stream. 

The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. As a result of this 

erratum being fixed in silicon version 3.1.x, 16-bit FIFO mode can be used. 

3.1.2 eTSEC 38—WWR Bit Anomaly 


Set DMACTRL[WWR] = 0. The effect of setting DMACTRL[WWR] = 0 is that the interrupt may 

arrive at the processor before the update to the BD for the received packet that caused the interrupt 

has been completed in memory. 

This may or may not have any impact on the system depending on how packets are processed. If 

the CPU reads the BD immediately after the interrupt, then in heavily congested systems it is 

possible that the CPU completes a read of the BD before the BD is closed by the eTSEC so that the 

BD's Empty bit is still set. 

In this case, software can either exit the packet processing routine and service the packet upon 

receiving the next interrupt, or it can schedule another interrupt to process the packet later. 

Use of Rx interrupt coalescing of even a few packets reduce the chance of the CPU reading a BD 

whose update is still in flight to virtually zero, though it is still possible if multiple receive rings 

are in use. 


erratum being fixed in silicon version 2.0/2.1, WWR = 1 is supported. Software that implements this 

workaround with silicon version 2.0/2.1 is not taking full advantage of the features supported in that 

version of silicon. 

3.1.3 eTSEC 57—RQUEUE[EXn] Bits Have No Effect 

For erratum eTSEC57 on silicon version 2.1.x, there is no workaround. 




In silicon version 2.1.x, stashing is controlled by the eTSEC DMA ATTR register. As a result of this 

erratum being fixed in silicon version 3.1.x, ring-by-ring control of stashing is available via the 

RQUEUE[EXn] bits. To achieve the same behavior as Rev 2.1.x, software must set all RQUEUE[EXn] 

bits to 0b1. By default, only EX0 is set to 1. If any of the EXn fields are set to 0b0, data transferred to the 

corresponding RxBD ring is not extracted to into the L2 cache, potentially resulting in a negative 

performance impact. 

3.1.4 eTSEC58—Parsing of MPLS Label Stack or Non-IPv4/IPv6 Label Not 

Supported 


Limit MPLS Ether-type packets to MPLS label stack depth = 1 with IPv4 or IPv6 label. 

The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. 

3.1.5 eTSEC59—Arbitrary Extraction on Short Frames Uses Data From 

Previous Frame 


• Option 1: Use only BnCTL = 01 (extract from offset of DA-8 bytes). For valid Ethernet frames 

(minimum length 64 bytes), the 6-bit offset cannot go beyond the end of the frame. 

• Option 2: Do not use the ARB filer property to reject frames if the controller may receive frames 

shorter than the location of any arbitrary extraction byte offset. Software must handle short frames 

that may be filed in the wrong queue. 


erratum being fixed in silicon version 3.1.x, filing based on arbitrary extraction of bytes is supported. 

Software that implements this workaround with silicon version 3.1.x is not taking full advantage of the 

filing capabilities supported in that version of silicon. 

3.1.6 eTSEC62—eTSEC Half Duplex Receiver Packet Corruption 


The eTSEC can be configured through either the MAC address filter or the filer to discard such 

packets that are received in this manner through the use of MAC addresses filtering match and 

drop. The receive MIB counters may still incorrectly count packet errors. Use eTSEC loopback 

mode configuration for full-duplex operation. 





3.1.7 eTSEC63—May Drop Rx Packets in Non-FIFO Modes with Lossless 

Flow Control Enabled 


• Option 1: Enable interrupts on transmit of pause frames (IMASK[TXCEN] = 1). For every 

interrupt due to pause frame transmission (IEVENT[TXC] = 1), enable a counter such as a cycle 

count in the Performance Monitor block which would overflow and generate an interrupt after 2/3 

of PVT time. If the counter is already enabled, reset the count to 2/3 of PTV time. In the overflow 

event interrupt handler, check the current number of free receive buffer descriptors versus the 

threshold. If the number of free BDs are below the threshold, manually transmit a pause frame by 

setting TCTRL[TFC_PAUSE] = 1. This also restarts the lossless flow control state machine. In 

either case (free BDs above or below threshold), disable the counter until the next transmit control 

frame event. 

• Option 2: Enable interrupts on dropped packets due to lack of RxBDs (EDIS[BSYDIS] = 0, 

IMASK[BSYEN] = 1). On detecting a busy dropped packet event (IEVENT[BSY] = 1), manually 

transmit a pause frame by setting TCTRL[TFC_PAUSE] to restart the lossless flow control state 

machine. 

As a result of this erratum being fixed in silicon version 3.1.x, the above workarounds are no longer 

necessary. Software that implements this workaround with silicon version 3.1.x may result in a system 

transmitting more pause frames than necessary. 

3.1.8 eTSEC64—Back-to-Back IPv6 Routing Headers Not Supported by 

Parser 


Software must parse the L4 information out of packets that indicate PRO = 0xFF. 


erratum fix in silicon version 3.1.x, parsing continues beyond the back-to-back routing headers and is 

reflected in the RxFCB. 

3.1.9 eTSEC65—RxBD[TR] Not Asserted During Truncation When Last 4 

Bytes Match CRC 

There is no workaround provided for erratum eTSEC65. As a result of this erratum fix in silicon version 

3.1.x, these truncated packets have their RxBD[TR] set. This does not have any impact on systems that 

send frames of size MAXFRM or smaller. 

3.1.10 eTSEC 66—Parser Continues Parsing L4 Fields When 

RCTRL[PRSDEP] Set for L2 and L3 Fields Only 


Knowing this behavior, the user can simply ignore the information associated with L4 protocols. 

In the case of filer PID = 1, the user must mask bits associated with TCP and UDP. 




As a result of this erratum fix in silicon version 3.1.x, the L4 fields are not parsed when 

RCTRL[PRSDEP] = 0b10. Software that ignores L4 parsing information when RCTRL[PRSDEP] = 0b10 

continues to function in silicon version 2.1.x. 

3.1.11 eTSEC68—Rx TCP/UDP Checksum Checking May be Incorrect 

While Operating at Low Frequencies In FIFO Mode 


• Option 1: Turn off Rx checksum checking by setting RCTRL[TUCSEN] = 0. 

• Option 2: Ensure that the minimum platform frequency to eTSEC Rx_CLK ratio with Rx 

checksum checking enabled in FIFO mode is greater than or equal to 4:1 (for example, 500 MHz 

platform frequency with 125 MHz Rx_CLK). 

• Option 3: Ensure that packets that are being checksummed have at least 4 bytes of data at the end 

of the packet that is not to be included in the checksum (such as a CRC) 

The impact of this workaround fix is that TCP/UDP header checksum generation is now supported at all 

platform:Rx_CLK ratios in silicon version 2.0/2.1. 

3.1.12 eTSEC69—Filer Does Not Support Matching Against Broadcast 

Address Flag PID1[EBC] 


Mask off matching on broadcast address flag (PID1[EBC] = 1) by clearing the bit 16 of the mask 

register. If the rule needs to be able to distinguish broadcast addresses as defined by IEEE Std 

802.3 – 2005 is all 1’s in the destination address field, then use a filer rule with PID3 and PID4 

(destination MAC address) to match on broadcast Ethernet frames. 

The workaround stated above will have the same behavior on silicon versions 2.1.x and 3.1.x. As a result 

of this erratum fix in silicon version 3.1.x, the filer now supports matching based on broadcast address. 

3.1.13 eTSEC 71—eTSEC Filer Reports Incorrect Ether-types With Certain 

MPLS Frames 


Use arbitrary extraction bytes to compare to the actual Ether-type if a filer rule is intending to file 

based on an MPLS label existence. 


erratum fix in silicon version 3.1.x, the correct Ether-type can be extracted from these types of packets. 




3.1.14 eTSEC 72—Compound Filer Rules Do Not Roll Back the Mask 


When using a compound rule that consists of SETMASK rules, the user must put another 

SETMASK rule after the last rule in the chain that resets the mask to the value it was prior to 

entering the chain. 


erratum fix in silicon version 3.1.x, this additional SETMASK rule is no longer required. 

3.1.15 eTSEC73—Incomplete Frame with Error Causes False CR error on 

Next Frame 


To work around this problem when the link is down, typically the PHY generates a link down 

interrupt. When this link down interrupt is detected, software must do the following: 

a) Perform a soft_reset (MACCFG1[Soft_Reset] = 1) or a receiver reset (MACCFG1[Reset Rx 

Func] = 1) 

b) Keep the MAC in reset until the link is up again. 

c) Discard any frames received during link down. 

d) Re-enable the receiver after the link is up. 

The workaround stated above will have the same behavior on silicon versions 2.1.x and 3.1.x. 

3.1.16 eTSEC 74: Parser Does Not Check VER/TYPE of PPPoE Packets 

There is no workaround provided for erratum eTSEC74. As a result of this erratum fix in silicon version 

3.1.x, the VER/TYPE field in PPPoE packets are checked by the controller. 

3.1.17 eTSEC 76: RMCA, RBCA Counters Do Not Correctly Count Valid 

VLAN Tagged Frames 

There is currently no work around for counting these packets other than software running on the core. 

As a result of this erratum fix in silicon version 3.1.x, RBCA and RMCA also increment for validly VLAN 

tagged Ethernet frames greater than 1518. Counting these packets in software is no longer necessary. 

3.1.18 eTSEC 77: Tx Errors Truncate Packets Without Error in 8-bit 

Encoded FIFO Mode 


Enable CRC append on Tx by setting FIFOCFG[CRCAPP] = 1 and CRC checking on Rx by setting 

FIFOCFG[CRCCHK] = 1. The truncation of the packet at the error presents a smaller than 1 in 4 

billion chance that the last four bytes of the packet match the running CRC32 calculation, ensuring 

that the packet is still seen is error. 




The workaround stated above will have the same behavior on silicon versions 2.1.x and 3.1.x. As a result 

of this erratum fix in silicon version 3.1.x, an invalid CRC is always appended when an error is detected 

for a transmit frame, regardless of the FIFOCFG[CRCAPP] value. Software-implemented CRCs are now 

supported with silicon version 3.1.x, since an invalid CRC will be appended if the frame has any error. 

3.1.19 eTSEC 79: Generation of Ethernet Pause Frames May Cause Tx 

Lockup and False BD Close 


• Option 1: Disable transmit flow control by setting MACCFG1[Tx_flow] = 0. 

• Option 2: Run with a minimum platform (CCB) frequency of 500 MHz to insure correct Ethernet 

operation at gigabit data rates. This workaround only applies to Ver 2.1.x. 

• Option 3: Use the following method to detect TX lock up and recover from it. 

Monitor Transmit Packet Counter TPKT and or Transmit Buffer Descriptor Pointers TBPTRn by 

software and if no change is detected in the expected time (several multiple of maximum transition 

time), and the Transmit halt of ring n bits in the transmit status register TSTAT[THLTn] is not set, 

assume the transmitter is stuck by the above condition and proceed with the following recovery 

mechanism: 

a) Set DMACTRL[GRS] = 1 to perform a graceful receive stop. 

b) Wait for IEVENT[GRSC] to be set, indicating stop complete. 

c) Set DMACTRL[GTS] = 1 to perform a graceful transmit stop. 

d) Wait for IEVENT[GTSC] to be set, indicating stop complete. 

e) Write a 1 to IEVENT[GTSC] to acknowledge the event. 

f) Clear MACCFG1[Tx_Flow]. 

g) Wait 256 TX_CLK cycles. 

h) Clear MACCFG1[Tx_EN]. 

i) Wait 3 TX_CLK cycles. 

j) Set MACCFG1[TX_EN] and MACCFG1[Tx_Flow]. 

k) Set DMACTRL[GTS] = 0 to clear the graceful transmit stop. 

l) Set DMACTRL[GRS] = 0 to clear the graceful receive stop. 


erratum being fixed in silicon version 3.1.x, the workarounds are no longer necessary, but will not 

adversely impact device functionality. 

3.1.20 eTSEC 81: eTSEC Does Not Verify IPv6 Routing Header Type Field 


If this device is operating in a network that is using non-type0 IPv6 routing headers, then the upper 

layer processing (IPv6 extension headers and payload checksumming operations) must be 

performed in software. 




Leaving this workaround in software used with silicon version 3.1.x results in a redundant check of routing 

type Value. 

3.1.21 eTSEC 82: Transmission of Truncated Frames May Cause Hang or 

Lost Data 


• Option 1: Disable truncation by setting MACCFG2[Huge Frame] = 1. 

• Option 2: Turn off TCP/IP offload enable by setting TxBD[TOE] = 0. 

As a result of this erratum being fixed in silicon version 3.1.x, these two features can be used 

simultaneously. Software that implements this workaround with silicon version 3.1.x does not take full 

advantage of the features supported in that version of silicon. 

3.1.22 eTSEC 83: L3 Fragment Frame Files on Non-existent 

Source/Destination Ports 


• Option 1: Include a filer rule to reject on PID1[IPF] at the beginning of the table. 

• Option 2: Limit parsing to L2 by setting RCTRL[PRSDEP] = 01. Note that limiting parsing to L3 

by setting RCTRL[PRSDEP] = 10 is not a valid work around (refer to eTSEC 9). 


3.1.23 eTSEC 85: TxBD[TC] is Not Reliable in 16-bit FIFO Modes 


• Option 1: Set FIFOCFG[CRCAPP] = 1 in 16-bit FIFO modes to force hardware append of CRC 

on all the frames, regardless of TxBD[TC] state. 

• Option 2: Set all TxBD[TC] = 0. 


erratum fix in silicon version 3.1.x, using CRC append on a frame-by-frame basis with TxBD[TC] is now 

supported. 

3.1.24 eTSEC 87: Arbitrary Extraction Cannot Extract Last Data Bytes of 

Frame 

Due to erratum eTSEC87 on silicon version 2.1.x, certain bytes cannot be extracted from a frame. No 

workaround is specified for this erratum. The impact of the fix is that this byte-extraction limitation does 

not apply to silicon version 3.1.x. 




3.1.25 eTSEC 88: False TCP/UDP and IP Checksum Error in FIFO Mode 

Without CRC Appending 


Set FIFOCFG[CRCCHK] = 1 to enable CRC checking on Rx and enable CRC append on the 

corresponding Tx on the link (by setting the equivalent of FIFOCFG[CRCAPP] = 1). Having CRC 

in the frame ensures that the last data beat is properly aligned for IP or TCP/UDP checksum 

checking. 


erratum fix in silicon version 3.1.x, it is no longer required to use FIFOCFG[CRCCHK] when running in 

FIFO mode. 

3.1.26 eTSEC 89: Frames Greater than 9600 Bytes with TOE = 1 Will Hang 

Controller 


For frames larger than 9600 bytes, set TxBD[TOE] = 0. For frames with TxBD[TOE] = 1, ensure 

Tx frame length 9600 bytes. 

The workaround stated above will have the same behavior on silicon versions 2.1.x and 3.1.x. Because the 

eTSEC supports a maximum frame size of 9600 bytes, packets larger than this still must not be transmitted. 

As a result of this erratum fix, rather than hang the eTSEC controller, frames larger than 9600 bytes result 

in an underrun error (IEVENT[XFUN] = 1). 

3.1.27 eTSEC 90: Setting RCTRL[LFC] = 0 May Not Immediately Disable 

LFC 


When disabling LFC, first set RCTRL[LFC] = 0, then poll the number of free RxBDs until it 

exceeds the threshold. When the number of free RxBDs exceeds the threshold, the configuration 

for LFC may be safely modified. 

As a result of this errata fix in silicon version 3.1.x, it is no longer necessary to poll the number of free 

RxBDs, since lossless flow control will be immediately disabled. The workaround stated above has the 

same behavior on silicon versions 2.1.x and 3.1.x. 

3.1.28 eTSEC 92: False Parity Error at Tx Startup 


Disable parity error detection by setting EDIS[DPEDIS] = 1 until at least 10 kilobytes of Tx data 

has been transmitted. 

As a result of this errata fix in silicon version 3.1.x, it is no longer necessary to disable parity error 

detection. The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. 




3.1.29 eTSEC 94: Rx Packet Padding Limitations at Low Clock Ratios 


Limit total receive packet byte insertion via RCTRL[PAL] and Rx preamble enable to less than 24 

bytes total when running at less than 2:1 eTSEC system clock: TSECn_TX_CLK ratio. 


erratum fix in silicon version 3.1.x, this limitation on data insertion no longer applies. 

3.1.30 eTSEC 95: False TCP/UDP Checksum Error for Some Values of 

Pseudo Header Source Address 


If RxFCB[CTU] = 1, RxFCB[ETU] = 1 and RxFCB[IP6] = 1, calculate the checksum for the SA 

field from the pseudo header. If this checksum equals 0x1_0000, then proceed to calculate the 

entire TCP checksum to be sure the checksum error is valid. If the SA checksum is not 0x1_0000, 

then the ETU is a valid checksum error indication. 

As a result of this errata fix in silicon version 3.1.x, this manual checksum calculation is not required. 

Leaving this workaround in software used with silicon version 3.1.x results in redundant checksum 

checking for IPv6 packets with checksum errors reported. 

3.1.31 eTSEC 98: FIFO16 Interface Encoded Mode Maximum Frequency is 

1/4.2 Platform Clock 


Run the FIFO16 interface no faster than 1/4.2 the platform clock. 

As a result of this errata fix in silicon version 3.1.x, the FIFO16 interface encoded mode maximum 

frequency is 1/3.2 platform clock. The hardware specification will be updated accordingly. 

3.1.32 eTSEC 99: ECNTRL[AUTOZ] Not Guaranteed if Reading MIB 

Counters with Software 

For eTSEC99 on silicon version 2.1.x, a software workaround was provided, using 

ECNTRL[AUTOZ] = 0. This workaround has the same behavior on silicon versions 2.1.x and 3.1.x. As a 

result of this errata fix, AUTOZ functionality is now supported. 

3.1.33 eTSEC 104: Rx May Hang if RxFIFO Overflows 

For erratum eTSEC104 on silicon version 2.1.x, a detailed software workaround is provided in the 

MPC8548 chip errata document. As a result of eTSEC104 being fixed in silicon version 3.1.x, the lockup 

detection mechanism is no longer required. If the lockup detection mechanism is used with silicon version 

3.1.x, then under certain circumstances false detections may still be triggered, as may occur with silicon 

version 2.1.x. In these cases the receiver would be needlessly reset. Normal data transmission and 

reception resumes after the receiver has been reset. 




3.1.34 eTSEC 105: MAC: Malformed Magic Packet Triggers Magic Packet 

Exit 

No workaround is specified for this erratum. The impact of the fix is that these malformed packets do not 

trigger an exit from magic packet mode in silicon version 3.1.x. 

3.1.35 eTSEC 106: Excess Delays When Transmitting TOE = 1 Large 

Frames 


Limit TOE = 1 frames to less than 2500 bytes to avoid excess delays due to memory throttling. 

When using packets larger than 2700 bytes, it is recommended to turn TOE off. 


errata fix in silicon version 3.1.x, performance can be improved by enabling TOE. 

3.1.36 eTSEC 107: Controller May Not be Able to Transmit Pause Frame 

During Pause State 

Due to erratum eTSEC107 on silicon version 2.1.x, pause frames may not be sent while the device is in a 

pause state. No workaround is specified for this erratum. 

As a result of the erratum fix in silicon version 3.1.x, the device is capable of sending pause frames while 

in a paused state. 

3.1.37 eTSEC-A001: MAC: Pause tIme May be Shorter than Specified if 

Transmit in Progress 


Add 2 pause quanta to the pause time value used when generating pause frames to prevent receive 

buffer overflow. 


3.1.38 eTSEC-A004: User-defined Preamble Not Supported at Low Clock 

Ratios 


Disable user-defined preamble Tx injection by setting MACCFG2[PreAmTxEn] = 0. 





3.1.39 CPU-A005: Enabling IEEE 754 Exceptions Can Cause Errors 


• Option 1: Ensure that the floating-point data exceptions are disabled by clearing the SPEFSCR 

exception enable bits (FINVE, FDBZE, FUNFE, or FOVFE). 

• Option 2: Exception handler make the hardware re-execute the instruction, if a floating point 

instruction causes an unexpected data exception. If the exception was a result of this erratum, there 

are no exception on re-execution. Freescale will make this modification to the exception handler 

we provide to the open source community. 

The first workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. The second 

workaround has no adverse impact to device functionality, as no unexpected data exceptions should occur. 

3.1.40 DMA 2: Transfer Error Reported for Wrong Channel 


• Option 1: Do not configure the ATMUs as described. 

• Option 2: When a channel completes a block transfer or descriptor chain, check that no other 

channel has its transfer error set. 

• Option 3: Use one channel at a time. Not very practical since it reduces the DMA to a one-channel 

DMA. 


3.1.41 GEN 11 - Some Pins Do Not Meet 500V CDM ESD Criteria 

Due to erratum GEN 11 on silicon version 2.1.x, some device pins do not meet the 500V Charged Device 

Model (CDM) ESD criteria. 

As a result of the erratum fix in silicon version 3.1.x, the device is expected to meet the specified ESD 

criteria, pending full ESD testing results. 

3.1.42 GEN 13 - CPU Write to Platform Failures in all Core, Platform, and 

SYSCLK Frequency Combinations 


Systems are restricted to the following configurations: 

a) Core is limited to minimum frequency of 800 MHz. 

b) Platform (CCB) is limited to minimum frequency of 333 MHz 

c) SYSCLK is limited to maximum frequency of 133 MHz 

The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x, but with version 

3.1.x the configuration limitations no longer exist. 




3.2 Software Impact of Partial Errata Fixes in Rev 3.1.x 

This section describes the software impact of the partial errata fixes in silicon version 3.1.x, including the 

impact of leaving the silicon version 2.1.x workaround in software used with silicon version 3.1.x. 

3.2.1 eTSEC 67—Fetches With Errors Not Flagged, May Cause Livelock or 

False Halt 


a) Ensure all eTSEC BD and data addresses map to valid regions of memory. 

b) Ensure EDIS[EBERRDIS] = 0. 

The workaround stated above continues to function on silicon version 3.1.x. 

3.2.2 eTSEC 84—Multiple BD Frame May Cause Hang 


Software must ensure that the ready bit of the first BD in a multiple TxBD frame is not set until 

after the remaining BDs of the frame are set ready. 


partial fix, violating this programming guideline in systems with multiple BD rings will trigger an 

underrun error, and will not hang the Ethernet controller. Violating the programming guideline Single 

TxBD ring operation may still cause the Ethernet controller to hang. 

3.2.3 DMA 1-DMA-DACK Bus Timing Violation When Operating in 

External DMA Master Mode 

Due to erratum DMA 1 on silicon version 2.1.x, in external DMA master mode, the DMA_DACK signal 

must be held for 6 CCB_clocks instead of three. 

In silicon version 3.1.x this erratum has been fixed except if the CCB Clock PLL Ratio is configured to 

either 9:1 or 20:1 setting. 

3.2.4 eTSEC 93—Transmit Fails to Utilize 100% of Line Bandwidth 

Due to erratum eTSEC93 on silicon version 2.1.x, the eTSEC transmitter may use an interpacket gap (IPG) 

larger than the 12-cycle minimum, preventing the transmitter from reaching 100% of line bandwidth. 


The following options maximize the bandwidth utilized by the Ethernet controller. 

• If multiple Tx queue operation is not required, use single Tx queue operation (thus eliminating the 

extra gap caused by switching queues) and use frames larger than 64 bytes (thus reducing the IPG 

as a portion of total bandwidth). 

• If multiple Tx queue operation is required, use priority arbitration by setting 

TCTRL[TXSCHED] = 0b01 and maximize the number of buffer descriptors (BDs) enabled per 




Revision History 

ring to minimize switching between rings. Also, minimize use of small frames, thus reducing IPG 

as a portion of total bandwidth. 

In silicon version 3.1.x, this erratum has been fixed for single-queue operation, with a single BD per frame. 

Under these conditions, the eTSEC adheres to the 12-cycle IPG, allowing 100% line bandwidth to be 

reached. 

The multiple-queue recommendations provided in the workaround still apply for silicon version 2.1.x. 

4 Revision History 

Table 4 provides a revision history for this application note. 

Rev. 

Number 

Table 4. Document Revision History 

Date Substantive Change(s) 

0 02/2012 Initial public release 


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