MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to ...

Software Impact of Errata Differences
3.2 Software Impact of Partial Errata Fixes in Rev 3.1.x
This section describes the software impact of the partial errata fixes in silicon version 3.1.x, including the
impact of leaving the silicon version 2.1.x workaround in software used with silicon version 3.1.x.
3.2.1 eTSEC 67—Fetches With Errors Not Flagged, May Cause Livelock or
False Halt
Software workaround:
a) Ensure all eTSEC BD and data addresses map to valid regions of memory.
b) Ensure EDIS[EBERRDIS] = 0.
The workaround stated above continues to function on silicon version 3.1.x.
3.2.2 eTSEC 84—Multiple BD Frame May Cause Hang
Software workaround:
Software must ensure that the ready bit of the first BD in a multiple TxBD frame is not set until
after the remaining BDs of the frame are set ready.
The workaround stated above has the same behavior on silicon versions 2.1.x and 3.1.x. As a result of this
partial fix, violating this programming guideline in systems with multiple BD rings will trigger an
underrun error, and will not hang the Ethernet controller. Violating the programming guideline Single
TxBD ring operation may still cause the Ethernet controller to hang.
3.2.3 DMA 1-DMA-DACK Bus Timing Violation When Operating in
External DMA Master Mode
Due to erratum DMA 1 on silicon version 2.1.x, in external DMA master mode, the DMA_DACK signal
must be held for 6 CCB_clocks instead of three.
In silicon version 3.1.x this erratum has been fixed except if the CCB Clock PLL Ratio is configured to
either 9:1 or 20:1 setting.
3.2.4 eTSEC 93—Transmit Fails to Utilize 100% of Line Bandwidth
Due to erratum eTSEC93 on silicon version 2.1.x, the eTSEC transmitter may use an interpacket gap (IPG)
larger than the 12-cycle minimum, preventing the transmitter from reaching 100% of line bandwidth.
Software workaround:
The following options maximize the bandwidth utilized by the Ethernet controller.
• If multiple Tx queue operation is not required, use single Tx queue operation (thus eliminating the
extra gap caused by switching queues) and use frames larger than 64 bytes (thus reducing the IPG
as a portion of total bandwidth).
• If multiple Tx queue operation is required, use priority arbitration by setting
TCTRL[TXSCHED] = 0b01 and maximize the number of buffer descriptors (BDs) enabled per
MPC8548 PowerQUICC III Silicon Changes from Version 2.1.x to Version 3.1.x, Rev. 0
16 Freescale Semiconductor