PXS30 Microcontroller Data Sheet - Freescale Semiconductor

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Introduction 1.5.26 Non-maskable interrupt (NMI) The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions. 1.5.27 System Status and Configuration Module (SSCM) The SSCM on the PXS30 features the following: • System configuration and status • Debug port status and debug port enable • Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word • Sets up the MMU to allow user boot code to execute as either Classic PowerPC Book E code (default) or as Freescale VLE code out of flash • Supports serial bootloading of either Classic PowerPC Book E code (default) or Freescale VLE code • Detection of user boot code • Automatic switch to serial boot mode if internal flash is blank or invalid 1.5.28 Nexus Development Interface (NDI) 18 • Per IEEE-ISTO 5001-2008 • Real-time development support for Power Architecture core through Nexus class 3 (some class 4 support) • Nexus support to snoop system SRAM traffic • Data trace of FlexRay accesses • Read and write access • Configured via the IEEE 1149.1 (JTAG) port • High bandwidth mode for fast message transmission • Reduced bandwidth mode for reduced pin usage 1.5.29 IEEE 1149.1 JTAG controller (JTAGC) • IEEE 1149.1-2001 Test Access Port (TAP) interface • JCOMP input that provides the ability to share the TAP —selectable modes of operation include JTAGC/debug or normal system operation • 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions • 5-bit instruction register that supports additional public instructions • Three test data registers: — Bypass register — Boundary scan register — Device identification register • TAP controller state machine that controls the operation of the data registers, instruction register, and associated circuitry PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor
2 Package pinouts and signal descriptions 2.1 Package pinouts PXS30 Microcontroller Data Sheet, Rev. 1 Package pinouts and signal descriptions Figure 2 shows the PXS30 in the 257 MAPBGA package. Figure 3 through Figure 6 show the PXS30 in the 473 MAPBGA package. A VSS_ HV_IO B VSS_ HV_IO C VDD_ HV_IO D nexus MDO [2] E nexus MDO [0] F nexus MDO[6] G nexus MDO [4] H nexus MDO [10] J nexus MCKO K nexus MSEO_ B[0] L nexus EVTO_B M VDD_ HV_ OSC N XTALIN P VSS_ HV_ OSC R XTAL OUT T VSS_ HV_IO U VSS_ HV_IO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS_ HV_IO VSS_ HV_IO nexus MDO [15] nexus MDO [3] nexus MDO [1] nexus MDO [11] VDD_ HV_IO VSS_ HV_IO nexus MDO[8] nexus MSEO_ B[1] nexus EVTI_B VDD_ HV_IO VSS_ HV_IO RESET FCCU_ F[0] VDD_ HV_IO VSS_ HV_IO VDD_ HV_IO mc_cgl clk_out VSS_ HV_IO can1 RXD flexray CA_RX dspi1 SOUT dspi0 SCK dspi0 CS0 dspi2 CS0 nexus RDY_B dspi2 SCK dspi1 CS2 dspi0 CS3 dspi0 CS2 VSS_HV _IO dspi2 SOUT dspi2 SIN nexus MDO[5] can1 TXD FCCU_ F[1] dspi0 SOUT NMI dspi1 SIN dspi1 SCK dspi1 CS0 dspi2 CS2 dspi0 SIN nexus MDO [13] nexus MDO [12] VSS_ LV_PLL VDD_ LV_PLL dspi1 CS3 adc3 AN[0] adc3 AN[1] nexus MDO[7] nexus MDO [14] flexray CB_RX RESERV ED etimer1 ETC[1] adc2 AN[0] adc3 AN[3] adc3 AN[2] nexus MDO[9] dspi2 CS1 etimer0 ETC[0] etimer0 ETC[5] VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR etimer1 ETC[2] adc2 AN[3] adc2 AN[2] adc2 AN[1] flexray CB_TX flexray CB_TR_ EN etimer0 ETC[1] etimer0 ETC[4] VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR adc0 AN[0] VDD_ HV_ ADR_13 VSS_ HV_ ADR_13 adc2_ adc3 AN[11] flexray CA_TR_ EN flexray CA_TX etimer0 ETC[2] VDD_ HV_FLA VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR etimer1 ETC[3] adc2_ adc3 AN[14] adc2_ adc3 AN[13] adc2_ adc3 AN[12] VDD_ HV_IO VSS_ HV_IO etimer0 ETC[3] VSS_ HV_FLA VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VSS_ HV_IO VDD_ HV_ ADR_02 VSS_ HV_ ADR_02 VDD_ HV_ ADV Figure 2. PXS30 257 MAPBGA pinout (top view) Freescale Semiconductor Preliminary—Subject to Change Without Notice 19 fec RXD[2] fec RXD[3] JCOMP fec TXD[2] VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR VDD_ HV_IO adc0 AN[2] adc0 AN[1] VSS_ HV_ ADV fec RX_ CLK fec RX_ER fec CRS fec TXD[1] VDD_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VSS_ LV_ COR VDD_ LV_ COR adc0_ adc1 AN[14] adc0_ adc1 AN[13] adc0_ adc1 AN[12] adc0_ adc1 AN[11] fec RXD[0] fec RXD[1] fec TXD[0] fec RX_DV VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR VDD_ LV_ COR etimer1 ETC[4] adc1 AN[1] adc1 AN[0] VREG_ INT_EN ABLE fec MDIO fec TX_ER fec COL fec MDC etimer1 ETC[5] VREG_C TRL adc1 AN[2] RESET_ SUP fec TX_EN fec TX_ CLK can0 RXD VDD_ HV_PDI pdi LINE_V mc_cgl clk_out pdi DATA [9] pdi DATA [12] pdi DATA [14] flexpwm 0 X[2] VDD_HV _DRAM_ VREF flexpwm 0 B[2] flexpwm 0 B[3] VDD_ HV_IO lin0 TXD lin0 RXD VDD_HV _PMU fec TXD[3] can0 TXD VSS_ HV_PDI VSS_ HV_IO pdi DATA [2] pdi DATA [6] pdi DATA [10] pdi DATA [13] pdi DATA [15] flexpwm 0 X[3] TCK VSS_ HV_IO VDD_ HV_IO pdi DATA [5] pdi DATA [0] pdi DATA [3] pdi DATA [7] pdi DATA [11] VDD_ HV_ PDI VSS_ HV_ PDI flexpwm 0 A[1] flexpwm 0 B[1] TDI TMS flexpwm 0 A[2] flexpwm 0 A[3] VSS_ HV_IO etimer1 ETC[0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VSS_ HV_ PMU flexpwm 1 A[0] flexpwm 0 A[0] flexpwm 1 A[2] VDD_ HV_IO VSS_ HV_IO VSS_ HV_IO VSS_ HV_IO pdi CLOCK pdi DATA [1] pdi DATA [4] pdi DATA [8] A B C D E F pdi G FRAME_ V flexpwm 0 X[0] flexpwm 0 X[1] flexpwm 0 B[0] TDO flexpwm 1 A[1] flexpwm 1 B[0] flexpwm 1 B[1] flexpwm 1 B[2] VSS_ HV_IO VSS_ HV_IO H J K L M N P R T U
Page 1 and 2: Freescale Semiconductor Data Sheet:
Page 3 and 4: Modules Analog-to-Digital Converter
Page 5 and 6: PXS30 Block Diagram PMU SWT MCM STM
Page 7 and 8: PXS30 Microcontroller Data Sheet, R
Page 9 and 10: 1.5.6 Frequency-Modulated Phase-Loc
Page 11 and 12: • DDR 1 • DDR 2 (optional) •
Page 13 and 14: 1.5.16 FlexCAN • Thirty-two messa
Page 15 and 16: — External ADC input, taking into
Page 17: • Collection of test results •
Page 21 and 22: Figure 5. PXS30 473 MAPBGA pinout (
Page 23 and 24: Ball Number Table 3. 257 MAPBGA sup
Page 29 and 30: Ball Number Ball Name Table 7. 257
Page 31 and 32: Freescale Semiconductor Preliminary
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Freescale Semiconductor Preliminary
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15 V DD_HV_ADV SR ADC supply voltag
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3.4 Thermal characteristics Table 1
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See Section 6, Reference documents,
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3.8.2 PMC board schematic and compo
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3.11 Main oscillator electrical cha
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3.13 16 MHz RC oscillator electrica
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PXS30 Microcontroller Data Sheet, R
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3.15 Flash memory electrical charac
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3.16 SRAM memory electrical charact
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3.17.2 GP pads AC specifications No
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Table 38. Drive Current, V DD_HV_PD
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Table 42. PDI pads AC electrical sp
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— All inputs are tolerant up to t
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NOTES: 1 L H signifies low-to-high
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Table 55. Output drive current @ V
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3.21.1 Reset sequence duration PXS3
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Reset Sequence Trigger Reset Sequen
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3.21.4 Reset sequence—start condi
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3.21.4.3 external Reset via RESET P
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Table 61. DDR and DDR2 (DDR2-400) S
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NOTES: 1 fTCK =1/t TCK. f TCK needs
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Figure 38. Nexus output timing 3.22
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SS SCK Input (CPOL=0) SCK Input (CP
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SS SCK Input (CPOL=0) SCK Input (CP
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3.22.8 Fast ethernet interface Tabl
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3.22.8.3 MII async inputs signal ti
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No. Symbol Parameter 6 t COV CC D_C
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D_CLKOUT Input Bus Input Signal ipg
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SCL 1 SDA 3.22.11 LINFlex timing Th
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Figure 61. 257 MAPBGA mechanical da
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Figure 63. 473 MAPBGA package mecha
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5 Orderable parts Qualification sta
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PXS30 Microcontroller Data Sheet - Freescale Semiconductor

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