PXS30 Microcontroller Data Sheet - Freescale Semiconductor

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Introduction 4 Clocking Clock monitor unit (CMU) 1.3 Block diagram Figure 1 shows a top-level block diagram of the PXS30 device. 3 modules Clock output 2 modules Frequency-modulated phase-locked loop (FMPLL) 2 modules (system and auxiliary) IRCOSC – 16 MHz 1 XOSC 4 MHz – 40 MHz 1 Supply Power management unit (PMU) 1.2 V low-voltage detector (LVD12) 1.2 V high-voltage detector (HVD12) 2.7 V low-voltage detector (LVD27) Table 1. PXS30 Family Feature Set (continued) Features PXS3010 PXS3015 PXS3020 Debug Nexus Class 3+ (for cores and SRAM ports) Packages MAPBGA 257 pins 473 pins 473 pins Temperature Ambient See the T A recommended operating condition in the device data sheet NOTES: 1 Sphere of Replication. 2 Does not include Test or Shadow Flash memory space. 3 Available only on 473-pin package. 4 DDR available only on 473 package. Other modules available as follows: EBI or DDR on 473 package. EBI + PDI on 473 package. DDR + PDI on 473 package PDI only on 257 package. Yes PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice 1 1 4 Freescale Semiconductor
PXS30 Block Diagram PMU SWT MCM STM INTC eDMA PBRIDGE FCCU TSENS Crossbar Switch (XBAR) Memory Protection Unit (MPU) 4 x UART/LIN e200z7 SPE2 VLE MMU Cache EBI 3 x SPI 3 x I2 3 x I C 2 C Ethernet Redundancy Checker 2 MB Flash (ECC) 4 x CAN ADC – Analog-to-digital converter BAM – Boot assist module CAN – Controller area network controller CMU – Clock monitoring unit CRC – Cyclic redundancy check unit CTU – Cross triggering unit EBI – External bus interface ECC – Error correction code ECSM – Error correction status module eDMA – Enhanced direct memory access controller FCCU – Fault collection and control unit FEC – Fast Ethernet controller FMPLL – Frequency-modulated phase-locked loop I 2 C – Inter-integrated circuit controller IRCOSC – Internal RC oscillator INTC – Interrupt controller JTAG – Joint Test Action Group interface MC – Mode entry, clock, reset, & power modules Redundancy Checker 3 x eTIMER Debug JTAG Nexus FlexRay Redundancy Checker Figure 1. PXS30 block diagram PXS30 Microcontroller Data Sheet, Rev. 1 mDDR – Mobile double data rate dynamic RAM PBRIDGE – Peripheral I/O bridge PDI – Parallel data interface PIT – Periodic interrupt timer PMU – Power management unit PWM – Pulse width modulator module RC – Redundancy checker RTC – Real time clock SEMA4 – Semaphore unit SIUL – System integration unit Lite SPI – Serial peripheral interface controller SSCM – System status and configuration module STM – System timer module SWT – Software watchdog timer TSENS – Temperature sensor UART/LIN – Universal asynchronous receiver/transmitter/ local interconnect network XOSC – Crystal oscillator Introduction Freescale Semiconductor Preliminary—Subject to Change Without Notice 5 3 x PWM PDI 2 x CTU 4 x ADC e200z7 SPE2 VLE MMU Cache Crossbar Switch (XBAR) Memory Protection Unit (MPU) PMU SWT MCM STM INTC eDMA Redundancy Checker MDDR PBRIDGE 512 KB SRAM (ECC) Communications I/O System
Page 1 and 2: Freescale Semiconductor Data Sheet:
Page 3: Modules Analog-to-Digital Converter
Page 7 and 8: PXS30 Microcontroller Data Sheet, R
Page 9 and 10: 1.5.6 Frequency-Modulated Phase-Loc
Page 11 and 12: • DDR 1 • DDR 2 (optional) •
Page 13 and 14: 1.5.16 FlexCAN • Thirty-two messa
Page 15 and 16: — External ADC input, taking into
Page 17 and 18: • Collection of test results •
Page 19 and 20: 2 Package pinouts and signal descri
Page 21 and 22: Figure 5. PXS30 473 MAPBGA pinout (
Page 23 and 24: Ball Number Table 3. 257 MAPBGA sup
Page 29 and 30: Ball Number Ball Name Table 7. 257
Page 31 and 32: Freescale Semiconductor Preliminary
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Freescale Semiconductor Preliminary
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15 V DD_HV_ADV SR ADC supply voltag
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3.4 Thermal characteristics Table 1
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See Section 6, Reference documents,
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3.8.2 PMC board schematic and compo
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3.11 Main oscillator electrical cha
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3.13 16 MHz RC oscillator electrica
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PXS30 Microcontroller Data Sheet, R
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3.15 Flash memory electrical charac
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3.16 SRAM memory electrical charact
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3.17.2 GP pads AC specifications No
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Table 38. Drive Current, V DD_HV_PD
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Table 42. PDI pads AC electrical sp
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— All inputs are tolerant up to t
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NOTES: 1 L H signifies low-to-high
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Table 55. Output drive current @ V
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3.21.1 Reset sequence duration PXS3
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Reset Sequence Trigger Reset Sequen
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3.21.4 Reset sequence—start condi
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3.21.4.3 external Reset via RESET P
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Table 61. DDR and DDR2 (DDR2-400) S
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NOTES: 1 fTCK =1/t TCK. f TCK needs
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Figure 38. Nexus output timing 3.22
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SS SCK Input (CPOL=0) SCK Input (CP
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SS SCK Input (CPOL=0) SCK Input (CP
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3.22.8 Fast ethernet interface Tabl
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3.22.8.3 MII async inputs signal ti
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No. Symbol Parameter 6 t COV CC D_C
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D_CLKOUT Input Bus Input Signal ipg
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SCL 1 SDA 3.22.11 LINFlex timing Th
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Figure 61. 257 MAPBGA mechanical da
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Figure 63. 473 MAPBGA package mecha
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5 Orderable parts Qualification sta
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PXS30 Microcontroller Data Sheet - Freescale Semiconductor

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