PXS30 Microcontroller Data Sheet - Freescale Semiconductor
PXS30 Microcontroller Data Sheet - Freescale Semiconductor
PXS30 Microcontroller Data Sheet - Freescale Semiconductor
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
Package pinouts and signal descriptions<br />
20<br />
A<br />
B<br />
C<br />
D<br />
E<br />
F<br />
G<br />
H<br />
J<br />
K<br />
L<br />
M<br />
N<br />
P<br />
R<br />
T<br />
U<br />
V<br />
1 2 3 4 5 6 7 8 9 10 11 12<br />
VSS_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
VDD_<br />
HV_IO<br />
nexus<br />
MDO[1]<br />
nexus<br />
MDO[0]<br />
nexus<br />
MDO[10]<br />
nexus<br />
MCKO<br />
nexus<br />
EVTO_B<br />
nexus<br />
RDY_B<br />
dspi0<br />
SCK<br />
dspi0<br />
CS0<br />
flexpwm0<br />
X[0]<br />
flexpwm0<br />
A[0]<br />
flexpwm0<br />
B[0]<br />
flexpwm0<br />
X[2]<br />
flexpwm0<br />
B[3]<br />
flexpwm1<br />
B[0]<br />
VDD_<br />
HV_OSC<br />
W XTALIN<br />
Y<br />
VSS_<br />
HV_OSC<br />
AA XTALOUT<br />
AB<br />
AC<br />
VSS_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
nexus<br />
MDO[15]<br />
nexus<br />
MDO[3]<br />
nexus<br />
MDO[2]<br />
nexus<br />
MDO[11]<br />
VDD_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
nexus<br />
MDO[13]<br />
dspi1<br />
CS0<br />
dspi2<br />
CS2<br />
VDD_<br />
HV_IO<br />
VDD_<br />
HV_IO<br />
mc_cgl<br />
clk_out<br />
VSS_<br />
HV_IO<br />
can1<br />
RXD<br />
flexray<br />
CA_RX<br />
nexus<br />
MDO[6]<br />
nexus<br />
MDO[8]<br />
nexus<br />
MSEO_B[0]<br />
nexus<br />
MDO[5]<br />
can1<br />
TXD<br />
FCCU_<br />
F[1]<br />
dspi0<br />
SOUT<br />
NMI<br />
nexus<br />
MDO[4]<br />
nexus<br />
MSEO_B[1]<br />
nexus<br />
EVTI_B<br />
nexus<br />
MDO[7]<br />
nexus<br />
MDO[14]<br />
flexray<br />
CB_RX<br />
RESERVED<br />
nexus<br />
MDO[9]<br />
dspi2<br />
CS1<br />
etimer0<br />
ETC[4]<br />
etimer0<br />
ETC[5]<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
flexray<br />
CB_TX<br />
flexray<br />
CB_TR_EN<br />
etimer0<br />
ETC[1]<br />
etimer0<br />
ETC[0]<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
flexray<br />
CA_TR_EN<br />
flexray<br />
CA_TX<br />
etimer0<br />
ETC[2]<br />
VDD_<br />
HV_IO<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
Figure 3. <strong>PXS30</strong> 473 MAPBGA pinout (northwest, viewed from above)<br />
VSS_<br />
HV_IO<br />
flexpwm0<br />
B[1]<br />
flexpwm0<br />
X[3]<br />
flexpwm1<br />
A[0]<br />
flexpwm1<br />
B[1]<br />
VDD_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
RESET<br />
FCCU_<br />
F[0]<br />
VDD_<br />
HV_IO<br />
VSS_<br />
HV_IO<br />
nexus<br />
MDO[12]<br />
dspi1<br />
SCK<br />
dspi2<br />
CS0<br />
dspi0<br />
SIN<br />
flexpwm0<br />
X[1]<br />
flexpwm0<br />
A[2]<br />
flexpwm0<br />
A[1]<br />
flexpwm1<br />
A[1]<br />
flexpwm1<br />
A[2]<br />
flexpwm1<br />
B[2]<br />
dspi0<br />
CS3<br />
dspi0<br />
CS2<br />
VSS_<br />
HV_IO<br />
dspi2<br />
SOUT<br />
dspi2<br />
SIN<br />
dspi1<br />
SIN<br />
dspi1<br />
SOUT<br />
VSS_<br />
HV_IO<br />
VDD_<br />
HV_IO<br />
flexpwm0<br />
B[2]<br />
flexpwm0<br />
A[3]<br />
VSS_<br />
HV_IO<br />
VDD_<br />
HV_IO<br />
dspi2<br />
SCK<br />
dspi1<br />
CS2<br />
VSS_<br />
LV_PLL<br />
VDD_<br />
LV_PLL<br />
dspi1<br />
CS3<br />
flexpwm1<br />
X[2]<br />
flexpwm1<br />
A[3]<br />
flexpwm1<br />
X[0]<br />
flexpwm1<br />
X[1]<br />
flexpwm1<br />
X[3]<br />
flexpwm1<br />
B[3]<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
adc3<br />
AN[0]<br />
adc3<br />
AN[1]<br />
adc3<br />
AN[2]<br />
adc3<br />
AN[3]<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
adc2_adc3<br />
AN[11]<br />
adc2_adc3<br />
AN[12]<br />
adc2_adc3<br />
AN[13]<br />
VDD_HV_<br />
ADR_23<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
adc2_adc3<br />
AN[14]<br />
adc2<br />
AN[0]<br />
adc2<br />
AN[1]<br />
VSS_HV_<br />
ADR_23<br />
Figure 4. <strong>PXS30</strong> 473 MAPBGA pinout (southwest, viewed from above)<br />
<strong>PXS30</strong> <strong>Microcontroller</strong> <strong>Data</strong> <strong>Sheet</strong>, Rev. 1<br />
fec<br />
RX_DV<br />
fec<br />
RXD[3]<br />
etimer0<br />
ETC[3]<br />
VSS_<br />
HV_IO<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
etimer1<br />
ETC[1]<br />
VDD_<br />
HV_ADV<br />
Preliminary—Subject to Change Without Notice<br />
adc2<br />
AN[2]<br />
adc2<br />
AN[3]<br />
fec<br />
MDIO<br />
fec<br />
RX_ER<br />
fec<br />
TXD[2]<br />
JCOMP<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
etimer1<br />
ETC[2]<br />
VSS_<br />
HV_ADV<br />
adc0<br />
AN[0]<br />
adc0<br />
AN[1]<br />
fec<br />
TX_CLK<br />
fec<br />
TXD[0]<br />
fec<br />
TXD[1]<br />
VSS_<br />
HV_IO<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
etimer1<br />
ETC[3]<br />
adc0<br />
AN[2]<br />
adc0<br />
AN[4]<br />
adc0<br />
AN[3]<br />
fec<br />
TX_EN<br />
fec<br />
RXD[0]<br />
fec<br />
CRS<br />
VSS_<br />
HV_FLA<br />
VDD_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VSS_<br />
LV_COR<br />
VDD_<br />
LV_COR<br />
VSS_<br />
HV_IO<br />
adc0<br />
AN[5]<br />
adc0<br />
AN[6]<br />
VDD_<br />
HV_ADR_0<br />
1 2 3 4 5 6 7 8 9 10 11 12<br />
<strong>Freescale</strong> <strong>Semiconductor</strong>
Change language