BlueSpec - Computation Structures Group - MIT

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A FIFO problem Immediate solution (Bluespec) Invent “wires” Wires similar to registers, but: Registers: Read “early” in clock cycle, written at end Wires: Written first, read later Value goes away at end of cycle 44
A FIFO problem Immediate solution (Bluespec) New primitive: no great upheaval to language Methods set wires; an internal rule makes the appropriate state change Allows the “problem” to be overcome by enhancing the FIFO’s design 45
Page 1 and 2: or Arvind goes commercial Joe Stoy,
Page 3 and 4: Servers Storage Arrays Network evol
Page 5 and 6: Delivering Efficient switch fabrics
Page 7 and 8: What is BlueSpec A language for har
Page 9 and 10: The Bluespec team Rishiyur Nikhil,
Page 11 and 12: Bluespec use at Sandburst HIBEAM ch
Page 13: Bluespec, Inc. background Research@
Page 16 and 17: Evolution of HDLs (Hardware Descrip
Page 18 and 19: Bluespec SystemVerilog A one slide
Page 20 and 21: One-at-a-time intuitions Untimed ru
Page 22 and 23: Two mutually exclusive rules (Later
Page 24 and 25: Practical Rule Composition Rules HW
Page 26 and 27: ule r1 (c1); x
Page 28 and 29: Bluespec SystemVerilog A one-slide
Page 30 and 31: Multiplier Example module mkTest ()
Page 32 and 33: ESL_MODULE (mkTest, ESL_EMPTY) { es
Page 34 and 35: Concern: the “learning curve” H
Page 36 and 37: Which one is correct? cond0 cond1 c
Page 38 and 39: Now, let’s make a small change: a
Page 40 and 41: Changing the Verilog design cond0 c
Page 42 and 43: So how does Arvind fit into this? B
Page 46 and 47: A FIFO problem Immediate solution (
Page 48 and 49: A Final Concern Has Arvind’s fame
Page 50 and 51: c:\users\stoy>finger arvind@mit.edu

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