Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
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<strong>Latency</strong> <strong>Insensitive</strong> BRAM<br />
• Memories are usually external<br />
to Bluespec<br />
– Generated RAMs<br />
– External RAMs<br />
• BRAM<br />
– Synchronous, Dual-ported<br />
SRAM<br />
– Primitive FPGA component<br />
• Wrapp<strong>in</strong>g a Pipel<strong>in</strong>ed BRAM<br />
– Keep an <strong>in</strong>ternal counter of <strong>in</strong>flight<br />
requests<br />
– Allow requests if room <strong>in</strong> the<br />
response buffer<br />
– To ma<strong>in</strong>ta<strong>in</strong> throughput, buffer<br />
must be as large as latency<br />
rdy en<br />
reqCnt<br />
rdy en<br />
reqIn<br />
Addr/Data<br />
outQ<br />
respOut<br />
BRAM<br />
2007-08-27 10<br />
req<br />
resp<br />
RAM latency=4
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