Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
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<strong>Latency</strong> <strong>Insensitive</strong> Bus<br />
• Burst transfer<br />
– Provide space to buffer the<br />
entire data of the transaction<br />
• Bus errors<br />
– Can’t allow bus <strong>in</strong>put to<br />
immediately escape to module<br />
• Fixed latency response times<br />
– Strict <strong>in</strong>put – compute – output<br />
method/rule order<strong>in</strong>g<br />
– Requires RWires<br />
• Same pr<strong>in</strong>ciples apply<br />
– Transaction start requires all<br />
<strong>in</strong>puts<br />
– Sufficient buffer<strong>in</strong>g for output<br />
– Transaction complete asserts<br />
all outputs valid<br />
2007-08-27 14
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