Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
Latency Insensitive Design in a Latency Sensitive World - MIT
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<strong>Latency</strong> Sensitivity<br />
• May require less logic<br />
– But sav<strong>in</strong>gs is m<strong>in</strong>imal<br />
• Many modules/Implementers<br />
– <strong>Design</strong>ers make undocumented tim<strong>in</strong>g<br />
assumptions<br />
– Do the assumptions of one effect the other?<br />
– When are these assumptions exposed?<br />
• Modular ref<strong>in</strong>ement<br />
– Major implementation ga<strong>in</strong>s possible<br />
– Does ref<strong>in</strong>ement affect design correctness?<br />
2007-08-27 2