ESSI Programming

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ESSI Registers Bit No. Bit Abbr. Value Function 21-19 WL[2:0] 22 SSC1 000 001 010 011 100 101 11x 0 1 Word Length Control 8 bits per word 12 bits per word 16 bits per word 24 bits per word 32 bits per word (valid in the first 24 bits) 32 bits per word (valid in the last 24 bits) Reserved Select SC1 as TX0 active - Valid only in synchronous mode with transmitter 2 disabled (see Table 1-2) SC1 is Flag 1 23 - Reserved bit to be written with 0 Bit No. Bit Abbr. Value Function 0 OF0 1 OF1 2 SCD0 3 SCD1 4 SCD2 - - 0 1 0 1 0 1 Table 1-5: Control Register A (CRA) SC1 is TX0 active - Valid only if SC1 is configured as an input; drives an external buffer for the transmitter 0 Table 1-6: Control Register B (CRB) Serial Output Flag 0 - Valid only in synchronous mode with transmitter 1 disabled and SC0 configured as an output (see Table 1-1) Data written to OF0 is seen on the SC0 pin Serial Output Flag 1 - Valid only in synchronous mode with transmitter 2 disabled and SC1 configured as an output (see Table 1-2) Data written to OF1 is seen on the SC1 pin Serial Control Direction 0 - Not valid when transmitter 1 is enabled (see Table 1-1) SC0 is an input SC0 is an output Serial Control Direction 1 - Not valid when transmitter 2 is enabled (see Table 1-2) SC1 is an input SC1 is an output Serial Control Direction 2 (see Table 1-3) SC2 is an input SC2 is an output Motorola DSP56300 ESSI Programming 6
Bit No. Bit Abbr. Value Function 5 SCKD 6 SHFD 8-7 FSL[1:0] 0 1 0 1 00 01 Clock Source Direction (see Table 1-4) SCK is input, clock SCK is output, clock Shift Direction Shift MSB first Shift LSB first Frame Sync Length Receive Transmit Word length Word length Word length Bit length 10 Bit length Bit length 11 Bit length Word length 9 FSR Frame Sync Relative Timing - Only valid with word length frame syncs 0 Frame sync begins with first bit of data word 1 Frame sync begins one bit before first bit of data word 10 FSP Frame Sync Polarity 0 Frame sync polarity is positive 1 Frame sync polarity is negative 11 CKP Clock Polarity ESSI Registers 0 Data and frame sync are clocked out on the rising edge of the transmit clock and latched in on the falling edge of the receive clock 1 Data and frame sync are clocked out on the falling edge of the transmit clock and latched in on the rising edge of the receive clock 12 SYN Synchronous/Asynchronous 0 Asynchronous mode 1 Synchronous mode 13 MOD ESSI Mode Select 0 1 Table 1-6: Control Register B (CRB) (Continued) Normal mode Network mode 14 TE2 Transmit 2 Enable - Valid only in synchronous mode 0 Transmit 2 disabled 1 Transmit 2 enabled Motorola ESSI Architecture 7
Page 1 and 2: MOTOROLA Semiconductor Application
Page 3 and 4: 1.1 ESSI Pins Figure 1-2 depicts th
Page 5: ESSI Registers ¥ Receive Slot Mask
Page 9 and 10: Bit No. Bit Abbr. Value Function Ta
Page 11 and 12: Part 2 ESSI Programming Transfer Ch
Page 13 and 14: 2.2 Synchronization Signals Synchro
Page 15 and 16: Operation Modes Word length frame s
Page 17 and 18: Operation Modes Some applications d
Page 19 and 20: Programming Control Registers ;----
Page 21 and 22: movep #$3F,x:M_PCRC ;Enable ESSI0 m
Page 23 and 24: Transfer Methods ¥ Transmit Last S
Page 25 and 26: 2.7 References 1. DSP56300 Family M
Page 27 and 28: NOTES: References Motorola DSP56300

ESSI Programming

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