Power Management - 6-Channel DMX Dimmer - AN2302 - Farnell

Application Note Abstract
Power Management - 6-Channel DMX Dimmer
AN2302
Author: Petro Kobluk
Associated Project: Yes
Associated Part Family: CY8C27443
GET FREE SAMPLES HERE
Software Version: PSoC Designer 4.2
Associated Application Notes: None
Basic principles of 6-Channel DMX Dimmer operation are described in this Application Note. A DMX dimmer can be used to
control the brightness of remote lighting in theaters, discos, and concert halls. The device is controlled via a DMX interface.
The structure, device function algorithm, interconnection circuits, DMX Protocol, and fundamental design aspects based on the
PSoC® device are considered.
Introduction
Nowadays computer-controlled equipment techniques,
consoles, and control panels are used to control effects
and stage lighting in theatres, discos, concert halls, etc.
The DMX Dimmer is used to convert the device input
signal into an analog representation of lamp brightness
(power).
Table 1. 6-Channel DMX Dimmer Characteristics
Number of Channels 6
Lamp Power Depending on TRIAC Used
Power Supply DC 5V, 100 mA
AC Synchronization AC 110-220V, 47-63 Hz, Automatic Turning
Address Range From 1 to 512
Service Features DMX Bus Sleep-Mode Support
DMX Protocol
DMX protocol was established by the United States
Institute for Theatre Technology (USITT) in 1986. This
protocol represents standard interface for data
communication between devices that are used for lighting.
In 1990, revisions were made and now the protocol is
known as USITT DMX512.
The DMX protocol uses the RS485 standard, which
defines electrical interface, voltage, and current.
This standard supports receiver and transmitter “ground”
connection to the cable core screen in order to lower the
influence of external noise and improve electrical safety.
The DMX Dimmer has the following characteristics (see
Table 1).
But the values of transmitter and receiver “ground” line
voltage can be different, which causes current to pass
through the cable screen. If the value of this current is too
great, the DMX cable and the circuit can be destroyed.
In order to correctly work devices that use DMX, to control
the interface, and also improve usage safety, it is
necessary to implement galvanic isolation on the DMX
receiver devices.
The DMX data stream is passed in the form of a burst that
is repeated continually. This data burst consists of the
synchro preamble that informs the receiver when it starts.
August 25, 2005 Document No. 001-31164 Rev. ** 1
[+] Feedback

This stream contains the values of each channel from 1 to
512, or less (see Figure 1, Table 2). The bit rate in the
DMX protocol is 250 kB. So, the duration of every bit is 4
µs. The number of channels passed is not fixed, but is
limited by the standard, which is from 24 to 512.
Figure 1. Structure of a DMX512 Signal
AN2302
If the information is given over all 512 channels, then the
maximum frequency that the information is updated is at
44,115 Hz. The maximum frequency that the information is
transmitted can be 836 Hz, which corresponds to
24 channels. Upon a long signal delay (more than 1s), the
device can enter DMX sleep mode.
1 2 3 6 7
9
Table 2. Data Stream Description and Duration
Item Description Duration
1 Space for Break (Reset) Min. 88 µs
2 Mark After Break (MAB) 8 µs – 1s
3 Slot Time 44 µs
4 Mark Time Between Slots 0 µs – 1s
5 Start Bit 4 µs
6 Least Significant Data Bit 4 µs
7 Most Significant Data Bit 4 µs
8 Stop Bit 4 µs
9 Mark Before Break (MBB) 0 µs – 1s
Start byte Channel 1 Channel 512
4 5
8
Lamp Power Phase Control
The TRIAC and lamp interconnection circuit example is
shown in Figure 2. This setup allows the control of lamp
brightness by varying the delay between AC line zerocrossing
and TRIAC ON events (see Figure 3). When
control impulses are sent to the TRIAC, it switches to ON
state. The TRIAC OFF state is automatically triggered
when the voltage falls to zero at the next zero-crossing
event.
Note The dimmer can be used with varying AC
frequencies; therefore, the AC line frequency needs to be
measured in order to provide correct dimmer operation
regardless of the actual power supply parameters.
August 25, 2005 Document No. 001-31164 Rev. ** 2
[+] Feedback

DMX Dimmer
110-220 V AC ~
AC mains
zero-crossing
Triac control
Voltage in Lamp
110-220 V AC~
Figure 2. TRIAC and Lamp Interconnection Circuit Example
TRIAC
The DMX Dimmer block diagram is shown in Figure 4. The
DMX Receiver receives data in accordance to the preset
address range and translates them in the TRIAC Control
Unit. When the value of the voltage is zero, the AC
Synchronizer (zero-crossing detector) generates the
lockout pulses that are used to delay initialization of the
counters.
DMX
AC
DMX Receiver
Synchronizer
from AC
TRIAC CONTROL
LAMP
Figure 3. Timetable of Lamp Power Phase Control
Delay 1 Delay 2 Delay 3
Figure 4. DMX Dimmer Block Diagram
Triac Control
Unit
t
t
t
t
AN2302
The TRIAC Control Unit has 6 independent counters.
When the lockout pulse enters from the AC Synchronizer,
the counters start their operation. If the counter reaches
the preset brightness compare value, the control impulse
for the TRIAC ON event is generated to turn the TRIAC
on.
Note The power supply of the AC Synchronizer and lamp
must be the same.
Channel 1
Channel 2
***
Channel 5
Channel 6
August 25, 2005 Document No. 001-31164 Rev. ** 3
[+] Feedback

DMX Dimmer Operation
Figure 5 illustrates the DMX Dimmer circuit.
J1
J2
DMX
J3
DC
(B)
R1
100k
(A)
2
1
110-220 AC
1
2
3
4
5
2
1
1
DV1 1n4148
R2
10k
R5
100k
DF04 832A
3
4 - +
D1
R3
51.1k
R6
10k
2
(C)
DV2
8V
(D)
VCC 8
RO 1
RE 2
DE 3
6
7
5
U4
DO/RI
DO/RI
GND DI
75LBC176A
4
VCC
C8
10u
C1
47u
2
+
OUT
3
-
V-
7
U1A
Gnd
LM311
V+ 8
4
1
VCC2
C9
0.1u
R8 2k
1
C10
0.1u
2
C11
0.1u
Figure 5. DMX Dimmer Circuit
1
2
U5 H11L1
U2 H11L1
C12
0.1u
In order to isolate the high voltage section from other parts
of the circuit, it is necessary to do galvanic isolation using
the optoisolator, U2 H11L1.
R7
1.47k
6
4
5
VCC
VCC
6
4
5
R15
270R
AN2302
August 25, 2005 Document No. 001-31164 Rev. ** 4
R4
270R
F100
DMX
1
U6
Vs
+Vout
6
14
SYNCin SYNCout
8
2
0Vin
0Vout
5
DCP010505BP
SW1
S2
C13
10u
SW2
S1
VCC
U3
Vcc
28
TR6
R9 C2
SLP
1
2
3
4
P0[7]
P0[5]
P0[3]
P0[1]
P0[6]
P0[4]
P0[2]
P0[0]
27
26
25
24 F100 TR5
47R
R10
0.47u
C3
SW8
SW6
SW4
SW2
5
6
7
8
P2[7]
P2[5]
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
23
22
21
20
SW7
SW5
SW3
SW1
TR4
47R
R11
47R
0.47u
C4
0.47u
9
SMP Xres
19
TR3
R12 C5
SW9
TR6
TR4
TR2
10
11
12
13
P1[7]
P1[5]
P1[3]
P1[1]
P1[6]
P1[4]
P1[2]
P1[0]
18
17
16
15
DMX
TR5
TR3
TR1 TR2
47R
R13
0.47u
C6
14
Vss
CY8C27443_DIP28
TR1
47R
R14
0.47u
C7
SLP
SW9
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
C14
0.1u
SW3
S0
47R
VCC
U7 LP2950-5.0
3
IN OUT
1
GND
2
0.47u
C15
10u
C16
0.1u
VCC2
C17
0.1u
Zero-crossing detection is implemented using U1, a lowcost
LM311 comparator. At Point “A” (after the diode
bridge), the voltage is in the form of a fully-rectified
sinusoid (Figure 6).
Figure 6. Clocking Unit Voltages of Points A, B, C Relative to Point D
Point “A”
Point “B”
Point “C”
Comparator Out
8.7 V
8 V
AC Synchronize
Out t
t
t
t
t
8
7
6
5
4
3
2
1
Triacs
J4
[+] Feedback

The zener diode DV2 and capacitor C1 forms the 8V DC
level relative to point «D». Voltage is scaled down to 1.3V
by the voltage divider formed from R3 and R6. The 1.3V is
used as a reference for negative comparator input. In point
«В», voltage is in the form of a fully-rectified sinusoid.
Voltage is supplied on positive input of the comparator by
the voltage divider across R2 and R5. The comparator
detects zero-crossing events and transmits them via the
optocoupler, U2.
The complexity of zero-crossing detection is compensated
for by stable and reliable operation, noise-immunity, and
testing in many industrial applications, including
automated welding machines.
Figure 7. PSoC Internal User Module Configuration
AN2302
The DMX receiver operates from PSoC’s RX8 receiver
and Counter8 (Figure 7). The signal is supplied for the
RX8 receiver and Counter8 through the RS485 differential
receiver, U4 75LBC176A, and the optocoupler, U5. In order
to provide galvanic isolated power supply for the U4
receiver, the U6 DCP010505BP DC/DC converter and U7
low-drop LP2950-5.0 DC regulator are used.
The TRIAC control unit is built using PWM generators and
the output signal is differentiated using a first order RC
high pass filter.
August 25, 2005 Document No. 001-31164 Rev. ** 5
[+] Feedback

It is important to provide good heat sink for the TRIACS,
which are used to control the power lamp. This is why they
are placed outside the PCB.
CONTROL
CONTROL
R
1K1
Figure 8. TRIAC Interconnection Circuit
(a) Low Lamp Power, (b) High Lamp Power
R Db
1K
Db
1
2
AN2302
Figure 8 shows two different TRIAC circuits (depending on
lamp power, low or high). The TRIAC, with a built-in
optocoupler, is used for the galvanic isolation control
circuit. This isolates the circuit from the power circuits.
Diode Db provides differential network capacitor discharge.
TRIAC DRIVER
1
2
(a)
TRIAC DRIVER
MOT3061
SW1, SW2, and SW3 are used to set the address of the
device and enable DMX bus sleep mode. The maximum
number of channels specified by the DMX512 Protocol is
512. The starting channel address is set by 3 DIP
switches, described as follows:
SW1/1 – is the address MSB, bit 8,
SW2/4 – 7,
SW2/3 – 6,
SW2/2 – 5,
SW2/1 – 4,
SW3/4 – 3,
SW3/3 – 2,
SW3/2 – 1,
SW3/1 – is the address LSB, bit 0.
SW1/2 and SW1/3 – are reserved.
SW1/4 is used to set DMX bus sleep mode. If there is no
signal on the DMX line for more than 1s, (see the DMX
Protocol), sleep mode activates and all lamps are switched
off. If sleep mode is not enabled, the device continues to
power itself at the lamp’s last values of brightness (power).
6
4
(b)
S202T01
6
4
R
POWER TRIAC
~AC LINE
CS20-12io1
~AC LINE
The DMX receiver receives the signal on the RX8. The
Counter8 is used to detect the break signal, the duration of
which is at minimum 88 µs. The DMX line is sent on the
RX8 receiver and Counter8 simultaneously (see Figure 7).
The break signal is detected by triggering a counter
interrupt. The GPIO interrupt is used to reset Counter8.
The GPIO interrupt is activated from the same DMX line.
RX8 chooses the data bytes from the DMX bus, and
increments the software channel counter.
CMP comparator is used to generate zero-crossing
interrupts, because the GPIO interrupt resource is already
taken and PSoC has no dedicated flag registers to
determine which GPIO pin triggered the interrupt.
Program Operation
The data are received in real-time from the DMX line and
TRIAC control unit. That is why it is very important to
separate these functions. If one of these functions misses
its specified deadline, faulty operation can occur.
August 25, 2005 Document No. 001-31164 Rev. ** 6
[+] Feedback

Using the software PWM to control the TRIACS is not an
optimal solution. Program operation is based on
processing short interrupts. When there is no active
interrupt handling, the device is waiting but inactive. The
duration of the data burst, which is received by the RX8, is
only 44 µs.
Table 3. Interrupt Sources
AN2302
With the PSoC system clock (IMO) of 24 MHz, the data
burst takes 1056 cycles. The sum of the interrupt handler
execution times must be less than this time. Five sources
of interrupts are used (see Table 3). To minimize their
duration they are written in assembly.
# Source Type IMO Cycles (Maximum)
1 Counter8 Terminal Count 35
2 RX8 Receiver Full 284
3 GPIO Rising Edge 23
4 Analog Column1 Rising Edge 193
5 Sleep Timer Terminal Count 78
The PSoC initialization flowchart is shown in Figure 9.
Initialization consists of two functions. First, AC line
frequency calibration occurs and second, initialization of
variables and modules occurs. These variables are
necessary for device operation.
Initialization
bCount = 0
wFrequency = 0
M8C_EnableIntMask
(INT_MSK0,
INT_MSK0_ACOLUMN_1);
M8C_EnableGInt;
CMPPRG_1_Start
(CMPPRG_1_HIGHPOWER);
wFrequency == 0
-
Figure 9. PSoC Initialization Flowchart
M8C_DisableIntMask
(INT_MSK0,
INT_MSK0_ACOLUMN_1)
Counter8_WritePeriod(175)
CounterCLK = VC1
CounterENABLE = Row0Input2
VC2 = 1
VC3Divider =
CalibrationFrequency
(Counter8_bReadCounter())
+
bPower1 = 0
bPower2 = 0
bPower3 = 0
bPower4 = 0
bPower5 = 0
bPower6 = 0
bSl = 0
M8C_EnableIntMask
(INT_MSK0,
INT_MSK0_ACOLUMN_1)
Counter8_EnableInt()
Counter8_Start()
RX8_EnableInt()
M8C_EnableIntMask
(INT_MSK0,INT_MSK0_GPIO)
M8C_EnableIntMask(INT_MSK
0, INT_MSK0_SLEEP)
PWM8_1_EnableInt()
PWM8_2_EnableInt()
PWM8_3_EnableInt()
PWM8_4_EnableInt()
PWM8_5_EnableInt()
PWM8_6_EnableInt()
IDLE Loop
August 25, 2005 Document No. 001-31164 Rev. ** 7
[+] Feedback

AC line frequency calibration is carried out only when the
device is turned on and is intended to adjust TRIAC turnon
angle setting appropriately for the utilized line
frequency.
AC Line
Counter8
PWM8
Period
Figure 10. Calibration Procedure
16 AC Line Half Cycles
AN2302
There are 255 lamp brightness levels. The value of the
PWM generator period is set constant and equal to
256 clock pulses. The VC3 divider supplies the clock. The
duration of the PWM period must be equal to exactly ½ of
AC line period (Figure 10).
1
T= CountValue
2Fmains t
After Calibration
This is done by tuning the VC3 divider during the
calibration procedure. It operates in the following way:
Counter8 starts counting during 16 AC line zero-crossing
comparator interrupts (16 half cycles). The count value is
used for VC3 divider calculation in the
CalibrationFrequency() routine using the following
formulas:
CntValue
1
=
Cnt 2 ⋅ f
Clock
Equation 1
256 1
=
PWM Clock 2 ⋅ f
Equation 2
CntValue
256
=
Cnt PWM
VC =
3
Clock Clock
CntValue ⋅VC
256
cal
3
Equation 3
Equation 4
VC3 cal , the value during the calibration procedure, is set to
100 and f is the AC line frequency.
For increased measurement precision, the calibration
procedure integrates 16 half cycles of the AC line
frequency. For correct Counter8 and PWM8 during these
16 half cycles, the clock frequency is reduced by a factor
of 16 by setting VC2 = 16 instead of the normal value
VC2=1.
wFrequency is a flag that shows that calibration has
competed. Once the program starts, this flag is reset and
the AnalogColumn1 interrupts are enabled. The flag reset
is done in the master program by the AnalogColumn1
interrupt handler. After that, the values of the necessary
dividers are set and Counter8 settings are modified for use
as a break detector.
At the second part of PSoC initialization, the variables and
necessary modules for device initialization are carried out.
First, the variables, which contain the brightness of each
lamp, are reset. Next, the necessary interrupt permission
flags are set and two modules start: Counter8 and CMP.
When the break signal passes over the DMX line, the
Counter8 interrupt handler is brought in. The
wAddressCounter variable is reset and the RX8 is
restarted in the Counter8 interrupt handler (Figure 11).
Figure 11. Counter8 Interrupt Flowchart
Counter8 INTERRUPT
wAddressCounter RESET
RX8 RESET
August 25, 2005 Document No. 001-31164 Rev. ** 8
Return
t
t
[+] Feedback

The GPIO is used for the zeroing of Counter8 (this is in the
absence of an enable signal on the Counter8). See
Figure 12.
Figure 12. GPIO Interrupt Flowchart
GPIO INTERRUPT
Counter8 RESET
Return
The SleepTimer interrupt handler flowchart is shown in
Figure 13.
Figure 13. SleepTimer Interrupt Flowchart
SleepTimer INTERRUPT
PRT0DR[1] == 1
+
bSl == 0
+
bPower1 = 0;
bPower2 = 0;
bPower3 = 0;
bPower4 = 0;
bPower5 = 0;
bPower6 = 0;
Return
-
-
AN2302
Initialization of the variables that contain lamp brightness
value is done under the following conditions: DMX bus
sleep-mode support switched ON and interrupt handler is
not set from RX8 bSl flag during the one-second time-out
period.
The AnalogColumn1 interrupt handler from the comparator
bus consists of two functions. First the device relative to
the AC line frequency is calibrated and second, the PWMs
are initiated. The flowchart of the AnalogColumn1 interrupt
handler is shown in Figure 14. Once the wFrequancy flag
is cleared (calibration has not yet occurred),
incrementation of the bCount counter is done. When the
counter value is equal to zero, the Counter8 starts. When
the counter value is equal to 16, the Counter8 stops and
the calibration completion flag is set.
If calibration was done, the interrupt handler from the
comparator stops all PWMs and sets PulseWidth of all
PWMs according to preset lamp brightness (which is
saved in the bPower1-6 variables in main.c).
August 25, 2005 Document No. 001-31164 Rev. ** 9
[+] Feedback

Figure 14. AnalogColumn1 Interrupt Flowchart
+
Counter8 STOP
wFrequency = 1
bCount == 16
-
-
bCount ++
If the data byte enters from the DMX line, the RX8
interrupt handler is invoked (see Figure 15). It reads the
data and status bytes. If wCountAddress contains more
than 512 channels, or errors in the byte status are
detected (OverrunError, FramingError), the RX8 stops.
Counter8 is used to restart the RX8 interrupt handler. This
means that a new data burst has entered. On the other
hand (the value of address counter is correct and there are
no errors), the device address is formed in the wSwitch
variable and then compared with the value of the address
counter. If the address of any lamp matches the value of
the address counter, the data byte is put in the
corresponding variable. After the comparison, the address
counter is incremented.
The RX8 interrupt handler also sets the bSl flag, which
means the DMX bus is active. If the value of lamp
brightness is 255, the TRIACS will malfunction (because
voltage of the AC line frequency is not enough to support
the TRIAC ON state). Therefore, lamp brightness must be
no greater than 254. The difference between 254 and 255
is 0.02%, which is imperceptible to the human eye.
Return
Analog Column1 INTERRUPT
wFrequency == 0
PWM8_1 STOP
PWM8_2 STOP
PWM8_3 STOP
PWM8_4 STOP
PWM8_5 STOP
PWM8_6 STOP
PulseWidth1 = bPower1
PulseWidth2 = bPower2
PulseWidth3 = bPower3
PulseWidth4 = bPower4
PulseWidth5 = bPower5
PulseWidth6 = bPower6
PWM8_1 START
PWM8_2 START
PWM8_3 START
PWM8_4 START
PWM8_5 START
PWM8_6 START
AN2302
August 25, 2005 Document No. 001-31164 Rev. ** 10
-
bCount == 0
+
Counter8 START
bCount ++
+
In order to increase noise immunity (oscillations of electric
supply network), all PWMs stop when their counter value
is equal to zero. This triggers the TerminalCount interrupt
handler for each PWM. This technique eliminates phase
error accumulation caused by AC frequency measurement
errors.
[+] Feedback

Figure 15. RX8 Interrupt Flowchart
RX8 INTERRUPT
bStatus =RX8_bReadRxStatus
bData=RX8_bReadRxData
bSl=1
bData == 255
-
(FramingError ) |
(wAddressCounter >512) |
(OverrunError)
-
wSwitch = PRT2DR
wSwitch+1 = PRT1DR[7]
if(wAddressCounter =wSwitch+0)
bPower1=bData;
if(wAddressCounter =wSwitch+1)
bPower2=bData;
if(wAddressCounter =wSwitch+2)
bPower3=bData;
if(wAddressCounter =wSwitch+3)
bPower4=bData;
if(wAddressCounter =wSwitch+4)
bPower5=bData;
if(wAddressCounter =wSwitch+5)
bPower6=bData;
wAddress Counter ++
Return
+
+
bData=254
RX8 STOP
AN2302
August 25, 2005 Document No. 001-31164 Rev. ** 11
[+] Feedback

TRIAC Control, Synchronization
Signal Waveforms
Figure 16 shows the four waveforms collected.
AC line frequency
Signal on AC Synchronizer output (in Figure 5 it is
called “F100”)
Signal on PWM output
TRIAC control pulse
Figure 16. TRIAC Control and Synchronization Signal Waveforms
Figure 17. Board
AN2302
August 25, 2005 Document No. 001-31164 Rev. ** 12
[+] Feedback

Summary
The optimal structure for a multi-channel dimmer system
(more than 6 channels) is a two-chip design (Figure 18).
The DMX Protocol receiver can be implemented using the
low-cost, CY8C21xxx PSoC device family. The 16-channel
PWM generator can be built using the CY8C29xxx family
or even a software implemented multi-channel PWM
generator. In this case, the second chip can be from the
CY8C21xxx family as well.
OPTO
AC Zero -
Crossing
Detector
21 Family
DMX
Receiver
Data
Ready for
Next
Figure 18. 16-Channel DMX System
21 or 29 Family
Zero-Crossing Module
Frequency Calibration
PWM Control
Up to 16
TRIACS
Lamp 1
Lamp 16
AN2302
August 25, 2005 Document No. 001-31164 Rev. ** 13
[+] Feedback

About the Author
Name: Petro Kobluk
Title: Application Engineer
Background: Petro graduated from National
University “Lviv Polytechnic”
(Ukraine) in 2001 with a degree
specializing in computer
systems.
Contact: petro_kobluk@ukr.net
AN2302
In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation
number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions.
PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, and PSoC Express are trademarks
of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
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August 25, 2005 Document No. 001-31164 Rev. ** 14
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