Bridgeless PFC Boosts Low-Line Efficiency - Power Electronics

Bridgeless PFC Boosts
Low-Line Effi ciency
By Jon Mark Hancock,
Principal Engineer,
In neon Technologies, N.A.,
Milpitas, Calif.
A bridgeless input power
factor boost converter
o ers the potential for
higher e ciency to meet
increasing demands for
power savings, especially
in switch-mode powersupply
applications at
low-line voltages.
ide input-voltage range
power factor correction
(PFC) converters present
some of the most difficult
component challenges in acdc
power electronics. With an
input-voltage range that can extend
from 265 Vac to as low as 75 Vac,
the range of operating conditions is
relatively extreme with wide current
operating range and duty-cycle demands.
As energy costs soar, the
pressure is on to fi nd ways to improve
effi ciency in power supplies used for
applications such as telecommunications
and computing. One solution is
the bridgeless PFC technique.
Bridgeless boost PFC is a concept that
has been long on promise for many years,
but has not reached mainstream acceptance.
Issues with EMI, robustness and the complexity
of early confi gurations have stymied eff orts to
realize the bridgeless boost PFC converter’s potential.
Furthermore, improvements in components used in
standard PFC boost converters have resulted in effi ciency
gains that did not justify the extra cost and complexity of
the bridgeless confi guration. And while bridgeless PFC has
been viewed as a potentially useful technique to improve lowline
input effi ciency, it is not certain that is where the demand for
improvement lies today.
As discussed in many forums over the last two years, the specifi -
cation and evaluation of switch-mode power-supply (SMPS) systems
is changing in response to the industry’s desire to save energy in the real
Power Electronics Technology February 2008 14
www.powerelectronics.com
802PET20.indd 14 2/12/2008 9:36:58 AM

world. Traditionally, effi ciency has normally been specifi ed
at full load for high- and low-line ranges, but now a more
realistic approach is being widely adopted, looking at the
behavior of the system and its effi ciency in the range where
the SMPS usually operates.
VIN [1] Th is means that for redundant
power systems such as computing servers and telecom
power, it is now realized that effi ciency in the 10% to 50%
range must be considered along with full load behavior, as
shown in Fig. 1.
As a result, system manufacturers such as IBM are
changing the focus of how they specify and procure power.
Th is change has been driven by customers with limited abilities
to expand data centers because of power and cooling
capacity. While the best of contemporary
conventional PFC designs can just meet
such current voluntary standards as
Green Grid and ClimateSavers, more
stringent future requirements may force
designers to look for new solutions. A
bridgeless PFC input confi guration can
help support these requirements, although
it may require some rethinking
of design methodology and optimization
methods.
Conventional PFC
Versus Bridgeless
The well-known single-boost PFC
rectifi er confi guration shown in Fig. 2a
consists of a full-bridge rectifi er input,
which provides a rectified pulsating
half-sine waveform applied to a boost
converter consisting of switch S1, boost
inductor L1 and boost rectifier D1,
which charges a bulk rectifi er capacitor,
“bus cap.”
Fig. 2b shows the basic bridgeless
boost concept, patented in 1983. [2] Th is
variant shows a dual-winding inductor
on one core. With alternating halfsine
polarity on the ac line voltage, the
MOSFETs alternate between operating
as a low-frequency half-wave rectifi er
diode connecting the ac line voltage to
the bulk bus negative terminal. It also
operates as a high-frequency chopper
driving the respective boost inductor winding and boost
rectifi er diode.
Th is confi guration reduces the number of semiconductor
devices in the inductor charging-current path from three to
two, lowering conduction loss by about one diode-junction
voltage drop (V F ). Th e MOSFETs conduct as either a highfrequency
switch or a low-frequency half-wave rectifi er
operating on alternate ac half cycles. As a result, some of
the power losses normally handled by the ac bridge rectifi er
V IN
www.powerelectronics.com 15
Power Electronics Technology February 2008
Efficiency (%)
95
90
85
80
75
70
Latest SMPS
Proposed silver level
Proposed gold level
Typical SMPS
65
10 20 35 50 75 100
Load (% rated power-supply output)
Fig. 1. In some computing and telecom applications, power supplies
are now expected to meet targets for effi ciency in the 10% to 50%
load range, while still achieving high effi ciency at full load. [1]
Boost
inductor
(a) Conventional boost PFC configuration
L1a
L1b
Dual-winding
boost inductor
(b) Basic bridgeless boost PFC configuration
Boost rectifier
L1 IL D1
D
D1
I L1a
S1
S1 S2
Bus
cap
D2
I L1b
Vdc OUT
+
Load
Vdc OUT
Fig. 2. A comparison of the conventional single-boost PFC rectifi er confi gurations: The basic
bridgeless boost PFC confi guration employs a full-bridge rectifi er, inductor, power MOSFET
switch and bus capacitor (a). The conventional confi guration includes a dual-winding
inductor on a single core, along with two power MOSFET switches, diodes D1 and D2, and
an output capacitor (b).
Load
are now transferred to the power MOSFETs, potentially
resulting in higher junction temperatures, which aff ects
the overall MOSFET size.
Deterring the industry’s adoption of the bridgeless PFC
are several innate confi guration characteristics. Because
of the inductor confi guration and lack of a low-frequency
path to the output, there is a relatively high common-mode
switching voltage present at the bulk negative connection
and no low-frequency path to the ac input. Th is can result
in relatively high common-mode EMI because of the
802PET20.indd 15 2/12/2008 9:37:03 AM
I DC
I DC

charge and discharge of normal parasitic
capacitances associated with the converter’s
physical construction.
Sensing the input voltage and input current
usually require isolated circuits due to
the high-frequency potential between the
ac input and output ground reference. It
may even be necessary to use dual currentsense
transformers (for switch and inductor
current), while also applying rectifi ed
half-sine voltage sensing on the primary. [3]
Th is example makes no provision for precharging
the bulk capacitance or dealing
with surge stress encountered during cycle
skip or low-line to high-line jumps.
Hall Eff ect Current Sensing
A modifi ed version of this confi guration
was used to develop an experimental
high-effi ciency bridgeless PFC front end
in coordination with Isle Engineering,
an independent consulting company in
Ilmenau, Thuringia, Germany, up to a
maximum output power level of 1500 W. [4]
Fig. 3 shows the basic confi guration. Some
of the design issues for this bridgeless PFC
were addressed with specifi c techniques to
optimize effi ciency to the greatest extent
possible, with a target value of 99% at full
load. In practice, these eff orts made it possible
to realize about 98.8% effi ciency at full
output in the fi nished design.
First, input-voltage sensing was eliminated by using a
PFC controller based on single-cycle control, as pioneered
by Smedly and Cuk. [5] Th is does not require input-voltage
sensing and PFC controllers are available from vendors
that use this technique. [6] Th e LAH25 wideband Hall Eff ect
sensor with isolated data outputs accomplishes current
sensing on the ac primary aft er the bulk precharge diodes
D3 and D4. Th is component avoids the losses associated
with resistive sensing and eliminates the need for sensing
transformers in high-speed switching paths.
Th e boost rectifi er diodes are silicon carbide, merged
PiN Schottky types that combine the characteristics of
Schottky and p-n diodes with nearly negligible reverse
recovery charge (Q RR ) capacitive losses and low forward
drop. The switching MOSFETs were selected for lowenergy-specifi
ed output capacitance (C OSS ) to minimize
turn-on loss and are capable of near zero-voltage switching
turn-off with very low losses due to their output capacitance
nonlinearity. [7]
Th e control arrangements for this confi guration are
somewhat complex, and a zero-crossing detector and
driver-steering logic located aft er the PWM output of the
PFC controller steer the driver signal to either S1 or S2.
Th is depends on the ac-voltage input phase while driving
V IN
bridgeless pfc
the other MOSFET as a synchronous rectifi er. A fl yback
bias supply, using an integrated controller and FET, provides
±12 V for the PFC controller and Hall Eff ect sensor
module, which is part of the overall losses accounted for
in the effi ciency measurement.
Th is development was successful in demonstrating a
range of techniques to achieve quite high effi ciency in the
PFC front end, but it was limited to a high-line confi guration
due to the lack of conventional heatsinks, and suff ers
from the common-mode EMI issues of the original confi
guration. Derivations of another proposed confi guration
address these issues.
Half-Wave Design
A bridgeless half-wave rectifi ed dual boost PFC was
proposed by Barbi and Souza that used insulated-gate bipolar
transistors (IGBTs) with a nondissipative snubber to
reduce switching losses. [8] IGBTs lack the functional body
diode of MOSFETs, so diodes must accomplish input halfwave
rectifi cation (slow-recovery diodes are suffi cient).
A modifi cation of this design was adapted to MOSFETs,
removing the nondissipative snubbers and adding diodes
for bulk capacitor precharge (Fig. 4).
Diodes D5 and D6 are low-frequency half-wave rectifi ers,
www.powerelectronics.com 17
Power Electronics Technology February 2008
LAH25
ZCD
driver
logic
Isolated input current sense
using Hall Effect sensor
Dual-winding
boost inductor
L1a
L1b
Bridgeless boost PFC with bulk precharge, Hall current sense
D3
D1
I L1a
D4
D2
S1 S2
I L1b
Vdc OUT
Fig. 3. A bridgeless boost PFC with bulk precharge and a Hall current sensor realizes about
98.8% effi ciency at full output.
V IN
D3
D5
D6
D4
NTC
L1
L2
Current
sense
D1
I L1
D2
S1 S2
Bridgeless boost PFC with half-wave rectifier and bulk bus precharge
I L2
+
+
Load
Vdc OUT
Fig. 4. A bridgeless boost PFC with half-wave and bulk bus precharge removes the nondissipative
snubbers and adds diodes for bulk capacitor precharge.
802PET20.indd 17 2/12/2008 9:37:04 AM
Load
I DC
I DC

Losses (W)
40
30
20
10
bridgeless pfc
Conduction losses
Capacitive losses CP Series
CoolMOS CP 600 V Series
0
0 50 100
Spec RDS (m)
ON
150 200
(a) Loss minimal for 800 W, 130 kHz, 90 Vac
Fig. 5. MOSFET losses in the boost PFC vary with the power MOSFET R DSON as demonstrated with a PFC stage configured for 800-W output
(full load), switching at 130 kHz. For the case where input voltage is 90 Vac, conduction loss (shown in yellow) and switching loss (shown in
red) are balanced and minimized at an R DSON of 30 mΩ (a). When input voltage is raised to 208 Vac , lowest losses occur with higher R DSON ,
and reduced capacitive loss (b).
alternately making a low-frequency connection between the
ac line and the bulk negative connection. Diodes D3 and D4
provide the bulk precharge function during startup and in
SIP AD1 6/1/07 2:06 PM Page 1
cycle skip or brownout recovery. The configuration of D3,
D4, D5 and D6 forms a bridge and can be implemented
Losses (W)
0
0 50 100
Spec RDS (m)
ON
150 200
(b) Loss minimal for 800 W, 130 kHz, 208 Vac
with standard slow-recovery ac bridge rectifiers.
Chopper switches S1 and S2 drive inductors L1 and L2
on alternate line half cycles. This is a potential cost disadvantage
compared with the combined coupled-inductor
structure of the last example. However, by using separate
cores high-frequency excitation and heating occurs for each
inductor only during every other ac half cycle, providing
thermal benefits that reduce inductor size and cost. Some
half-wave rectification still occurs through the inductor
and the MOSFET body diode, shown in Fig. 4, because
they’re not the primary half-wave rectifier used for other
configurations.
The majority of current flows in diodes D5 and D6,
slow-recovery half-wave rectifiers. This has the effect of
reducing the power dissipation and maximum junction
temperature in the MOSFET switches, which lowers their
effective operating on-resistance (R DSON ). MOSFET R DSON
can double between room temperature and maximum
operating temperatures, so a lower junction temperature
lowers conduction losses.
In this configuration, current sense is at the same potential
as the output load return and controller ground,
allowing some flexibility in measurement technique and
including the use of conventional resistive in-line sensing.
Of course, resistive sensing increases the losses, but by
how much?
Let’s consider an example of a 1-kW output converter, assuming
a nominal efficiency (η) of 90% and a low-input-line
voltage of 90 Vac. Let’s assume that for the controller being
used, we need 26 mΩ to generate the required maximum
sense voltage. The peak input current is:
(Eq. 1)
Power Electronics Technology February 2008 18
www.powerelectronics.com
40
30
20
10
I
PK
POUT
×
=
η×
V
IN MIN
Conduction losses
Capacitive losses CP Series
CoolMOS CP 600 V Series
2
= 17. 64 A.
The sense resistor power dissipation is:
802PET20.indd 18 2/12/2008 9:37:06 AM

P
SENSE
2
IPK
= RSENSE
⎛ ⎞
⎜ ⎟ × = 4. 365 W. (Eq. 2)
⎝ 2 ⎠
This amounts to 0.5% efficiency loss at low line. However,
if normal operation at high line and cost are a greater concern,
at 208 Vac the total P SENSE loss is only 0.755 W, less than
0.1%. This may be a tolerable tradeoff. Note that eliminating
the extra diode drop of the conventional bridge diode even
at high line may save 5 W to 8 W.
Examining this bridgeless PFC configuration, it could
appear that the component count is double that of the conventional
PFC configuration in Fig. 2a. In reality, with the
same total MOSFET and boost rectifier silicon “budget” in
either configuration, a higher total efficiency can be achieved
with the bridgeless configuration. And considering the
targets shown in Fig. 1, achieving higher efficiency at the
lower power ranges is well served by splitting up the switch
and diode budget between the dual boost phases.
To understand why this is so, examine the selection of the
MOSFETs based on a conventional boost PFC that delivers
the lowest total losses at full load and low-line ac. An Excel
workbook was used to do this, with some assumptions translated
from the data sheet to the application (Fig. 5a).
Fig. 5 shows an 800-W output PFC application, with a
net input to output efficiency of 85%, which is used to factor
up the required input power. The switching frequency
bridgeless pfc
is 130 kHz, with an input voltage of either 90 Vac in Fig.
5a or 208 Vac in Fig. 5b. The x axis is the nominal R DSON
specification, but this is not used for calculation; instead,
the R DSON is normalized to 105°C for the calculation of
conduction losses.
Since turn-off losses can be made nearly negligible with
super-junction MOSFETs [7] , the focus for dynamic losses is
on C OSS discharge at turn-on, an unavoidable loss in hardswitching
circuits. With conventional diodes, this loss might
be nearly swamped out by the Q RR and C OSS of the boost
rectifier diode. With modern silicon carbide and even silicon
ultrafast diodes, the output capacitance of the MOSFETs can
play a dominant role in losses. [9]
Looking at Fig. 5a, the minimum of the loss curve occurs
for a specified R DSON of 25 mΩ to 30 mΩ. At this point, at
full load and low line, the conduction and switching losses
are balanced and minimized. This low resistance would take
two 75-mΩ TO-247 MOSFETs in parallel to achieve. This
may not be the best way to achieve efficiency, particularly
if we consider the bridgeless option. Those switching losses
due to C OSS capacitance will be there regardless of the load
current or line voltage.
Considering that the bridgeless option can save 5 W to 8
W or more in conduction losses, we can take that savings into
account in derating the conduction performance requirement
for the MOSFETs. Moving on the loss line to the right,
Take a look at our broad offering of quality
power modules and fi nd out why Bel is now
the preferred source for dc-dc converters.
Finally, you can get cost effective products
in industry standard form factors without
sacrifi cing performance. To learn more
about how Bel can help you power your
next system, visit us at www.belpower.com.
High Effi ciency Power Modules
www.belpower.com • 1-800-BELFUSE
Isolated Converters-Single & Dual Output
•1/16, 1/8, 1/4, 1/2 Bricks up to 120A
Bus Converters-4:1, 5:1, 6:1 Fixed Ratios
•1/16, 1/8, 1/4 Bricks up to 500W
VRMs-Solutions for most Microprocessors
•Up to 150A Output; Goldfi nger and TH
Non-Isolated POL Modules-Boost, Buck
and Inverting
•1A to 150A Output; Vertical Mount or SMT
power PE 4-30-07.indd 1 6/27/07 12:14:13 PM
www.powerelectronics.com 19
Power Electronics Technology February 2008
802PET20.indd 19 2/12/2008 9:37:08 AM

idgeless pfc
the losses increase as a function of conduction loss, so it’s
possible to move over to the right, where conduction losses
are up by 5 W to 7 W, and write that off due to the conduction
loss improvement of the bridgeless configuration.
Most importantly, shifting to a single 75-mΩ, instead of
a 25-mΩ to 30-mΩ MOSFET cuts C switching losses in
OSS
half. Therefore, switching loss reduction at all other load
ranges and line voltages will be significant. This is shown in
Fig. 5b for operation at full load at the SMPS normal operating
208-Vac input, where the optimum MOSFET choice
would appear to be around 100-mΩ. In fact, if you have that
so-called “optimum” conventional MOSFET of 25 mΩ to
30 mΩ for low-line performance in a conventional PFC
circuit, the total losses at full load are doubled for the
MOSFET, due to higher C switching loss when operating
OSS
at 208 Vac. The loss is even worse at 50% load and below.
PETech
References
1. Janick, J., “IBM Technology and Solutions,” IBM Power
and Cooling Symposium, October 2007, Raleigh, N.C.,
proceedings at www-03.ibm.com/procurement.
2. Mitchell, D.M., “AC-DC Converter Having an Improved
Power Factor,” U.S. Patent 4,412,277, Oct. 25, 1983.
3. Moriconi, U., “A Bridgeless PFC Configuration Based
CKE-PET on L4981 7-06 PFC 12/27/07 Controller,” 10:10 Application AM Page Note 1AN
1606,
REPLACEMENTS
FOR MANY
FUJI DIODES
AVAILABLE
1 kV to 300 kV
Fast Recovery
down to 35nS
Average Forward
Current up to
10 Amps
HVCA diodes are ideal for use
in high voltage power supplies
and multipliers found in
medical equipment and
instrumentation. They
are also well-suited for
aerospace, military,
automotive, down hole and
high temperature applications
and X-ray equipment used
for medical, dental,
industrial and
security purposes.
HVCA
P.O. Box 848, Farmingdale, NJ 07727
(732) 938-4499 (732) 938-4451 FAX
e-mail: info@hvca.com www.hvca.com
STMicroelectronics, November 2002.
4. Hancock, J., “Meeting the Challenge for Offline SMPS
Through Improved Semiconductor Current Density,”
IBM Power and Cooling Symposium, 2005, proceedings
at www-03.ibm.com/procurement.
5. Smith, K.M., Jr.; Lai, Z.; and Smedley, K.M., “A New PWM
Controller with One-Cycle response,” IEEE Transactions
on Power Electronics, Volume 14, Issue 1, January 1999,
pp. 142-150.
6. Lu, B.; Brown, R.; and Soldano, M., “Bridgeless PFC
Implementation Using One Cycle Control Technique,”
IEEE Applied Power Electronics Conference (APEC) 2005
proceedings, pp. 812-817.
7. Bjoerk, F.; Hancock, J.; and Deboy, G., “CoolMOS CP:
How to Make Most Beneficial Use of the Latest Generation
of Super Junction Technology Devices,” AN-CoolMOS
CP-01, www.infineon.com.
8. Souza, A.F., and Barbi, I., “High Power Factor Rectifier
with Reduced Conduction and Commutation Losses,’’
International Telecommunication Energy Conference
(INTELEC) proceedings, June 1999, session 8, paper 1.
9. Lu, B.; Dong, W.; Shao, Q.; and Lee, F., “Performance
Evaluation of CoolMOS and SiC Diode for Single Phase
Power Factor Correction Applications,” IEEE APEC 2003
proceedings.
Minisens
FHS Current
transducer
Minisens is taking miniaturization to the next level as it
is a fully fledged isolated current transducer including
magnetic concentrators in an IC SO8 size.
• Non-contact, no insertion
losses
• Isolation provider
• Attractive price
• Flexible design to measure
2-70 A RMS
• +5V power supply
• Access to voltage reference
• Ratiometric or fixed gain and
offset
• Standby mode pin
• Dedicated additional fast output
for short circuit detection
• High performance gain and
offset thermal drifts
www.lem.com
At the heart of power electronics
Power Electronics Technology February 2008 20
www.powerelectronics.com
802PET20.indd 20 2/12/2008 9:37:09 AM