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TECHNICAL ARTICLE
Set
H
Reset
H
Figure 1: SR FLIP-FLOP
power up and try to work out their output state. This
becomes more complex as the outputs are fed back to
the inputs. This means that the output is affecting the
input, hence the decision making and hence the output
itself. Confused? Well thats how the gate feels. However
after a few microseconds the gate settles and a stable
state persists.
S R Q
0 0 !
0 1 1
1 0 0
1 1 X
Figure 2: SR TRUTH TABLE
Q
L
Q
H
The truth table for the SR flip-flop is therefore as follows:
The most interesting states are the Set and Reset states
and the Do Nothing state—so remember these for later.
The next thing to add is our clock input, which is done by
adding two more NAND gates to the front end of our SR
circuit. This becomes a gated SR flip-flop. The Set and
Reset still work as before, but as the name suggests, it’s
gated so the output only happens at certain times, when
the clock input is high. This is all very good, however,
it’s possible for the circuit to change its output multiple
times during a clock high, which is not what we want at
all. It’s also not a D-type yet. However, this is easy to fix
by adding a NOT gate between the S and R inputs and
renaming the S input as D (Figure 3).
Our new D-Type works just like the SR flip-flop as it’s
possible to change the output while the clock is high
multiple times during that period. We need a circuit that
only latches in the D signal when the clock edge is rising.
To simplify this to begin with, let’s think about the ability
to generate race conditions—or in this case, a glitch.
If there was only a way to make the clock pulse really
really small on the positive duration, then there would
not be enough time to switch back (Figure 4).
L
Figure 3: D-TYPE FLIP-FLOP
Figure 4: GLITCH CIRCUIT
This circuit uses the idea that it takes time for the gates to
switch. Let’s assume for a moment that the input is LOW.
One side of the AND gate is set to LOW as per the input
and the other is logic HIGH because the NOT gate has
inverted the input. In a perfect world, if the input changes,
the NOT gate would change instantaneously and this
input to the AND gate would swap and the output remain
unaffected. However, because it takes time for the NOT
gate to react and drive the output, there is, in fact, a small
moment in time were both the inputs to the AND gate are
HIGH. This sets off the chain reaction in the gate that will
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H
D
CLK
Q
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L
TECHNICAL ARTICLE